JPH0677239B2 - Memory access controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method in a main memory access processing unit when a data processing apparatus performs multiple access processing by table index access processing.

Here, the table index access method is one in which a main memory device is provided with one or a plurality of index tables, and these index tables are processed once based on one key data, or the obtained index table data is directly or processed. However, this is an access method in which the target data is obtained by successively accessing the main storage device a plurality of times. A process using this method is called a table index access process.

[Conventional technology]

FIG. 3 shows a memory access control method by a conventional table index access process, and FIG. 4 explains an access operation to a main memory.

In FIGS. 3 and 4, reference numeral 10 denotes a main storage device in which one or more index tables are stored. A main memory access processing unit (MAC) 11 controls the table index access processing.

In the MAC 11, reference numeral 12 is a port that stores a processing request, address generation information, write data, and the like. When distinguishing each port, add A, B, C, etc. to distinguish, for example,
It is indicated by port A12A, etc.

A main memory access request circuit (MAD) 13 generates an address and issues an access request to the main memory 10.

An address data register (ADR) 14 stores address data for accessing the main memory device 10. 15 is a read data register (RDR),
The data read from the main storage device 10 is stored.

Reference numeral 16 is a read buffer (RDB), which stores the final data read from the main storage device 10, that is, the data to be output to the lower processing unit that has accessed the main storage device 10, which is provided corresponding to each port. . When distinguishing each RDB,
The ports are distinguished by adding A, B, C, etc., for example, and RDB16 corresponding to the port A12A is indicated by RDB.A16A.

Reference numeral 17 is a work register (WR), which stores the data read from the main storage device 10 when the main storage device 10 is accessed again. When distinguishing each WR, it is distinguished by adding P, Q, etc., and is indicated by, for example, WR / P17P.

Reference numerals 18 and 19 denote selector circuits, and the desired WR17 data is returned to the MAD 13 by these selector circuits. 20
Is a control circuit that controls the operation of each unit to control memory access to the main storage device 10.

In this configuration, when the lower processing unit A of the plurality of lower processing units (for example, channels) accesses the main storage device 10, the table index access processing request and the address data are stored in the port A12A.

When the MAD 13 detects that there is a table index access processing request from the lower processing unit A via the selector circuit 19,
Check that there is a free space on WR17, for example open WR17
Reserve WR / P17P.

Then, an address is generated based on the key data of the address from the port A12A and stored in the ADR14. This address makes the first access to the main memory 10,
Data is read from the index table and stored in RDR15 (Fig. 4 (A)).

The first read data stored in RDR15 is transferred to the reserved WR / P17P.

The control circuit 20 stores that the first read has been completed, and in the case of a table index access request, the read data stored in this WR / P17P is sent to the MAD 13 via the selector circuits 18 and 19. Forward.

The MAD 13 makes a second access to the main storage device 10 from the address indicated by the first read data or by using the address obtained by processing this data, and the data is read from the corresponding index table. Read
It is stored in RDR15 (Fig. 4 (B)).

The second read data stored in RDR15 is WR P17.
After being transferred and stored in P, it is added to MAD 13 via selector circuits 18 and 19.

The MAD 13 reads the data by accessing the main memory device 10 for the third time based on the read data for the second time. Hereinafter, similarly, the address generated based on the data read for the nth time. Thus, the main memory device 10 is accessed, and the process of reading the (n + 1) th data from the corresponding index table is repeated (FIG. 4 (C)).

When all access to the main memory 10 is completed and the data at the desired address is read from the main memory 10, the RDR15
Stored in RDB / A16A via. When the processing operation to the lower processing unit is enabled, the data is transferred to the lower processing unit A.

When there are processing requests to the main storage device 10 from a plurality of lower processing sections at the same time, the MAD 13 checks the vacant WR17 and accepts all the processing requests when the number of processing requests is less than the number of WR17. However, when the number of processing requests is larger than the number of WR17, the processing requests are accepted in descending order of priority. The lower-level processing unit that did not accept the request waits at the port until one of the work registers WR becomes empty.

[Problems to be solved by the invention]

In the conventional table index access method, as described above, the work register WR is provided separately from the read buffer RDB to perform the access processing.

However, in this case, the work registers WR were provided in a smaller number than the read buffers RDB because of the cost and the space.

Therefore, if the table index access processing request frequency is low, there is no problem, but if this processing request frequency becomes high and processing requests from the lower processing units exceed the number of work registers WR, the number of work registers WR The request beyond
There was a problem that the process of reserving the work register WR first had to wait until it was completed. Further, since the work register WR is provided, there is a problem that extra space is required and the cost is increased accordingly.

The present invention solves the above-mentioned problems in the conventional table index access method, has a simplified hardware configuration that does not require a work register, and generates a large number of table index access requests from the lower processing unit. Even so, it is an object of the present invention to provide an improved memory access control system so that all these processing requests can be efficiently multi-processed.

[Means for solving problems]

The present invention is characterized by a octopus configured as follows in order to solve the above-mentioned problems in the conventional tape index access method.

That is, a table index access function for reading data from the main storage device by repeating the operation of accessing the main storage device, using the data read from the main storage device as address information, and accessing the main storage device again. In the memory access control device of the main storage device access processing unit that has multiple access processings, the storage unit that stores the address generation information and the like input from the lower processing unit, and holds the access processing request type A plurality of ports including a processing request type storage unit, an access number storage unit that stores the number of times of access to the main storage device when the processing request type is table index access, and a data buffer that stores data; b) The address is generated based on the address generation information of one of the ports and the access processing request type. Main memory access requesting means for requesting access to the main memory, and (c) the processing request type stored in the processing request type holding unit stores a data register from the main memory. Whether the data read via the processing request is transferred to the processing request source, or when the processing request type is table index access and is used as address information when accessing the main memory again, A plurality of read buffer means corresponding to the port for commonly storing the data; and (d) a control means for controlling the respective means and units to control memory access to the main storage device, wherein the processing request When the processing request type stored in the type holding unit is a table index access request, the read used by the table index access The value of the access count storage section corresponding to the buffer means is updated, and the data recorded in the read buffer means is read and supplied again to the main storage device access request means as address generation information, When the recorded number of accesses becomes equal to the predetermined number of accesses, the data recorded in the read buffer means is transferred to the access request source, and the processing request type stored in the processing request type holding unit is When accessing the main memory instead of the table index access request, control means for controlling to transfer the record data of the read buffer means in which the data read from the main memory is recorded to the access request source. , Is provided.

[Action]

Address generation information input from a plurality of lower processing units that access the main storage device is stored by a plurality of ports. In addition to the address generation information, each port holds the access processing request type in the processing request type holding unit, and when the processing request from the lower-order processing unit is the table index access, the access count storage unit holds the access processing request type. The number of times the main storage device is accessed by the processing request is stored.

One of the plurality of ports is selected, and its address generation information is supplied to the main memory access requesting means together with the access processing request type, the number of times of access to the main memory, and the like.

The main memory access requesting means generates an address based on the input address generation information and the access processing request type, inputs it to the address register, and requests access to the main memory.

The data read from the main memory via the data register is provided in correspondence with the port regardless of whether it is transferred to the processing request source or used as address information when accessing the main memory again. The plurality of buffer means are stored in common.

The control unit for controlling each unit and each unit controls memory access to the main storage device as follows.

In the case of table index access, the access type stored in the processing request type holding unit is
In the case of a table index access request, when the read data is used as address generation information and the main storage device is accessed again after the data is read from the main storage device, the read data is read from the main storage device. The buffer means used at the time of reading is selected, and the read data is supplied to the main memory access requesting means again as address generation information.

At the same time, the value of the access count storage unit corresponding to the buffer means used by the table index access is updated each time the main storage device is accessed.

When the number of accesses recorded in the buffer means becomes equal to the number of accesses, the data recorded in the buffer means is transferred to the access request source.

When it is not a table index access, the access type stored in the processing request type holding unit is
When accessing the main memory instead of the table index access request, the data in the buffer means in which the data read from the main memory is recorded is transferred to the access request source.

As described above, according to the present invention, since the work register and the like are shared with the read buffer, the hardware configuration of the device can be simplified.

Further, even if there are access requests to the main storage device from a plurality of lower processing units, all of the plurality of access requests can be efficiently multiplexed.

Further, since the address is generated by using both the address generation information input from the port and the read data from the main memory device, the main memory device access requesting means accesses the main memory device by the table index method. It is possible to execute the subsequent re-access processing for the main storage device only by the access command without requiring a control signal from the other.

〔Example〕

In the conventional table index access method, as explained in FIG. 3, only the work register WR is used and the read buffer RDB is not used during the table index access processing. When the desired data for the accessed address is read out, it is read out in the read buffer RD.
Stored in B, work register WR is not used.

The present invention pays attention to this fact, and the work register WR and the read buffer used for the table index access processing.
By making RDB common, work registers WR can be deleted, and table index registers (corresponding to work registers) for the number of ports can be secured and all processing requests can be multi-processed. Is.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(A) First Example A first example of the present invention will be described with reference to FIGS. 1 and 4. FIG. 1 is a block diagram illustrating the configuration of the first embodiment.

In FIG. 1, 21 is a main memory access processing unit (MA
C), which controls the entire table index access process.

In the MAC 21, 22A to 22C are ports, and address generation information and the like input from a plurality of lower processing units A to C are stored.

In each of the ports 22A to 22C, 221A to 221C are processing request type holding units, which hold access processing request types. twenty two
2A to 222C are number storage units, and when the processing request from the lower processing units A to C is a table index access, the number of accesses transferred from the lower processing unit and the number of accesses to the main storage device 30 performed by the request. And are recorded.

23 is a main memory access request means (MAD), which inputs one information of the port and generates an address based on the address generation information and the access processing request type,
The number of accesses to the main memory device 30 and the like are input to the address register 24, and a process of requesting access to the main memory device 30 is performed.

Reference numeral 24 is an address data register (ADR), which stores address data for accessing the main storage device 30. A read data register (RDR) 25 stores data read from the main storage device 30.

Reference numerals 26A to 26C are read buffers (RDBs), and the process request types stored in the process request type holding units 221A to 221C are data read from the main storage device 30 via the data register 24. The data stored in the RDR25 is commonly used even when the data is stored in the RDR25, even when the data is stored in the RDR25. It is stored.

Reference numerals 27 and 28 are selector circuits, and these selector circuits return the desired data of the RDBs 26A to 26C to the MAD 23.

29 is a control means for controlling the operation of each means and each part as described in the above [Means for solving the problem] and [Operation]. The main storage device 30 stores one or more index tables.

Next, the operation of FIG. 1 will be described by taking as an example the case where the lower processing unit A of the plurality of lower processing units accesses the main storage device 30 and fetches the data at the desired address. The fourth
The drawings are also referred to in the description of the operation of the present invention.

The access processing request type such as the table index access processing request, the number of accesses, and the address generation information transferred from the subordinate processing unit A are input to the port A22A, the access processing request type is stored in the processing request type holding unit 221A, and the number of accesses is It is stored in the access count storage unit 222A. The access count storage unit 222A includes a memory for recording the access count and a memory for recording the access count, and the memory for recording the access count is initially reset to 0.

When the MAD 23 receives the port information from the lower processing section A via the selector circuit 28 and detects that the access processing request type is the table index access processing request, the address is generated based on the address generation information received from the port A 22A. Is generated and stored in ADR24. In this case, the key data of the address may be used as the address as it is, or may be modified depending on the type of processing request. The access count and the access count received from the access count storage unit 222A are also stored in the ADR 24.

In this way, the main memory device 30 is accessed for the first time by the generated address, the data is read from the index table and stored in the RDR 25 (fourth).
(A). The number of accesses to the main memory device 30 stored in the ADR 24 is also stored in the RDR 25 as read data.

The first read data stored in RDR25 is port A
Stored in RDB / A26A corresponding to 22A.

When there are processing requests from multiple lower-level processing units at the same time,
Multiplexing processing is performed and stored in the buffer means RDB26 for each request source.

When the first read is completed, the control means 29 causes the RDR25
The access type stored in the processing request type holding unit 221A is detected from the read data set in.

If the detected access processing request type is a table index access request, and this read data is used as address generation information to access the main memory device 30 again, the selector circuit 27 causes the RDB / A26A to The first read data is taken out.

Then, using this as address generation information, the selector circuit 28
Control to transfer to MAD23 again via.

Further, the control means 29 updates the access count value of the access count recording unit 222A corresponding to the RDB / A26A used by this table index access by "+1".

Based on this first read data, the MAD23 generates an address in the same manner as described above, accesses the main memory 30 for the second time, reads the data from the corresponding index table, and reads the data from the RDB25 through the RDB25.・ Restore in A26A (Fig. 4 (B)).

In this case, the address for the second access is
The first read data transferred from RDB / A26A may be directly used as the address.
An address generated by modifying this read data by 3 may be used. Further, the address may be generated by the key data and the read data given by the lower processing unit A at the time of processing request. Which method is used to generate the address is determined by the address conversion method used.

The control unit 29 detects the access processing request type from the read data stored in the RDR 25, is a table index access request, and uses this read data as address generation information to access the main storage device 30 again. In this case, the RDB A26A is selected, the read data is supplied again to the MAD 23 as address generation information, and the access count value of the access count recording unit 222A is further updated by "+1".

Thereafter, in the same manner, the process of accessing the main memory device 30 by the address generated based on the data read at the n-th time and reading the data at the (n + 1) -th time from the corresponding index table is repeated ( FIG. 4 (C)).

The control means 29 controls to terminate the table index access when the number of accesses to the main storage device 30 becomes equal to the number of accesses. When all access to the main memory device 30 is completed and the data at the desired address is read, this data is stored in the RDBA 26A. When the processing operation to the lower processing unit is enabled, it is transferred to the lower processing unit A which is the request source.

The above is the memory access control operation in the case of the table index access processing. However, when the access type stored in the processing request type holding unit 221A is not the table index access request but accesses the main storage device 30, The address generation information of the plurality of ports 22A is supplied to the MAD 23.

The MAD 23 generates an address based on this address generation information and accesses the main storage device 30.

The data read from the main memory 30 is the port 22A.
To 22C corresponding to the buffer means 26A to 26C, and controlled to be transferred to the access request source.

The above is a description of the case of accessing the main memory device 30 to read the data, but in the case of writing, the address in the main memory device 30 for storing the data is obtained by the above-mentioned table index access method or the like. At that time, the write data is taken out from the write buffer section of the port A22A and stored at a predetermined address in the main memory device 30.

(B) Second Embodiment In the second embodiment of the present invention, the read buffer RDB and the write buffer at the port 22 are made common in the first embodiment shown in FIG. It has been improved so as to simplify.

Hereinafter, another embodiment will be described with reference to FIG. Second
The figure shows the configuration of the second embodiment of the present invention.

In FIG. 2, 30 is the same main memory as in FIG.
Reference numeral 31 is a main memory access processing unit (MAC). Less than,
Similarly, the same name and abbreviated reference numerals are given to the structure corresponding to the first embodiment shown in FIG. 1 for explanation.

In the MAC 31, 32 is a port, the processing request type holding unit 321 that stores the access processing request type, and the main storage device 3
An access count storage unit 322 that stores the access count and access count to 0, an address unit 323 that stores address generation information, a data buffer unit 324 that stores write data or read data, and a processing flag is set. The processing flag unit 325 is provided. When distinguishing each port and each part, as in the case of Fig. 1, A, B, C
Are marked to distinguish.

33 is a main memory access request circuit (MAD). MAD33
3, a port input register (PIR) 331 includes an access count storage unit 322 for the port 32 and a processing request type storage unit 3
21, the address section 323 and the data buffer section 324 are provided with a count section for storing data, a processing request section, an address section and a data section. The data portion stores the data portion used for address generation from the data in the data buffer portion 324 of the port 32.

A processing control circuit 332 generates an access count from the processing request data, stores the access count of the access count record data, and generates a main memory access processing code for instructing what kind of access processing is to be performed. An address generation circuit 333 generates an address for accessing the main storage device 30.

Reference numeral 34 is an address data register (ADR), which stores various data when accessing.

In this ADR34, 341 is a processing control information register (PCI
R), which has a number-of-times section for storing the number of accesses and the number of accesses generated in the processing control circuit and a MAP code section for storing a main memory access code (MAP code).
An address register 342 stores the generated address. A data register 343 stores data at the time of writing.

A read data register (RDR) 35 stores data read from the main storage device 30. This RD
In R35, 351 is a processing control information register (PCIR), which has the same configuration as PCIR341. A data register 352 stores the read data.

A main memory access post-processing circuit (MAPPC) 36 controls the next process to be executed based on the number of accesses, the number of accesses, and the access process code. A processing order control circuit 37 controls the processing order of each port of the port 32.

The MAPPC 36 and the processing order control circuit 37 correspond to the control means 29 in the first embodiment shown in FIG.

38, 39, 40 are selection circuits, which include a processing flag, the number of accesses,
Select the port to set the access count and read data. 41 and 42 are selector circuits, and 43 to 45 are AND
Circuit.

Next, the operation of FIG. 2 will be described. The access processing request type and the address generation information from the lower processing unit are port 32.
Are stored in the processing request type holding unit 321 and the access count storage unit 322, and finally the processing flag is stored in the processing flag unit 325. At this time, the number of accesses of the access number storage unit 322 is reset to zero in the recording memory.

The processing order control circuit 37 determines the processing order according to the processing flag of each port of the ports 32. Now, assuming that port A32A is selected, the access count storage unit 32 of port A32A
2. Each data from the processing request branch holding unit 321, the address unit 323, and the data buffer unit 324 is stored in the corresponding frequency unit, processing request unit, address unit, and data unit of the PIR 331 via the selector circuit 41. To be done. Initially, the contents of the frequency part and the data part are zero.

The processing control circuit 332 generates a MAP code for instructing access processing to the main storage device 30 and the number of accesses according to the input number of accesses and the content of the processing request type, and outputs P
It is stored in the corresponding frequency part and main memory processing code part of CIR341.

On the other hand, the address generation circuit 333 generates an address for accessing the main storage device 30 based on the key data of the address part of the PIR 331 in the same manner as in the case of FIG. 1, and stores it in the address register 342.

The main memory device 30 accesses the index table according to the data from the PCIR 341 and the address register 342, reads the data at the predetermined address, and stores it in the data register 352. On the other hand, the count data and the MAP code of the PCIR 341 are directly stored in the corresponding units of the PCIR 351 without being changed.

The MAPPC 36 determines, based on the access count and the access count MAP code, whether the main storage device 30 needs to be reaccessed, the read data should be transferred to the lower processing unit, or the write operation should be performed. Control the process. That is, in table index access, if the access count is not equal to the access count, re-access is performed. If the access count is equal to the access count, or if it is not the table index access, transfer of the read data to the lower processing unit, and table index access In the case of access and data writing, when the subtracted value of the number of accesses from the number of accesses becomes 1, the data is controlled to be written in the next access.

When re-access to the main storage device 30 is required, the selection circuits 38 to 40 are controlled so that the access count of the PCIR 351 is stored in the access count storage section 322A of the port A32A in the data register.
After storing the data of 352 in the address section 323A of the port A32A, the data buffer section 324A, or both, the processing flag is stored in the processing flag section 325A.

Thereafter, the second access to the main storage device 30 is performed in the same manner as the first access described above. And the main storage device 30
The access process is repeated a predetermined number of times until the access to all is completed.

When all accesses to the main storage device 30 have been completed, if MAPPC36 is a read processing request, the MAPPC 36 sends data to the data register 352.
The data read out is stored once in the data buffer unit 324A of the port A32A. Then, when the processing operation to the lower processing unit A becomes possible, for example, when a predetermined amount of read data is completed, the data is transferred to the requesting lower processing unit A via the AND circuit 43.

In the case of a write processing request, the write data from the data buffer unit 324A of the port A32A is stored in a predetermined address of the main storage device 30 via the selector 42 and the data register 343. Then, when the processing operation to the lower processing unit A is possible, for example, when a predetermined amount of data is stored, an end signal is output.

Although the above description of each embodiment has been made by taking the lower processing unit A as an example, even if there is a processing request from another lower processing in parallel, the ports of each lower processing unit are used and all processing is performed by multiple processing. The processing request from the lower processing unit can be executed. The number of the ports 32 is not limited to three, and a plurality of ports 32 corresponding to the lower processing units are provided. Therefore, each lower processing unit can access the main storage device 30 without waiting.

〔The invention's effect〕

As described above, according to the present invention, the following effects can be obtained by including the respective configurations described in (a) to (d) of the claims.

(B) Since the work register and the like are shared with the read buffer, the hardware configuration of the device can be simplified.

(B) Even if there are access requests to the main storage device from a plurality of lower processing units, all of the plurality of access requests can be efficiently multiplexed.

(C) Since an address is generated using both the address generation information input from the port and the read data from the main memory, the main memory access requesting means accesses the main memory by the table index method. ,
It is possible to execute the subsequent re-access processing for the main storage device only by the access command without requiring a control signal from the other. "

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of another embodiment of the present invention, FIG. 3 is an explanatory diagram of a conventional memory access control method by table index access processing, and FIG. The figure is an illustration of an access operation in the main memory. In FIGS. 1 and 2, 30 ... Main storage device, 21, 31 ... Main storage device access processing unit (MAC), 22, 32 ... Port, 23, 33 ... Main storage device access request circuit ( MAD), 24,34 …… Address data register (ADR), 25,35 …… Read data register (RDR), 26 …… Read buffer (RDB), 27,28,41,4
2 ... Selector circuit, 29 ... Control means, 221, 321, ... Processing request type holding unit, 222,322 ... Access count storage unit, 36
...... Main memory access post-processing circuit (MAPPC), 37 …… Processing order control circuit, 38-40 …… Selection circuit, 43-45 …… AND circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-53-102635 (JP, A) JP-A-50-141225 (JP, A) JP-A-59-148967 (JP, A) JP-A-59- 8057 (JP, A)

Claims (2)

[Claims] 1. A table for reading data from a main memory by repeating a plurality of operations of accessing the main memory and using the data read from the main memory as address information to access the main memory again. In a memory access control device of a main storage device access processing unit having an index access function and performing access processing in a multiplexed manner, (a) a storage unit for storing address generation information and the like input from a lower processing unit, an access processing request type A plurality of ports including a processing request type holding unit that holds the number of times, an access number storage unit that stores the number of times of access to the main storage device when the processing request type is table index access, and a data buffer that stores data. (B) An address is generated based on the address generation information of one of the ports and the access processing request type. Main memory access requesting means for requesting access to the main memory, and (c) the processing request type stored in the processing request type holding unit stores a data register from the main memory. Whether the data read via the processing request is transferred to the processing request source, or when the processing request type is table index access and is used as address information when accessing the main memory again, A plurality of read buffer means corresponding to the port for commonly storing the data; and (d) a control means for controlling the respective means and units to control memory access to the main storage device, wherein the processing request When the processing request type stored in the type holding unit is a table index access request, the read used by the table index access The value of the access count storage section corresponding to the buffer means is updated, and the data recorded in the read buffer means is read and supplied again to the main storage device access request means as address generation information, When the recorded number of accesses becomes equal to the predetermined number of accesses, the data recorded in the read buffer means is transferred to the access request source, and the processing request type stored in the processing request type holding unit is When accessing the main memory instead of the table index access request, control means for controlling to transfer the record data of the read buffer means in which the data read from the main memory is recorded to the access request source. A memory access control device comprising: 2. The memory access control device according to claim 1, wherein the plurality of read buffer means are shared as a data buffer in the port.