JPH0297063A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a simply structured memory cell without using a capacitor and to obtain a semiconductor device which is small in cell area and capable of executing a memory function sufficiently by a method wherein a second MOS transistor is formed on a single crystal semiconductor layer formed on a first MOS transistor through the intermediary of an insulating film and other processes are executed. CONSTITUTION:A first MOS transistor is formed on a primary face of a semiconductor substrate 10, highly concentrated impurity diffusion regions 24 and 25 are provided apart from a single crystal semiconductor layer 20 by a specified distance, where the layer 20 is formed on the first MOS transistor through the intermediary of insulating films 11, 12, and 16, and a second MOS transistor, provided with an electrode 23 formed on a channel region which is sandwiched in between the diffusion regions 24 and 25, is provided. And, the channel region of the above second MOS transistor is arranged just above an impurity region 14 of the impurity regions of the first MOS transistor, and the thickness of a semiconductor layer of the second MOS transistor channel region is so set as to enable the channel region to be completely depleted when the second MOS transistor is in operation.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device having a memory function, and in particular, to a semiconductor device having a memory function, and particularly to a transistor memory using a silicon film (SOI film) on an insulating film. Regarding the semiconductor device created.

(Prior Art) Various structures have been developed for semiconductor memory, but the simplest structure is DRA, in which one memory cell consists of one transistor and one capacitor.
It is an M cell. This memory cell typically has a structure in which a capacitor section is provided next to a transistor as shown in FIG. In addition, 40 in the figure is a silicon substrate;
1 is an insulating film for element isolation, 42 is a gate oxide film, 43 is a gate electrode, 44.45 is an n-type diffusion layer (source/drain region), 46 is an n-type diffusion layer, 47 is a capacitor electrode, 4
8 indicates an interlayer insulating film.

However, this type of semiconductor device has the following problems. That is, in order to increase the memory capacity, it is necessary to miniaturize the element, but since the capacitor capacitance must be greater than a certain level, the area of the capacitor section cannot be made much smaller. In other words, the area of the capacitor portion has been a factor that hinders the fineness of the element. In addition, since the charge accumulated in the capacitor section is gradually discharged, a refresh operation is required at regular intervals.In this way, in conventional memory cells consisting of one transistor/one capacitor, the area of the capacitor section is small. This is a factor that hinders the miniaturization of devices, making it difficult to reduce the cell area. Also, a refresh operation is required,
Extra for that.

A suitable circuit must be provided.

The present invention has been made in consideration of the above circumstances, and its purpose is to realize a memory cell with a simple configuration without using a capacitor, and to have a small cell area and sufficient memory function. The objective is to provide a semiconductor device that fulfills the following requirements.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a thin film transistor directly above the source region of a normal MOS transistor, uses the lower transistor as a writing transistor, and changes the threshold voltage of the upper transistor. This allows it to have a memory function.

That is, the present invention provides a semiconductor device in which a memory cell is configured using a transistor, in which high concentration impurity diffusion regions are provided on one main surface of a semiconductor substrate at a predetermined distance apart, and
A first MOS transistor in which a gate electrode is provided on a channel region sandwiched between the diffusion regions via a gate insulating film, and a single crystal semiconductor layer formed on this transistor via an insulating film are separated by a predetermined distance. and a second MOS transistor in which a high concentration impurity diffusion region is provided, and a gate electrode and a pole are provided on a channel region sandwiched by the diffusion region via a gate insulating film, and the second MOS transistor a channel region of the transistor is arranged directly above one of the impurity diffusion regions of the first transistor;
The thickness of the semiconductor layer in the channel region of the transistor is set to be less than or equal to the thickness at which the channel region is completely depleted in the operating state of the transistor.

(Function) According to the present invention, the write transistor (first MOS
By applying voltage to the gate and drain of a transistor (transistor), the potential of the source part can be increased. In the readout transistor (second MOS transistor) formed on this layer, the thickness of the semiconductor layer in the channel region is thinner than the maximum depletion layer width generated by applying the gate voltage, so the gate voltage is applied to the lower insulating film. It's getting easier. Therefore, when a gate voltage is applied to the read transistor, the potential of the entire semiconductor layer increases. As a result, the threshold value of the read transistor changes depending on the potential of the source of the write transistor. That is, when data is written, the source potential of the write transistor becomes high, and the threshold value of the read transistor becomes lower than when data is not written. By using this function, it can be made to function as a transistor memory.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. In the figure, reference numeral 10 denotes a p-type single-crystal silicon substrate, and an
+ impurity diffusion layers (source/drain regions) 14 and 15 are formed.

A gate electrode 13 is formed on the channel region between the source and drain regions 14 and 15 with a gate oxide film 12 interposed therebetween. Here, a first MOS transistor is constituted by the gate electrode 13, source/drain 14, 15, etc.

Further, on the first MOS transistor, a single crystal silicon layer (So
1 film) 20 is formed. This silicon layer 20 has a source/drain region 2 similar to a write transistor.
4.25 are formed, and further source/drain regions 24
．． A gate electrode 23 is formed on the channel region between the gate electrodes 25 with a gate oxide film 22 interposed therebetween. Here, the second MO
An S transistor is configured.

Note that the channel region of the second Mo3 transistor is
It is arranged directly above the source region 14 of the MOS transistor. Further, the thickness T of the silicon layer 20 in the channel region of the second MOS transistor is
The film is thinned so that the channel region is completely depleted in the operating state of the transistor. In other words, the thickness T of the silicon layer 20 is T≦[2ε φF/(qNsub)
It is set to l/2. However, φF is Fermi energy (eV), and φF − (kT/q) log (Nsub /N
i). In addition, N5ub is the impurity concentration (Cffl-3) of the silicon layer 20, ε is the dielectric constant, q is the fundamental charge of electrons (coulombs), k is Boltzmann's constant, and T is the temperature (K).
, Ni indicates the intrinsic carrier concentration.

FIG. 2 is a sectional view showing the manufacturing process of the semiconductor device.

First, as shown in FIG. 2(a), a p-type silicon substrate 10
An insulating film 11 for element isolation is formed by selectively oxidizing the surface. Subsequently, as shown in FIG. 2(b), a gate electrode 13 made of polysilicon is formed through the gate oxide film 12 in the same manner as in the normal Mo3 transistor manufacturing process, and then phosphorous is formed using the gate electrode 13 as a mask. ion implantation, n+
A type scattering layer source/drain region) 14 and 15 are formed. The first MOS transistor is formed through the steps up to this point.

Next, as shown in FIG. 2(c), the gate electrode 13 is oxidized to form an insulating film 16. Subsequently, as shown in FIG. 2(d), after forming an opening 17 to serve as a seed in the element isolation oxide film 11, a polysilicon film 1 is formed over the entire surface by CVD.
8 to a thickness of about 1,500. Thereafter, the polysilicon film 18 is melted and recrystallized by annealing using an electron beam or a laser beam, and selectively etched except for necessary portions. Furthermore, boron ions were implanted into this single crystallized film (Sol film) to make lX1016CI11-3
A p-type single crystal silicon layer 20 having a concentration of .

Next, as shown in FIG. 2(e), the surface of the silicon layer 20 is oxidized to form a gate oxide film 22. Thereafter, the structure shown in FIG. 1 is realized by forming a gate electrode 23 and then implanting phosphorus ions to form a source and drain to form a second MoS transistor.

Note that although an electron beam or a laser beam is used to obtain the Sol film in the above process, solid phase epitaxial growth may be used in order to avoid thermal damage to the underlying element. To this end, after opening the opening 17, an amorphous silicon film of 1,500 layers is deposited in place of the polysilicon film in a high vacuum, and heat treated at 600°C. As a result, single crystal silicon grows from the opening 17. The subsequent steps are the same as above.

In the semiconductor device thus manufactured, the first MOS
When a voltage is applied to the gate electrode 13 and drain region 15 of the transistor, the transistor is turned on and the potential of the source region 14 increases.

When the potential of the source region 14 increases, the potential of the channel region of the second MOS transistor increases, and the threshold value of the transistor decreases. Note that even if the voltage application to the gate electrode 13 and the drain region 15 is stopped, the potential of the source region 14 in a floating state remains unchanged.

In this state, the gate electrode 2 of the second MOS transistor
When a voltage is applied to transistor 3, a current flows between the source and drain regions 24 and 25 of the transistor. At this time, the voltage V applied to the gate electrode 23 is set to the original threshold value Vl.
and the threshold value V2 when the potential of the source region 13 is high, the second MOS transistor
The drain current of the transistor changes. In other words, the first MOS transistor is used for writing, and the second MOS transistor is used for writing.
By using an OS transistor for reading,
Transistor memory will be realized. Note that the source potential of the first MOS l-transistor is the same as that of the second MOS transistor.
The second element that affects the channel potential of the transistor is
This is because the thickness of the semiconductor layer 20 forming the MOS transistor is set to the value shown by the above formula.

Thus, according to this embodiment, a transistor memory can be realized by using the first MOS transistor for writing and the second MOS transistor for reading. In this case, there is no need to provide a capacitor section, and the area of one cell can be reduced. Further, refreshing is not required, and it can be used as a static RAM with an extremely simple configuration of two MOS transistors.

Note that the present invention is not limited to the embodiments described above. For example, when manufacturing the first MOS transistor, as shown in FIG. 3, by providing a recess in the substrate in the area where the gate electrode is provided, it is possible to avoid thinning of the drain region of the second MOS transistor. . Furthermore, by actively utilizing this idea, the second MOS
The channel region is set to the value shown by the above formula by thickening the portion of the transistor other than the channel region,
The source/drain regions can be made much thicker than this. This makes it possible to reduce the resistance of the source/drain diffusion regions. Furthermore, the conductivity types of the substrate, semiconductor layer, and diffusion layer are not limited to the same as those in the embodiments, and can be changed as appropriate according to the specifications.In short, as long as the upper and lower elements function as MOS transistors, good. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, a thin film transistor is provided directly above the source region of a normal MOS transistor,
Using the lower transistor as a writing transistor,
A memory function can be provided by changing the threshold voltage of the upper transistor. For this reason,
A memory cell can be configured without using a capacitor section, and a semiconductor device with a small cell area and a sufficient memory function can be realized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the same embodiment, and FIG. 3 is a cross-sectional view showing a modification of the present invention. Figure, 4th
The figure is a sectional view showing a schematic configuration of a conventional device. DESCRIPTION OF SYMBOLS 10... P-type silicon substrate, 11... Insulating film for element isolation, 12.22... Gate oxide film, 13.23...
・Gate electrode, 14, 15, 24.25... n+ type scattering layer source/drain region), 16... Insulating film, 1
7... Opening portion, 18... Polycrystalline silicon film, 20...
...P-type car crystal silicon layer. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 4

Claims (2)

[Claims] (1) A first method in which high concentration impurity diffusion regions are provided on one main surface of a semiconductor substrate at a predetermined distance apart, and a gate electrode is provided on a channel region sandwiched between the diffusion regions via a gate insulating film. A high concentration impurity diffusion region is provided at a predetermined distance in a MOS transistor and a single crystal semiconductor layer formed on the transistor via an insulating film, and
a second MOS transistor in which a gate electrode is provided on a channel region sandwiched between the diffusion regions via a gate insulating film, and the channel region of the second MOS transistor is connected to the impurity diffusion region of the first transistor. The second MOS transistor is disposed directly above one of the regions, and the thickness of the semiconductor layer in the channel region of the second MOS transistor is set to be less than or equal to the thickness at which the channel region is completely depleted in the operating state of the transistor. semiconductor device. (2) The semiconductor device according to claim 1, wherein the thickness T of the semiconductor layer in the channel region of the second MOS transistor is T≦[2εφF/(qNsub)]^1^/^2. . However, Nsub is the impurity concentration of the semiconductor layer (cm^-^3), ε is the dielectric constant, and q is the basic charge of electrons (
Coulomb), φF is Fermi energy (eV).