KR0163759B1 - Semiconductor device and semiconductor memory device - Google Patents

Abstract

None.

Description

Semiconductor Device and Semiconductor Memory Device

1 is a perspective view showing a semiconductor device in accordance with an embodiment of the present invention.

2A to 2G are sectional views showing the manufacturing process of the semiconductor device shown in FIG. 1 and similar semiconductor devices.

3A is a plan view showing a semiconductor device in accordance with an embodiment of the present invention.

3B and 3C are cross-sectional views of the semiconductor device shown in FIG. 3A.

4A is a plan view showing a semiconductor memory device according to the embodiment of the present invention.

4B is a cross-sectional view taken along the line b-b 'of the semiconductor memory device shown in FIG. 4A.

4C is a plan view showing a modification of the semiconductor memory device shown in FIG. 4A.

FIG. 4D is a cross-sectional view of the semiconductor memory device shown in FIG. 4C.

FIG. 4E is a cross-sectional view showing another modification of the semiconductor memory device shown in FIG. 4A.

5 is a cross-sectional view showing a semiconductor memory device in accordance with an embodiment of the present invention.

6A, 6B, 6BB, 6C, 6CC, 6D, and 6E are sectional views showing the manufacturing process of the semiconductor memory device shown in FIG.

7A is a plan view showing a semiconductor memory device according to the embodiment of the present invention.

7B and 7C are cross-sectional views of the semiconductor memory device shown in FIG. 7A.

8 is a plan view showing a semiconductor memory device according to the embodiment of the present invention.

9A is a plan view showing a semiconductor memory device according to the embodiment of the present invention.

9B and 9C are cross-sectional views of the semiconductor memory device shown in FIG. 9A.

10A and 10B are sectional views showing the manufacturing process of the semiconductor memory device shown in FIGS. 9A to 9C.

10C is a cross-sectional view showing a modification of the semiconductor memory device shown in FIGS. 9A to 9C.

Fig. 11A is a plan view of a semiconductor memory device in the embodiment of the present invention.

11B and 11C are cross-sectional views of the semiconductor memory device shown in FIG. 11A.

12 is a plan view of a semiconductor memory device according to the embodiment of the present invention.

13A and 13B are sectional views showing the manufacturing process of the semiconductor memory device shown in FIG.

14A is a plan view of a semiconductor memory device according to the embodiment of the present invention.

14B and 14C are cross-sectional views of the semiconductor memory device shown in FIG. 14A.

FIG. 14D is a plan view showing a modification of the semiconductor memory device shown in FIG. 14A.

Fig. 15A is a plan view of a semiconductor memory device according to the embodiment of the present invention.

FIG. 15B is a sectional view of the semiconductor memory device shown in FIG. 15A.

16A is a plan view of a semiconductor memory device according to the embodiment of the present invention.

FIG. 16B is a sectional view of the semiconductor memory device shown in FIG. 16A.

17A is a plan view of a semiconductor device in accordance with the embodiment of the present invention.

FIG. 17B is a sectional view of the semiconductor device shown in FIG. 17A.

FIG. 17C is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 17A.

18A is a plan view of a semiconductor device in accordance with the embodiment of the present invention.

FIG. 18B is a cross-sectional view taken along the line A-A 'of the semiconductor device shown in FIG. 18A;

19 is a planar layout view of a semiconductor device in accordance with an embodiment of the present invention.

20A and 20B are cross-sectional views taken along line A-A 'and B-B' of the semiconductor device shown in FIG. 19, respectively.

21A is a planar layout view of a field effect transistor in the prior art.

FIG. 23B is a cross-sectional view of the field effect transistor shown in FIG. 21A.

Fig. 22 is a sectional view of a field effect transistor in another prior art.

Fig. 23A is an equivalent circuit diagram of a semiconductor memory device in the embodiment of the present invention.

23B and 23C are cross-sectional views of the semiconductor memory device shown in FIG. 23A.

Fig. 24A is an equivalent circuit diagram of a semiconductor memory device in the embodiment of the present invention.

24B is a planar layout view of the semiconductor memory device shown in FIG. 24A.

24C is a cross-sectional view of the semiconductor memory device shown in FIG. 24A.

25 is a perspective view showing a charge coupling device in an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10 substrate 11 well

19: active area 20: insulating layer

21: insulating film 25: field oxide film

30, 32, 32 ': gate electrode 30': polycrystalline silicon

31, 31 ': word line 40: source electrode

40 ': Source wiring 41: Capacitive portion

45, 55: low concentration impurity layer 50: drain electrode

51: power line 60 ': plate electrode

61: n ⁺ buried layer 80: bit line

90 capacitor insulating film 91 gate insulating film

96: trench 100, 101: semiconductor layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and semiconductor memory devices having insulated gate field effect transistors.

A conventional MOS field effect transistor (hereinafter referred to as MOSFET) will be described with reference to the drawings. A representative structure is shown in a planar arrangement in Fig. 21A, and a cross-sectional structure by this A-A 'cross section is shown in Fig. 21B.

In this device, the active region 19 is separated by forming a thick insulating film 21 around the active region 19 used as a channel, source and drain electrode, and a gate insulating film is formed in the active region 19. The gate electrode 30 is formed, and the source electrode 40 and the drain electrode 50 are formed in a self-aligned manner by an ion implantation method using the gate electrode 30 as a mask. When the device is integrated on the same substrate, electrical separation is performed by separation of the active region performed by the insulating film 21 made of an oxide film. By securing a sufficient thickness in comparison with the gate insulating film in forming the oxide film, even if an operating voltage is applied to the gate, the portion coated on the oxide film can be kept in an inactive state. In order to grow this oxide film, oxidation is usually carried out in a wet (wet) atmosphere to grow the oxide film to a sufficient film thickness. Such oxidation is called field oxidation, and the grown oxide film is called field oxide film. Hereinafter, this term is also used here.

Increasing the degree of integration in the device has a problem that, for example, if the device spacing indicated by x in the figure is shortened, a current easily flows under the field insulating film 21 indicated by an arrow in the figure.

In order to eliminate such unnecessary current passage, a silicon on insulator (SOI) substrate structure in which an insulating film 20 is provided under the channel shown in FIG. 22 is considered. The FET formed on this insulator is discussed in IEEE Electron Device Letter (vol. 9, No. 2, pp. 97-99, 1988. 2).

In this structure, a transistor is formed on the substrate 10 having the silicon oxide layer formed by ion implantation as the insulating layer 20 therein. The transistor attaches a gate insulating film on the semiconductor on the substrate surface, forms the gate electrode 30, and then forms the source electrode 40 and the drain electrode 50 in a self-aligned manner using an ion implantation method for the gate. Manufacture. This transistor has the same structure as the conventional MOSFET structure shown in Fig. 21A in planar arrangement.

As a feature of the structure shown here, the thickness d of the silicon on the insulating film 20, i.e., the thickness of the channel is set to a thin film of about 0.1 mu m or less. In the structures shown in Figs. 21A and 21B, the electric field effect of the gate is less likely inside the substrate away from the gate. On the other hand, in the structure shown in FIG. 22, the area | region where such an electric field effect is hard to replace is replaced with the insulator. Therefore, better control of device operation can be performed on the gate.

In the above structure of the prior art, since there is a relationship of I∝W between the amount of current I flowing through the device and the channel width W, there is a problem that I decreases when W is made small. Therefore, the planar dimension cannot be reduced without reducing the amount of current.

This is also a semiconductor memory device (e.g., SRAM) formed by combining the semiconductor device of the prior art, or a semiconductor memory device (e.g., formed by the combination of the capacitor device which is another semiconductor element with the semiconductor device of the prior art (e.g., For example, even in the case of DRAM, there is a restriction that the planar dimension cannot be reduced.

It is an object of the present invention to provide a semiconductor device and a semiconductor memory device suitable for high integration.

[1] A semiconductor device having a field effect transistor comprising a source electrode and a drain electrode provided on a substrate, and a gate electrode having a field effect between the source electrode and the drain electrode and a channel having an insulating film in the channel. Wherein the channel is provided in a semiconductor layer at least a portion of which is substantially perpendicular to the substrate, and the direction of the current flowing in the channel is substantially parallel to the substrate. [2] The channel of the field effect transistor is [1] The semiconductor device of the above-mentioned [1], wherein the channel is substantially insulated from the substrate, wherein an insulating layer is disposed between at least a portion of the substrate in a direction perpendicular to the substrate. [1] The semiconductor device of the above-mentioned [1], wherein a charge coupling portion and an insulating film are attached to the charge coupling portion on a substrate. A semiconductor device having a charge coupling device having a plurality of gate electrodes acting thereon, wherein at least a portion of the charge coupling portion is provided in a semiconductor layer approximately perpendicular to the substrate, and the direction of charge transfer in the charge coupling portion is determined by the substrate. A semiconductor device, characterized in that substantially parallel, [5] having at least two transistors on a substrate, wherein at least one of the transistors has a source electrode, a train electrode, a channel, and a gate electrode having an electric field effect through the lead film in the channel; A semiconductor memory device having a field effect transistor, wherein the channel of the field effect transistor has at least a portion thereof disposed substantially perpendicular to the substrate between the source electrode and the drain electrode, and the current direction in which the channel flows is approximately parallel to the substrate. [6] The channel is a semiconductor memory device characterized in that the substrate and A semiconductor memory device according to the above [5], wherein a source electrode and a drain electrode are provided on the substrate, and between the source electrode and the drain electrode, and a channel and the channel are insulated from each other. A semiconductor device having at least two field effect transistors having a gate electrode having a field effect, wherein each channel is provided in a semiconductor layer at least partially of which is substantially perpendicular to the substrate, and at least one gate electrode of the transistors. [8] A semiconductor device comprising: a source electrode and a drain electrode provided on a substrate; and a channel disposed between the source electrode and the drain electrode; and a gate electrode having an electric field effect through the channel through an insulating film. A semiconductor device having at least one field effect transistor and at least one capacitance And the channel is provided in a semiconductor layer at least a portion of which is substantially perpendicular to the substrate, wherein a current direction flowing in the channel is substantially parallel to the substrate. The semiconductor memory device described in [8] above is substantially insulated from the semiconductor memory device.

In the present invention, the channel is preferably substantially insulated from the substrate. What is practical here is that even if it is not completely insulated, it has almost the same effect as the case where it is insulated in its operating voltage. In addition, the semiconductor layer substantially perpendicular to the substrate is preferably a thin film.

The thickness of the semiconductor layer substantially perpendicular to the substrate is 0.2 탆 or less, more preferably 0.1 탆 or less, even more preferably 0.05 탆 or less. The lower limit of the thickness is considered to be about the thickness of the gate insulating film because the semiconductor device has a structure of a field effect transistor having a gate electrode passing through the insulating film. In the current state of the art, the thickness of the gate insulating film is considered to be the limit of 3 nm due to problems such as voltage resistance. Therefore, the lower limit of the thickness of the semiconductor layer which is approximately perpendicular to the substrate is about 3 nm in the state of the art.

The higher the semiconductor layer, which is substantially perpendicular to the substrate, is preferable because the higher the current flowing through the channel, the higher the limit is. That is, for example, when a semiconductor layer perpendicular to this is formed by etching the substrate, when the silicon substrate is dry-etched with a selectivity of 100 using a SiO ₂ film having a thickness of 10 nm as a mask, the height of the formed semiconductor layer is 1 μm. can do. The lower limit of the height of the semiconductor layer does not exist in particular, and if it protrudes from the substrate surface to some extent, it is effective in its own way. For example, even if the height is 0.2 µm, it has sufficient characteristics.

In addition, the semiconductor layer is preferably provided perpendicular to the substrate surface, but in many cases the cross section of the semiconductor layer cut in a plane perpendicular to the semiconductor layer and the substrate becomes a trapezoid that becomes thicker as it approaches the substrate surface. The angle formed between the substrate surface and the trapezoidal sides intersecting the substrate surface (that is, the angle formed between the substrate surface and the semiconductor side surface) may be 80 ° or more. When this angle is less than 80 degrees, the effect of this invention is reduced and it is unpreferable.

The semiconductor layer substantially perpendicular to the substrate may be of the same material, impurity concentration, and conductivity type as the channel portion and sides of the conventional field effect transistor.

In the FET of the present invention in which a channel is provided in a semiconductor layer substantially perpendicular to the substrate, and the direction of the current flowing in the channel is substantially parallel to the substrate, the channel width for determining the amount of current is increased by increasing the height of the semiconductor layer. You can do it. Therefore, the current amount can be maintained and the planarized FET can be maintained by securing the height of the semiconductor layer without impairing the thin film channel effect of obtaining good electrical characteristics by the gate.

Further, even in the semiconductor memory obtained by combining this FET with other elements, the FET portion can be miniaturized, so that the overall miniaturization can be achieved.

In the semiconductor device and the semiconductor memory device of the present invention, at least a portion of the channel or charge coupling portion is provided in a semiconductor layer approximately perpendicular to the substrate, and required electrodes and necessary insulating layers of the source, drain, and gate electrodes are added to the semiconductor layer. Other than what is said, you may use the knowledge of the prior art of this field.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated with an Example.

In addition, in all the figures for demonstrating an Example, the same code | symbol is attached | subjected to the thing which has the same function, and the repeated description is abbreviate | omitted.

Example 1

1 is a device structure diagram showing features of the present invention. The thin film semiconductor layer provided perpendicular to the substrate is separated from the substrate 10 by the insulating layer 20. The gate electrode 30 surrounds the thin film semiconductor layer with the gate insulating film 91 interposed therebetween. The thin film portion not covered by the gate is a source electrode 40 and a drain electrode 50 which are activated by introducing impurities at a high concentration, and the thin film semiconductor layer coated by the gate therebetween opens channels in a direction parallel to the substrate surface. Configure. Since the channel is surrounded by the insulating layer 20 and the gate insulating film 91, the channel is electrically separated from the substrate 10.

The gate electrode 30 exerts an electric field effect on the channel via a gate insulating film 91 made of silicon oxide having a thickness of 10 nm, and performs a three-terminal field effect transistor operation by the source electrode 40 and the drain electrode 50.

Gm mutual conductance, capacitance of C _G the gates of the devices, when the load capacitance consisting of a C _D mainly diffusion capacity, between the maximum operating frequency f _o and their value in the MOSFET, the f _o α Gm / C _G + There is a tube that is C _D. In the semiconductor device according to the present invention, the Gm becomes large and the C _D can be made very small due to the electric field effect of the gates on both sides, so the maximum operating frequency f _o can be increased. For this reason, the semiconductor device of the present invention is suitable as an element constituting a logic circuit operating in a high clock cycle or communication requiring high speed operation.

This structure can be similarly manufactured in a P-type channel transistor and an N-type channel transistor. Here, a method of forming an N-type channel transistor will be described using FIGS. 2A to 2G. 2a, 2b, 2c and 2e show the C-C 'cross section of FIG.

The process shown in FIG. 2A; The surface of the P-type silicon substrate is thermally oxidized to form a silicon oxide film 151 of about 20 nm, and the silicon nitride film 701 is deposited by about 20 nm by CVD (Chemical Vapor Deposition). A semiconductor layer 100 having a thickness of 0.1 μm is formed by patterning in a line shape, using the mask as a mask, and etching the substrate about 1 μm vertically by the Reactive Ion Etching (RIE) method and vertically providing the substrate. do. This patterning may be performed by a silicon oxide film instead of a photoresist film. Hereinafter, the layer which uses the one part provided perpendicularly to the board | substrate in this way as a channel is called a semiconductor layer.

At this time, if the thickness of the semiconductor layer 100 is smaller than the width of the depletion layer to be extended by the field effect of the gate, the thin film transistor operation can be obtained. That is, in the state where the surface of the channel portion where the channel is turned on by applying a bias to the gate is strongly inverted, the semiconductor layer can be in a depletion state or an inversion state. For this reason, control by a gate, such as suppressing the hole density in a semiconductor layer low, can be performed.

In general, the range of the depletion layer width Xd, ie, the field effect, in which the gate extends to the substrate side through the gate insulating film is

Can be seen.

Where K _s is the dielectric constant of the substrate semiconductor, εο is the dielectric constant of the vacuum, φ s is the potential change in the surface depletion layer when the surface becomes strongly inverted, q is the electron charge amount, and Ns is the impurity concentration of the substrate. Therefore, in the silicon channel, for example, when the substrate impurity concentration is 5 × 10 ¹⁶ cm ⁻³ , Xd is about 0.1 μm. In this embodiment, as described in the following steps, the semiconductor layer 100 has an electric field effect by the gate electrodes 30 on both sides. Therefore, the film thickness of the semiconductor layer may be set to 0.2 µm or less, more preferably 0.1 to 0.05 µm or less.

The process shown in FIG. 2B; After the thin film semiconductor layer 100 is formed, the photoresist mask 201 is removed, a silicon oxide film 152 of about 20 nm is formed on the surface of the substrate, and a silicon nitride film is deposited by about 20 nm by the CVD method. The silicon nitride film 700 is formed on the sidewalls of the thin film semiconductor layer 100 by anisotropically etching the silicon nitride film by using a. The substrate is removed by etching a hydrofluoric acid system to remove the silicon oxide film 152 of the portion not covered with the silicon nitride films 701 and 700, and further, a fluorine acid based solution (HF / HNO ₃ solution). Lightly etch the silicon at the bottom of the semiconductor layer 100 by wet etching, and then selectively oxidize the surface of the substrate 10 other than the semiconductor layer 100 by field oxidation in a wet atmosphere at 1100 ° C. A thick field oxide film can be attached. This oxide film becomes the insulating layer 20. At this time, since the oxide film grows on both sides of the bottom of the semiconductor layer 100, an extended oxide film is connected, whereby the semiconductor layer 100 is separated from the substrate 10.

The process shown in FIG. 2C; After the silicon nitride films 700 and 701 are removed by wet etching, the thin film surface of the semiconductor layer 100 is oxidized to form a thermal oxide film (not shown), and isotropic etching by hydrogen fluoride oxidation system is performed to perform this heat. By removing the oxide film, the layer damaged by etching is removed from the surface of the semiconductor layer 100, and the film thickness of the semiconductor layer 100 is made into a predetermined thickness. Thereafter, a gate oxide film 91 having a thickness of 10 nm is formed by oxidation, the polycrystalline silicon 30 'serving as a gate is deposited about 200 nm, and the resist material is patterned, and the polysilicon 30' is etched using this as a mask. Process by As a result, the gate electrode 30 as shown in FIG. 1 is obtained. 2C is a cross-sectional view taken along line C-C 'in FIG. 1.

The thickness of the oxide film grown by the thermal oxidation process (FIG. 2b) at the time of forming the gate oxide film 91 has a plane orientation dependency. Therefore, for example, the wafer surface orientation and the arrangement direction are selected so that the semiconductor layer 100 surface comes out to the convex side surface serving as the main channel, and the semiconductor layer 111 surface on which the thick oxide film is grown is the upper surface of the wafer (ie, The characteristics of the device obtained can be controlled by setting so as to be the bottom (surface to be the bottom) during polycrystalline silicon processing as a gate.

After patterning the gate electrode 30, the source electrode (region) 40 and the drain electrode (region) 50 shown in FIG. 1 are formed by the following method.

The gate insulating film on the surface of the semiconductor layer 100 where the source and drain regions are formed is removed by hydrofluoric acid wet etching. Then, impurities are activated by introducing a high concentration of phosphorus into the exposed semiconductor layer 100 and the gate electrode 30 and performing heat annealing to thereby source and drain the source electrode (region) 40 and the drain electrode (region). 50 and the gate electrode 30 are formed. Impurity introduction into the source electrode 40 and the drain electrode 50 may be performed by an ion implantation method using the gate electrode 30 as a mask. For example, as shown in FIG. 1, it can form by implanting ions with respect to the both sides of the semiconductor layer 100 with respect to a board | substrate in the inclination direction (X, X ').

In addition, when the height of the semiconductor layer 100 is low, for example, about 0.2 μm, the source electrode 40 and the drain electrode 50 can be formed without wide diffusion of impurities by heat treatment after ion implantation. That is, since the implantation energy can be set low, the impurity of ion implantation can be stopped by the field oxide film. Therefore, the source electrode 40 and the drain electrode 50 may be formed by implanting in a direction Y substantially perpendicular to the surface of the substrate 10.

The process shown in Fig. 2d; After the process shown in FIG. 2C, a thermal oxide film (not shown) is grown on the surfaces of the gate electrode 30, the source electrode 40, and the drain electrode 50, and then silicon oxide 150 is deposited. 30, a connection hole is drilled in the source electrode 40 and the drain electrode 50 to execute wiring. By forming the connection, the side of the semiconductor layer 100 is brought into contact with each other, whereby the connection area can be increased to reduce the resistance of the connection. 40 'is a source wiring.

As mentioned above, although the manufacturing method of the element structure shown in FIG. 1 was demonstrated, the example which improved this method is demonstrated. In the process of FIG. 2B, when forming the semiconductor layer by etching, the silicon nitride film 700 is formed only on the sidewalls, and then the semiconductor substrate etching is added to the lower portion of the semiconductor layer 100 so as not to have the silicon nitride film. The non-region can be formed (FIG. 2E). After the field oxidation, the formation of the insulating layer 20 under the semiconductor layer 100 can be facilitated.

In the process of FIG. 2A, oxidation of the upper portion of the semiconductor is suppressed by depositing the silicon nitride film 701 on the upper portion of the semiconductor layer in advance, but an oxide film is also formed on the upper portion of the semiconductor by field oxidation without providing the silicon nitride film on the upper portion. Can be. In this case, the oxide film on the semiconductor layer acts as a stopper layer for etching at the next gate processing.

In addition, the height of the semiconductor layer determines the channel width of the transistor. Therefore, the amount of current flowing by increasing the semiconductor layer can be increased. However, increasing this must be performed on the high semiconductor layer when connecting to the source and drain in a later step, making it difficult to form a lead-out layer for the connection. Therefore, as shown in the cross sectional view of the embodiment according to Fig. 2f, it is possible to avoid by lowering the height of the semiconductor layer other than the channel.

In the structure of the present invention, since the gate electrode spans over the semiconductor layer 100 serving as a channel, the gate length is effectively longer than that of the conventional single-sided MOSFET. Therefore, there is a problem that the gate wiring resistance increases. However, as shown in FIG. 2G, when the deposition of the polysilicon of the gate electrode 30 is a thickness of 1/2 or more of the width between the adjacent channels, the gate upper part can be connected almost uniformly, and the gate resistance can be adjusted to the conventional structure. Can be. As shown in FIG. 2G, the distribution resistance of the gate electrode can be reduced by providing the tungsten silicide layer 30 on the gate electrode or by replacing the gate electrode 30 with silicide. In this structure, the threshold value of the gate bias that determines the ON-OFF state of the device is strongly dependent on the work function of the gate material. Therefore, by using a material such as silicide having a suitable work function as the gate material, it is possible to set a threshold value required for circuit operation.

In this embodiment, in an nMOS having an n-type high concentration impurity layer as a source and a drain electrode, when the threshold value is the same as the source electrode and the gate electrode (formed by implanting phosphorus at a high concentration), that is, V _g ≒ 0 V (V _g is An example of setting the gate voltage) is described. Therefore, although the p-type semiconductor layer is used for the area | region used as a channel, an n-type layer can be selected and a channel part can be formed by setting this threshold value.

Since the element of the present invention is insulated from the substrate, even if integrated on the same substrate or on the chip, each of them is an independent element, and separation between the elements can be performed well. Therefore, latching up, which is a problem in the conventional CMOS structure, does not occur well, and software errors caused by? Rays, spacecrafts, and the like can be avoided.

If the thickness of the semiconductor layer is made thinner, the channel control by the gate electrode acts more strongly. Therefore, good thin film transistor characteristics can be obtained by setting it to about 0.1 µm to 0.05 µm in the silicon channel.

Here, the SOI substrate structure is formed by the oxidation method, but the SOI substrate or silicon is formed by forming a silicon recrystallization layer on an SOI substrate (so-called SIMOX) or an oxide film layer in which a high concentration of oxygen is ion-implanted into the substrate to form an oxide layer inside the substrate. The device structure of the present invention can be fabricated using a substrate such as SOI or a Silicon on Sapphire (SOS) substrate formed by attaching a silicon single crystal layer with an oxide layer interposed therebetween.

Example 2

In addition, in the device structure of the first embodiment, the effect of the electrical insulation separation between the element and the substrate is lost when the insulating layer extending from both sides is not connected to the lower portion of the semiconductor layer. However, it is possible to maintain the characteristics of the device suitable for the control and high integration of good channel electrical characteristics by the electric field effect performed by the gates on both sides of the channel formed in the thin film semiconductor.

3A to 3C show such a device structure. FIG. 3A is a plan view, FIG. 3B is a sectional view taken along line A-A 'of FIG. 3A, and FIG. 3C is a sectional view taken on line B-B' in FIG. 3A. The semiconductor layers 100 of two transistors share a gate electrode 30. As shown in FIG. 3C, in such a structure, the source and drain electrodes are formed in the semiconductor layer 100 by being slightly thinner than the diffusion layer field oxide film and formed deeper (closer to the substrate) than this. By this, stable electrical characteristics can be obtained. In such a structure in which the substrate crystal and the thin film are connected, the insulating layer 20 having an opening may be formed on the substrate, and the semiconductor layer 100 may be obtained by epitaxially growing the substrate crystal in the opening.

Example 3

4A to 4E show an embodiment in which the present invention is applied to a DRAM (Dynamic Random Access Memory) cell, in which FIG. 4A is a plan view of a 2-bit cell, and FIG. 4B is a sectional view taken along line bb 'in FIG. 4A. to be. Instead of making a wiring connection (contact) to the source electrode (region) 40 of the transistor shown in FIG. 1, the source electrode serving as one electrode (accumulation electrode) of the capacitor portion similarly to the gate insulating film 91 ( The surface of the region (40) is covered with the capacitor insulating film 90, and the other electrode (plate electrode) 60 of the capacitor portion is provided on the capacitor insulating film 90. As a result, the capacitive portion 41 is formed. In FIGS. 4A and 4B, the word line 31 and the bit line 80 constitute a 2-bit memory. As shown in FIG. 4A, by arranging the capacitive portion 41 in a T-shape, the surface area can be increased to increase the capacitance.

The word line 31, the bit line 80 and the plate electrode 60 are made of polysilicon implanted with a high concentration of phosphorus, for example. The bit line 80 is connected to the drain electrode (region) 50 through a bit line contact 80c provided in the interlayer insulating film.

When the semiconductor device of the present invention is used for the word portion (switching transistor), current leakage can be suppressed and stored by lowering the word potential as low as V _{bi relative} to the low bias side (source) potential when the transistor is in the off state. Information retention time can be extended. Here, V _bi is the difference between the Fermi level of the source electrode diffusion layer and the semiconductor layer of the channel portion. For example, in the case of an n-type device, the word write level may be set to -0.6V when V _bi = 0.6V and the low bias side potential is 0V.

In addition, as shown in Figs. 4C to 4E, the capacitance portion 41 can be laminated on the thin film semiconductor to increase the capacitance. FIG. 4C is a plan view and FIG. 4D is a sectional view taken along the line A-A 'of FIG. 4C. Low concentration impurity diffusion layers 45 and 55 are formed on the channel side of the source electrode 40 and the drain electrode 50 to form a DDD (Double Diffused Drain) type transistor. 4E is a modified example of the present embodiment, as shown in the figure, the bit line 80 may be formed after the word line 31 is formed, and the capacitor portion 41 may be laminated thereafter. 102 is a silicon oxide layer.

Example 4

FIG. 5 is a device cross-sectional view showing an embodiment in which the present invention is used in a trench type DRAM cell, and FIGS. 6A to 6E are process drawings showing the manufacturing method thereof.

In FIG. 5, the capacitor part 41 is inside the trench 96 provided in the board | substrate, and the periphery is comprised by the board | substrate plate 60 'with the capacitor insulating film 90 interposed.

By using the semiconductor layer 100 on the field oxide film 20, charge information can be written to the capacitor portion 41 in the bit line 80 via a thin film transistor having the word line 31 as a gate.

Since the transistor of the structure of the present invention is electrically isolated from the substrate, it is not electrically affected by the substrate. Therefore, the potential of the plate, that is, the substrate, can be arbitrarily set. Although the board | substrate is used here as a plate, it is the same also if the plate is comprised by the well layer which raised the impurity concentration and improved electroconductivity rather than that formed in the board | substrate.

6A to 6E, a method of forming an element in the embodiment of FIG. 5 will be described.

The process shown in Fig. 6A; Ion implantation of boron at a concentration of 1 × 10 ¹² cm ^-2 and diffusion by heat treatment to thermally oxidize the surface of the silicon substrate 10 on which the p-type well 60 'is formed, and to obtain an oxide film (not shown) of about 20 nm. The silicon nitride film 701 is deposited thereon by CVD to form a trench pattern on the photoresist. Using this as a mask, the silicon nitride film 701 is anisotropically etched by the RIE method, and the substrate is etched by about 5 µm vertically by the RIE method to form a trench, and then the photoresist is removed to form a capacitor insulating film on the trench surface. 90 is formed.

The process shown in Fig. 6B; Polycrystalline silicon is deposited on the entire surface of the substrate by CVD to at least about 1/2 of the trench diameter, and then etched back to remove polycrystalline silicon up to a depth of about 500 nm from the substrate surface. Leaves silicone. The etch-back method is used to perform an etching perpendicular to the substrate after deposition by using the planarization of the substrate surface when isotropic deposition to a thickness of 1/2 or more of the widest width of the groove pattern on the substrate caused by anisotropic etching or the like. We say method to leave sediment only in groove part formed by.

Using the polysilicon as a mask, the capacitor insulating film 90 is etched to open the sidewall 900 of the trench upper portion, and the polysilicon is filled in the trench by repeating deposition and etch back of the polysilicon again. To form 41. Thereafter, the silicon nitride film 701 is removed by wet etching of thermal phosphoric acid, followed by 20 nm deposition of silicon oxide (not shown), and 50 nm deposition of the silicon nitride film 701 'again, followed by a photo for forming a semiconductor layer. The resist 201 is patterned.

FIG. 6B shows a state in which the photoresist 201 on the silicon nitride film 701 'is patterned.

Formation (patterning) of the semiconductor layer and subsequent steps (Fig. 6C) are performed in the following step (Fig. 6B ') without depositing the silicon oxide and the silicon nitride film 701' in the step. The silicon nitride film 702 may be deposited after thermal oxidation of the surface of the semiconductor layer is performed.

The process shown in Fig. 6bb; The semiconductor layer 100 serving as a transistor by removing the silicon nitride film 701 ′ and the silicon oxide using the photoresist 201 as a mask, etching the substrate 10 vertically, and stopping the etching in the middle thereof. (Semiconductor layer 100 having the shape shown in FIG. 1) is formed.

The process shown in Fig. 6C; After the photoresist 201, the silicon oxide and the silicon nitride film 701 'are removed following the process shown in FIG. 6bb, the semiconductor layer 100 is thermally oxidized to form a 10 nm oxide film on the surface of the semiconductor layer 100. After that, the silicon nitride film 701 is deposited by 20 nm to protect the semiconductor layer 100 serving as a transistor and the connection portion between the capacitor portion 41 and the semiconductor layer 100. Then, a part of the trench upper surface in contact with the semiconductor layer 100 is selectively coated with a drawing electrode forming mask (not shown), and then selectively etched into the silicon nitride film 702 using the drawing portion forming mask. Is performed to leave the silicon nitride film 702 in the semiconductor layer 100 and the trench lead-out portion. That is, the semiconductor layer 100 and the trench lead-out portion are covered with the silicon nitride film 702. Impurity concentration of the well 60 'serving as a plate electrode separately from the channel by ion implantation of well impurities at 1 × 10 ¹³ cm ^-2 in this step (optionally covering the silicon nitride film 702). (p-type impurity concentration) can be set high.

The process shown in Fig. 6cc; By oxidizing the surface of the well 60 'not covered with the silicon nitride film 702, a thick field insulating film 20 is formed, and the semiconductor layer 100 serving as a channel is isolated from the well 60'. At this time, since the portion which electrically connects the semiconductor layer 100 and the capacitor portion 41 is covered with the silicon nitride film 702, the oxide film is not grown and electrical conduction is maintained.

The process shown in Fig. 6D; The silicon nitride film 702 is removed.

The process shown in Fig. 6E; The word line 31 is formed at the number where the thin film surface is oxidized to form a gate insulating film (not shown) having a thickness of 20 nm. Hereinafter, the process of wiring etc. is the same as that of Example 1.

In this embodiment, one transistor composed of a thin film semiconductor is provided for one trench capacitor. On the other hand, by forming a plurality of semiconductor layers serving as channels for one trench capacitance, it is possible to substantially increase the current flowing by increasing the channel width of the transistor.

Example 5

The planar space can be reduced by using the device of the present invention as a selection transistor and making the channel a vertical thin film. As shown in Figs. 7A to 7C, in the DRAM, an area which has been conventionally used only as an isolation region can be effectively used as the transistor region. For this reason, there is an effect of reducing the memory cell area or increasing the storage capacity. FIG. 7A is a planar layout view of a DRAM having two cells, FIG. 7B is a cross-sectional view taken along line A-A 'of FIG. 7A, and FIG. 7C is a cross-sectional view taken along line B-B' of FIG. 7A.

The capacitor 41 may be disposed to have a maximum area in the memory cell by removing a region necessary for separation between adjacent capacitors. In the semiconductor layer 100, the word line 31 can cross the capacitor portion with the capacitor portion 41 interposed therebetween. In addition, since the trench opening 250 is removed and the surface is covered with the field oxide film 20, it is not necessary to consider the arrangement of the capacitive portion 41 in the formation of a connection or the like formed thereon.

Example 6

FIG. 8 is a diagram showing an embodiment of a DRAM memory cell capable of realizing a fine memory cell area. In particular, FIG. 8 shows a two-point memory cell arrangement consisting of cells in which one thin film semiconductor is a channel of a selection transistor (switching transistor) and a capacitor portion is formed inside the trench. And a select transistor Qs and a trench capacitor C 96 each including a source electrode 40, a drain electrode 50, and a gate electrode (word line) 31 formed in the (100). The trench capacitor C has a structure as shown in FIG. 5, and one electrode (accumulation electrode) of the trench capacitor is connected to the source electrode 40. As shown in FIG. Reference numeral 400 denotes a bit line connection portion.

Example 7

9A to 9C show that the semiconductor layer (channel thin film) 100 is self-aligned with the trench mask. FIG. 9A is a plan view showing two cell arrangements, FIG. 9B is a sectional view taken along line A-A 'of FIG. 9A, and FIG. 9C is a sectional view taken along line B-B' of FIG. 9A. 10A and 10B are sectional views showing the manufacturing process thereof.

The process shown in FIG. 10A; After depositing about 500 nm of silicon oxide 211 on the substrate, patterning is performed to form trenches, and trenches are formed using this as a mask. After the capacitor portion 41 is formed in the trench, the photoresist 210 is filled to the silicon oxide surface by applying and etching back the photoresist.

The process shown in Fig. 10B; Thereafter, the silicon oxide 211 is removed, and the spacer 212 is provided on the sidewall of the photoresist using the step between the substrate surface and the photoresist. In this way, if an isotropically uniform thickness of deposition on a stepped pattern is etched by the film thickness vertically deposited with the substrate, the deposit can be left only on the stepped side wall. Hereinafter, the deposit formed in this way is called a spacer. By etching the substrate using the spacer as a mask, the semiconductor layer 101 self-aligned with the trench pattern can be formed.

10C is a cross-sectional view of a modification of the present embodiment, and may be connected to the semiconductor layer 100 around the trench by using the lead layer 300 in the capacitor portion 41. 61 represents n ⁺ buried layer.

Example 8

FIG. 11A is a planar layout view of two cells in a two-point (folded bit line type) arrangement, FIG. 11B is a sectional view taken along line A-A 'in FIG. 11A, and FIG. 11C is a sectional view taken along line B-B' in FIG. 11A. The capacitor portion 41 in the trench 96 is connected to the semiconductor layer 100 by the lead layer 300 at the trench opening 250. The lead layer 300 may be formed to be self-aligned with the word lines 31 and 31 ′.

Example 9

12 is a plan view showing two intersection arrangements when the semiconductor layer 100 is provided using substrate silicon between adjacent cells. The capacitor portion 41 is connected to the semiconductor layer 100 by the lead layer 300. A selection transistor is formed in the semiconductor layer 100 by the word line 31, and is connected to a data line (not shown) via the bit line connection unit 400.

The element shown in FIG. 12 is manufactured as follows. As shown in Figs. 13A and 13B, by forming trenches in the substrate to form the capacitor portion 41 and isotropically etching, the protrusions are thinned to form the semiconductor layer 100 having a predetermined thickness. do. In this step, the semiconductor layer 100 may be formed by thinning the projection by removing the silicon oxide by using the semiconductor layer surface layer as an oxide film by thermal oxidation. According to these methods, the semiconductor layer 100 which becomes a channel self-aligned between the adjacent trenches 96 can be formed. Therefore, since the distance with an adjacent trench can be made uniform, it is suitable for high integration. Thereafter, the semiconductor layer 100 can be formed in a self-aligned manner by removing the semiconductor layer 100 which is not used as a channel after the field oxide film is formed. This removal step may be performed after masking the active region used for the channel or the like. In addition, the thin film semiconductors other than the active region may be separated from the active region by inactivation by thermal oxidation or the like.

Example 10

Further, when forming the trench, the trench and the semiconductor layer 100 can be formed simultaneously by etching at intervals of about 0.1 to 0.2 mu m. FIG. 14A is a four-bit memory cell planar layout at two intersections, FIG. 14B is a sectional view taken along line A-A 'of FIG. 14A, and FIG. 14C is a sectional view taken along line B-B' of FIG. 14A. 14D is a memory cell planar layout diagram of a modification of the present embodiment.

In the embodiment shown in Figs. 14A to 14D, after forming the field oxide film 25 having a thickness of about 500 nm by thermal oxidation on the surface of the substrate, a trench 96 is provided to partially form a silicon oxide layer ( A semiconductor layer 100 having 25 can be formed. In this apparatus, since adjacent electrodes are electrically separated by the field oxide film 25 provided first, leakage between cells is suppressed even if the field oxide film 20 formed under the thin film semiconductor is insufficient. In addition, by forming the trench 96 in a concave shape in a plan view, when forming the lead-out layer 300, the layout margin of isolations α and the alignment margin β with the thin film semiconductor are greatly increased. can do. As shown in FIG. 14D, the trench may be arranged in a symmetrical position.

Α is the distance between the lead layer 300 and the trench 96 shown in the dashed-dotted frame in FIG. 14A. Β is the distance between the lead layer 300 shown by the dashed-dotted frame in FIG.

In the structure of this embodiment, since the capacitive portion is also field-oxidized and separated together with the substrate, the restriction for forming the channel at the time of forming the capacitive portion is reduced.

Example 11

As another example, as shown in FIGS. 15A and 15B, the capacitor portion 41 may be surrounded by the plate electrode 60 '. At this time, since both the plate electrode 60 'and the capacitor portion 41 can be formed of, for example, polycrystalline silicon, there is a risk that impurities in the insulating film or when forming the insulating film contaminate the substrate surface or the substrate. As a result, various materials such as Ta ₂ O ₅ and Hf oxide can be used for the capacitor insulating film 90. FIG. 15A is a planar layout view of one cell, and FIG. 15B is an AA 'cross-sectional view of FIG. 15A. In order to form the semiconductor device of FIGS. 15A and 15B, the trench is formed in FIGS. 14A to 14C, the silicon oxide film 150 is formed on the sidewalls, and the plate electrode 60 'is formed. After the capacitor insulating film 90 is formed, the capacitor portion can be formed by charging the capacitor storage electrode.

Example 12

FIG. 16 shows another embodiment by arranging an open bit line type. FIG. 16A is a plan view of two cells, and FIG. 16B is a sectional view taken along line A-A 'in FIG. 16A.

Example 13

As shown in Figs. 17A to 17C, the gate may be arranged on only one side by sufficiently thinning the semiconductor layer 100. Figs. In this device, the semiconductor layer 100 may be set to a thin film of 0.1 mu m. FIG. 17A is a planar layout view at one gate, and FIG. 17B is a sectional view taken along the line A-A 'in FIG. 17A. A spacer 500 for silicon oxide is formed on one side of the semiconductor layer 100, the gate electrode 30 is disposed horizontally thereon, and a transistor operation is obtained by the source electrode 40 and the drain electrode 50. Can be.

17C is a modification of the present embodiment, and as shown in the figure, a transistor may be formed using the semiconductor layer 100 in the stepped portion 501.

In addition, when a semiconductor device having a three-dimensional structure is formed, a Si portion having an insulating layer (for example, SiO ₂ ) on one side thereof is parasiticly formed. The embodiment shown in FIG. 17C aims at utilizing the stepped portion 501 made of an insulating layer in this parasitic structure.

Example 14

18A and 18B show a six stage CMOS inverter chain using the transistor structure of the present invention. FIG. 18A is a schematic planar layout view of a CMOS inverter chain, and FIG. 18B is a cross-sectional view taken along line AA ′ of FIG. 18A.

In FIG. 18A, NMOSs Q _n1 , Q _n2 , Q _n3 , Q _n4 , Q _n5 and Q _n6 are formed in the comb-tooth shaped thin film semiconductor layer 103. On the other hand, PMOS (Q _p1 , Q _p2 , Q _p3 , Q _p4 , Q _p5 , Q _p6 ) is formed in the comb-tooth shaped thin film semiconductor layer 104. In this embodiment, as shown in FIG. 18A, the comb-shaped thin film semiconductor layers 103 and 104 are located on the field insulating film 20. As shown in FIG. After the protective film 500a made of silicon oxide and the spacer 500b made of silicon oxide are formed on the sidewalls of the gate electrode 30, the surface of the thin film semiconductor layer (source and drain regions) is formed on the upper surface of the gate electrode 30. The silicide layer 600 generated by the reaction with a metal such as tungsten can be provided to increase the conductivity of the thin film semiconductor layer. In the diffusion layer serving as a conventional source and drain, it is difficult to use it as a wiring layer due to parasitic capacitance with a resistor or a substrate. However, in the present embodiment, it can be used as the wiring layers 103 and 104 of the first layer. In addition, since each device is independent, separation between the devices can be easily maintained even when integrated. In Fig. 18A, reference numeral 510 denotes an input hole for connecting the input signal wiring to the gate electrode.

Example 15

In addition, a bipolar transistor can be manufactured using the semiconductor layer 100. At this time, since it can be formed similarly to MOSFET, the circuit which has both MOSFET and a bipolar transistor can be formed easily. 19 is a diagram schematically showing a planar arrangement of one example thereof. In FIG. 19, a MOSFET Q _M and a thin film semiconductor layer 100 ′ formed of a source region 40, a drain region 50, and a gate electrode 30 formed on the thin film semiconductor layer 100 are formed on a main surface of the semiconductor substrate 10. The lateral type bipolar transistor Q _B formed of the emitter region 800, the base region 801, and the collector region 802 formed thereon is disposed. In addition, CH is a connection hole (contact hole) for connection with the upper wiring. AA 'is shown a cut end face 20a on the diagram of a method according to claim 19 degrees MOSFET Q unit _M. In addition, "the cut end face is shown in Figure 20b the BB in claim 19 degrees MOSFET Q unit _M.

In FIG. 20A, the thin film semiconductor layer 100 is disposed on the field insulating film 20. The gate electrode 30 is formed on the surface of the thin film semiconductor layer 100 via a gate insulating film to form a MOSFET Q _M.

On the other hand, in FIG. 20B, the bipolar transistor Q _B forms a mask on the base 801 by a silicon oxide film during processing of the gate electrode of the MOSFET Q _M , and emitter region 800 and collector region (by ion implantation method). 802 can be formed. At this time, the spacer 805 is formed on the mask side wall and the ion is implanted twice before and after, so that the concentration distribution of two stages can be provided only on one side. As a result, the medium concentration region 802 'can be formed.

Example 16

23A to 23C show an example in which a DRAM cell formed of two transistors is formed using a transistor of the present invention structure. FIG. 23A is an equivalent circuit diagram, FIG. 23B is a sectional view of the element, and FIG. 23C is a cross-sectional structure in a direction orthogonal to FIG. The selection transistor α and the memory unit transistor β are formed on the semiconductor layer 100. The transistor β uses the semiconductor layer 100 as the gate electrode 32 on the back side, and after the gate oxidation, polycrystalline silicon is deposited on the surface by 500 kV CVD to form the channel 910, and the gate oxide film 91 After forming the upper gate electrode 30. In the channel 910, V _th of the gate electrode 30 is changed by the potential of the gate electrode 32 on the back side, that is, the amount of charge accumulated in the gate electrode 32. This change can be operated as a memory element by reading.

That is, as shown in FIG. 24A, the data (charge) from the bit line is first passed through the selection transistor (light transistor) α in the ON state to the internal gate 32 of the memory transistor (lead transistor) β. Is introduced. In the stage where the selection transistor α is subsequently turned off, the gate electric field by the gate voltage V _G of the transistor β changes and the introduction and non-introduction (with or without charge) into the internal gate 32 changes the threshold voltage V. _th changes

Example 17

FIG. 24A is an equivalent circuit diagram of a memory cell of a static random access memory (SRAM). Here, PMOS and NMOS are displayed using the symbols of the substrate. In the transistor of the present invention, since the substrate is separated, separation between the transistors is easy, so that the transistors can be arranged close to each other. Therefore, the present transistor is effective when there is a high necessity for high integration of the transistor as in the SRAM structure.

24B and 24C show an example of the actual device configuration. 24B is a planar layout view, and FIG. 24C is a cross-sectional view along the line A-A 'in FIG. 24B.

The frame indicated by α in FIG. 24B constitutes a 1-bit memory cell, and FIG. 24B shows an example of a 2-bit cell arrangement. 24A and 24B, the transistors (a) and (b) having the word line 31 as a gate are formed using the semiconductor layer 100. The transistors (c) and (d) are formed by the trench 96 with a vertical transistor formed by the n ⁺ buried layer 61 inside the substrate and the gate 30. The gate 30 and the semiconductor layer 100 are connected by the connecting portion 402. The transistors (e) and (f) are formed of a polysilicon MOS transistor having a channel of polysilicon 30 'stacked on the gate 30 as a channel. The channel layer 30 'is controlled by the gate 30 layer via the gate insulating film 92 deposited on the gate 30. As shown in FIG. The polysilicon layer 30 'is connected to the gate 30 which is paired on the trench 96 pattern, respectively, and the other end is connected to the power supply line 51 via the connection part 403. FIG.

Example 18

As shown in FIG. 25, in the structure of the present invention, a charge coupled device (CCD) can be fabricated by overlapping gates. A 1 × 10 ¹⁷ cm ⁻³ N-type heavily doped impurity layer 803 is formed around the 1 × 10 ¹⁶ cm ⁻³ P-type semiconductor layer 100, a gate insulating film 90 is formed thereon, and the gate electrode thereon. 30 and selectively oxidize the gate electrode 30 without oxidizing the gate insulating film 90 to form the silicon oxide layer 102, and then overlap the gate electrode 30 with the gate electrode 30. Form '). Electric charge can be transferred into the semiconductor layer 100 by applying a sequential bias to the gate electrode.

In each of the figures, the same reference numerals and the same numerals denote essentially the same parts.

According to the present invention, a semiconductor device having a thin film transistor having high integration and good electrical characteristics can be obtained. In addition, by using this thin film transistor, a semiconductor memory device suitable for high integration and having good electrical characteristics can be obtained.

Claims (23)

A semiconductor device comprising a field effect transistor provided with a source electrode and a drain electrode on a substrate, and a channel between the source electrode and the drain electrode and a gate electrode having an electric field effect through an insulating film in the channel. At least a portion is provided in the thin film semiconductor layer having a height greater than its width and having a pair of main surfaces on both sides thereof, each main surface having a surface area larger than any other surface of the thin film semiconductor layer, and the gate electrode having the insulating film Disposed on at least one of the main surfaces, at least one of the main surfaces is substantially perpendicular to the substrate, and a current direction flowing through the channel is at least one of the main surfaces of the thin film semiconductor layer. And a semiconductor device substantially parallel to the substrate. The semiconductor device according to claim 1, wherein the channel of the field effect transistor is provided with an insulating layer disposed at least in part with the substrate in a lower portion perpendicular to the substrate. 3. The semiconductor device according to claim 2, wherein said insulating layer disposed at least in part between said substrate and said channel is a thermal oxide film formed by thermally oxidizing a substrate. The semiconductor device of claim 1, wherein the channel is substantially insulated from the substrate. A semiconductor device having a charge coupling portion formed on a substrate and having a plurality of gate electrodes formed on an insulating film formed on the charge coupling portion, wherein the gate electrode acts on the charge coupling portion via the insulating layer. Wherein at least a portion of the charge coupling portion is provided in a thin film semiconductor layer having a height greater than its width and having a pair of main surfaces on both sides thereof, each major surface having a surface area larger than any other surface of the thin film semiconductor layer. And the gate electrode is disposed on at least one of the main surfaces via the insulating film, and the at least one main surface of the thin film semiconductor layer is substantially perpendicular to the substrate, and the charge transfer direction in the charge coupling portion is A semiconductor device substantially parallel to said substrate. A semiconductor memory device having at least two transistors on a substrate, wherein at least one of the transistors is a field effect transistor having a source electrode, a drain electrode, a channel, and a gate electrode having an electric field effect through the insulating film on the channel. At least a portion of the channel of the field effect transistor is disposed between the source electrode and the drain electrode, and is provided in a thin film semiconductor layer having a height greater than its width and having a pair of main surfaces on both sides, wherein the main surfaces are each the thin film. Has a surface area larger than any other surface of the semiconductor layer, the gate electrode is disposed on at least one of the main surfaces via the insulating film, and the at least one main surface of the thin film semiconductor layer is substantially perpendicular to the substrate And a current direction flowing through the channel is approximately parallel to the substrate Semiconductor memory. 7. The semiconductor memory device according to claim 6, wherein said channel is substantially insulated from a substrate. A semiconductor device having at least two transistors provided with a source electrode and a drain electrode on a substrate, and with a channel between the source electrode and the drain electrode and a gate electrode having an electric field effect through the insulating film in the channel, respectively. At least a portion of each channel is provided in a thin film semiconductor layer having a height greater than its width and having a pair of main surfaces on both sides thereof, each major surface having a larger surface area than any other surface of the thin film semiconductor layer, the gate An electrode is disposed on at least one of the main surfaces via the insulating film, the at least one main surface of the thin film semiconductor layer is substantially perpendicular to the substrate, and a current direction flowing through the channel is substantially parallel to the substrate At least one gate electrode of the transistor is disposed between two channels Control semiconductor device. At least one capacitor and at least one field effect transistor provided with a source electrode and a drain electrode on the substrate, and a channel between the source electrode and the drain electrode and a gate electrode having a field effect through the insulating film in the channel. In a semiconductor memory device, at least a portion of the channel is provided in a thin film semiconductor layer having a height greater than its width and having a pair of main surfaces on both sides thereof, each major surface having a surface area larger than any other surface of the thin film semiconductor layer. And the gate electrode is disposed on at least one of the main surfaces via the insulating film, the at least one main surface of the thin film semiconductor layer is substantially perpendicular to the substrate, and the current direction flowing through the channel is A semiconductor memory device approximately parallel with the substrate. 10. The semiconductor memory device according to claim 9, wherein said channel is substantially insulated from a substrate. The semiconductor device according to claim 1, wherein the semiconductor layer has a thickness of 0.2 µm or less. The semiconductor device according to claim 5, wherein the semiconductor layer has a thickness of 0.2 µm or less. The semiconductor memory device according to claim 6, wherein a thickness of the semiconductor portion provided with the channel is 0.2 탆 or less. The semiconductor device according to claim 8, wherein the semiconductor layer has a thickness of 0.2 µm or less. The semiconductor memory device according to claim 9, wherein the semiconductor layer has a thickness of 0.2 µm or less. A semiconductor device having a field effect transistor provided with a source electrode and a drain electrode on a substrate, and a channel between the source electrode and the drain electrode and a gate electrode having an electric field effect through an insulating film in the channel. At least a portion is provided in a semiconductor layer having a height greater than its width and having a pair of main surfaces on both sides thereof, each main surface having a surface area larger than any other surface of the semiconductor layer, and the gate electrode passing through the insulating film Disposed on at least one of the main surfaces, provided on the substrate via an insulating film disposed on the substrate of the semiconductor layer, at least one of the main surfaces of the semiconductor layer is substantially perpendicular to the substrate, The current direction flowing through the channel is approximately parallel to the substrate, Least a portion is a semiconductor device which is provided on the side surface side of the semiconductor layer. A first process of growing a silicon oxide film on a silicon substrate and a first process of depositing a silicon nitride film, and after the first process, using the resist pattern as a mask, the first silicon nitride film, the silicon oxide film and the silicon substrate A second process of etching to form a silicon island made of a portion of the silicon substrate, a silicon oxide film is grown on the surface of the silicon substrate and the silicon island exposed by the second process after the second process, and A third process of depositing a silicon nitride film of 2 and etching the second silicon nitride film so that the second silicon nitride film remains on the sidewall of the silicon island; and after the third process, the surface of the silicon substrate is A fourth step of growing a silicon oxide film by thermal oxidation and electrically separating the silicon island from the silicon substrate; and To the gate electrode, and forming a gate electrode on said silicon seomsang after the fourth step of a mask manufacturing method of insulated gate field effect transistor comprising a fifth step of forming source and drain regions in the silicon island. A first process of growing a silicon oxide film on a silicon substrate and depositing a first silicon nitride film, and after the first process, using the resist pattern as a mask, the first silicon nitride film, the silicon oxide film and the silicon substrate A second process of etching to form a silicon island made of a portion of the silicon substrate, a silicon oxide film is grown on the surface of the silicon substrate and the silicon island exposed by the second process after the second process, and A third process of depositing a silicon nitride film of 2 and etching the second silicon nitride film so that the second silicon nitride film remains on the sidewall of the silicon island; and after the third process, the surface of the silicon substrate is A fourth step of growing a silicon oxide film by thermal oxidation and electrically separating the silicon island from the silicon substrate; A fifth step of forming a gate electrode on the silicon island after the step and forming a source and a drain area on the silicon island using the gate electrode as a mask, and an insulating film on the source area after the fifth step. A manufacturing method of a semiconductor memory device comprising a sixth step of forming a plate electrode. 19. The method of manufacturing a semiconductor memory device according to claim 18, wherein in the second step, the silicon island is formed in a T-shape. A first step of forming a groove in the silicon substrate and forming an insulating film to a predetermined height of the inner wall of the groove; a second step of filling the groove with the conductive layer to the surface of the silicon substrate after the first step A third step of growing a silicon oxide film on the silicon substrate and the conductive layer after the second step and depositing a first silicon nitride film; and using the resist pattern as a mask after the third step A fourth step of forming a silicon island comprising a portion of the silicon substrate and a portion of the conductive layer by etching the silicon nitride film 1, the silicon oxide film, the silicon substrate, and the conductive layer to at least the predetermined height; After the process of growing a silicon oxide film on the surface of the silicon substrate and the silicon island exposed in the second process, and the second silicon nitride film A fifth process of etching the second silicon nitride film so that the second silicon nitride film deposited on the sidewall of the silicon island and the second silicon nitride film deposited on the connection portion between the silicon island and the conductive layer remain; A sixth process of growing a silicon oxide film by thermally oxidizing the silicon substrate surface after the fifth process and electrically separating the silicon island from the silicon substrate, and on the silicon island after the sixth process And a seventh step of forming a gate electrode and forming a source and a drain region in the silicon island using the gate electrode as a mask. A first step of growing a first silicon oxide film on a silicon substrate and depositing a first silicon nitride film thereon, the first silicon nitride film, the first silicon oxide film and the silicon using a resist pattern as a mask A second process of etching a substrate to form a silicon island consisting of a portion of the silicon substrate, a second silicon oxide film is grown on the surface of the silicon substrate and the surface of the silicon island exposed by the second process, and A third process of etching the second silicon nitride film such that a second silicon nitride film is deposited thereon and the second silicon nitride film portion remaining on the sidewall of the silicon island is left; and a gate electrode is formed on the silicon island; A method for manufacturing an insulated gate field effect transistor comprising a fourth step of forming a source region and a drain region in a silicon island. A first step of growing a first silicon oxide film on a silicon substrate and depositing a first silicon nitride film thereon, the first silicon nitride film, the first silicon oxide film, and the silicon substrate using a resist pattern as a mask Etching to form a silicon island consisting of a portion of the silicon substrate, a second silicon oxide film is grown on the surface of the silicon substrate and the surface of the silicon island exposed by the second process and thereon; A third process of etching the second silicon nitride film so as to deposit a second silicon nitride film and leave a portion of the second silicon nitride film deposited on the sidewall of the silicon island, forming a gate electrode on the silicon island and forming the silicon In the fourth step of forming a source region and a drain region on an island, an insulating film is interposed between the plate electrode and the source region. A method for fabricating a semiconductor memory device comprising a fifth step of forming a plate electrode on the source region. 23. The method of claim 22, wherein the silicon island is formed in a T shape.