JPH05110107A - Semiconductor device having floating gate - Google Patents

Abstract

PURPOSE:To provide a structure of a gate electrode improved in write and erase characteristics of a nonvolatile semiconductor memory device having floating gates such as an EPROM. CONSTITUTION:A part of a floating gate 28 is constituted of a polysilicon layer formed by chemical vapor growth under conditions to form many microruggednesses on the surface, and the surface of the floating gate 28 with micro-ruggednesses is overlaid with an intermediate insulating film 30 and a control gate 32 along the ruggedness.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a floating gate, and more particularly to a structure of a gate electrode for improving writing and erasing characteristics of a nonvolatile semiconductor memory device having a floating gate such as EPROM.

[0002]

^2. Description of the Related Art In a non-volatile memory device such as an EPROM and an E ² PROM, each memory cell composed of MOS transistors generally has a structure having a floating gate. That is, as shown in FIG.
In the memory cell 2 including the S transistor, the gate insulating film 6, the floating gate 8, the intermediate insulating film 10 and the control gate 12 are formed on the surface of the semiconductor substrate 4.
The layers are stacked in this order. The source region 14 and the drain region 1 are formed on the surface of the semiconductor substrate 4 located below both sides of the floating gate 6 and the control gate 12.
6 is formed.

In order to write data to the memory cell 2, a current is applied to the channel region 18 while a high voltage is applied between the source region 14 and the drain region 16 and floating is performed by utilizing the hot electron effect. It suffices to inject charges into the gate 8. A method is also known in which a high voltage is applied between the control gate 12 and the semiconductor substrate 4 and charges are injected into the floating gate by the tunnel effect to write data. In the memory cell 2 as described above, in order to erase data, the data is erased between the control gate 12 and the semiconductor substrate 4.
This is performed by applying a high voltage opposite to that at the time of writing data and extracting the electric charge accumulated in the floating gate 8 to the substrate 4 side.

The structure of the gate electrode in the memory cell 2 described above can be represented by an equivalent circuit in which capacitors A and B are connected in series as shown in FIG. That is, the capacitor A is composed of the semiconductor substrate 4, the gate insulating film 6 and the floating gate 12 shown in FIG. 7, and the capacitor B is the floating gate 8 and
It is composed of the intermediate insulating film 10 and the control gate 12. The potentials of the terminals a, b and c shown in FIG. 8 correspond to the potentials of the semiconductor substrate 4, the floating gate 8 and the control gate 12, respectively.

Here, when the voltages Va, c are applied to the terminals a, c, the larger the voltages Va, b applied to the terminals a, b are, the more the efficiency of writing and erasing data is improved. V
To increase Va, b while keeping a, c constant, use capacitor B
It is necessary to make the capacitance CB of the capacitor A relatively larger than the capacitance CA of the capacitor A. This is because Va, b is obtained by the following equation. Va, b = Va, c × CB / (CB + CA)

[0006]

As a means for relatively increasing the voltages Va and b, it is conceivable to reduce the thickness of the intermediate insulating film 10 shown in FIG. However, with such means, a leak current from the floating gate 8 to the control gate 12 is likely to occur, which causes a problem of data deterioration. Therefore, the intermediate insulating film 6 cannot be made too thin.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a structure of a gate electrode for improving writing and erasing characteristics of a nonvolatile semiconductor memory device having a floating gate such as an EPROM. To do.

[0008]

In order to achieve the above object, the semiconductor device of the present invention uses a chemical vapor deposition method in which at least a part of the floating gate is formed under the condition that a large number of fine irregularities are formed on the surface. It is characterized in that the intermediate insulating film and the control gate are laminated along the unevenness on the surface of the floating gate which is formed of the formed polysilicon layer and in which the minute unevenness is formed.

[0009]

In the semiconductor device of the present invention, at least a part of the silicon layer to be the floating gate is provided with a large number of fine irregularities on its surface, that is, a transition state from an amorphous state to a polycrystalline state. Chemical vapor deposition (C
Since it is formed by the VD method), hemispherical fine irregularities are formed on the surface of the floating gate on the control gate side. By stacking the intermediate insulating film and the control gate on the fine uneven surface, the fine uneven surface increases the capacitance of the capacitor between the floating gate and the control gate. Therefore, the voltage applied to the control gate efficiently acts on the floating gate with a small voltage drop, and the data writing efficiency and erasing efficiency with respect to the floating gate are improved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device having a floating gate according to an embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a cross-sectional view of a main part of a semiconductor device having a floating gate according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device of the same embodiment, and FIGS. Graphs showing conditions for forming fine irregularities formed on the surface of a floating gate used in a semiconductor device, and FIGS. 5 and 6 are schematic cross-sectional views of a main part of a semiconductor device according to another embodiment of the present invention.

A semiconductor device according to an embodiment of the present invention shown in FIG. 1 is an EPROM or an E ² PROM, and has memory cells 20 as shown in a matrix on a semiconductor substrate 22. Each memory cell 20 is element-isolated by the selective oxidation region 24 formed on the surface of the semiconductor substrate 22, and the gate insulating film 26, the floating gate 28, the intermediate insulating film are formed on the element-isolated surface of the semiconductor substrate 22. 30 and the control gate 32 are laminated in this order.

A source region 34 and a drain region 36 are formed on the surface of the semiconductor substrate 22 located below both sides of the floating gate 28 and the control gate 32.
It is formed by an ion implantation method or the like. An interlayer insulating film 38 is laminated on the surface of the semiconductor substrate 22 on which the floating gate 28 and the control gate 32 are formed. A contact hole 40 is formed in the interlayer insulating film 38 so as to face the source region 34 and the drain region 36 formed on the surface of the semiconductor substrate 22. The interlayer insulating film 3 is formed so that the metal electrode layer 42 made of aluminum or the like enters the contact holes 40.
A metal electrode layer 42 is formed on the surface of No. 8 in a predetermined pattern.

Although not shown, the control gate 32 is also connected to a metal wiring layer formed in another layer through a contact hole so that a gate voltage can be applied. ..

To manufacture a semiconductor device having the memory cell 20 having the above structure, a selective oxidation region 24 as an element isolation region is formed on the surface of a semiconductor substrate 22 as shown in FIG. After the formation, the gate insulating film 26 is formed by means of thermal oxidation or the like. As the semiconductor substrate 22,
For example, a silicon substrate is used.

Next, as shown in FIG. 3B, a polysilicon layer 28a to be the floating gate 28 shown in FIG. 1 is formed on the surfaces of the gate insulating film 26 and the selective oxidation region 24.
Is formed by a low pressure CVD method. The CVD method for forming the polysilicon layer 28a of the present embodiment is different from the condition for the ordinary CVD method for forming the polysilicon layer, that is, the condition that many fine irregularities are formed on the surface, that is, the amorphous state. It is performed under the condition that the transition state from the state to the polycrystalline state is obtained. In this respect, the polysilicon layer 28a of the present embodiment is not composed of poly (polycrystalline) silicon in the strict sense, but in the present invention, the amorphous state to the polycrystalline state is as described above. The silicon layer obtained by the CVD method under the condition that the transition state to is also a layer composed of polysilicon in a broad sense, and is referred to as a polysilicon layer.

The CVD conditions for the polysilicon layer 28a on the surface of which fine hemispherical irregularities are formed depend particularly on the CVD temperature conditions, and as shown in FIG.
Preferably, the CVD temperature condition of about 560 to 575 ° C is desirable. When the polysilicon layer is formed under such a CVD temperature condition, the grain size is 0.03 to 0.1 μm.
Concavities and convexities of about m are formed on the surface of the polysilicon layer 28a. The condition for forming the polysilicon layer 28a is C
Other than VD temperature, normal CVD for forming polysilicon layer
The conditions are similar to the conditions, for example, 0.1 to 0.4 Tor
CVD using rH monosilane gas SiH ₄ as atmosphere gas
It is a condition. In the CVD process, by adding PH ₃ gas to SiH ₄ gas, the polysilicon layer 28
It is preferable to dope phosphorus a into a. This is to improve the conductivity and the like of the polysilicon layer 28a. As a means for doping the polysilicon layer 28a with phosphorus, an ion implantation method may be adopted.

The CVD temperature condition for forming a normal polysilicon layer having a flat surface is 600 ° C. or higher, which is higher than the temperature condition for forming the polysilicon layer of this embodiment. I understand. Polysilicon layer 28
The film thickness of a is not particularly limited and is preferably about 0.2 μm. As shown in FIG. 4, the film thickness of the polysilicon layer 28a and the grain size have a fixed relationship, and the grain size tends to increase as the film thickness increases.

Next, as shown in FIG. 2C, an intermediate insulating film 30 is formed on the uneven surface of the polysilicon layer 28a. The intermediate insulating film is not particularly limited, but for example, ONO
It is composed of a membrane. The ONO film is used as the polysilicon layer 28a.
The surface of the polysilicon layer 28a is thermally oxidized by about 7 nm to form a silicon nitride film on the surface thereof by CV.
It is formed by depositing about 10 nm by the D method and thermally oxidizing the surface of the silicon nitride film about 3 nm. Next, a control gate conductive layer 32a to be the control gate 32 shown in FIG. 1 is formed on the surface of the intermediate insulating film 30. The conductive layer 32a is composed of, for example, a normal polysilicon layer. When the conductive layer 32a is composed of a polysilicon layer, the polysilicon layer is 58
The film is formed by the CVD method under the temperature condition of 0 to 650 ° C. The thickness of the conductive layer 32a is not particularly limited,
The film thickness is similar to that of the polysilicon layer 28a. As described above, this conductive layer is a portion that will be the control gate 32, and is preferably doped with phosphorus for the purpose of improving conductivity.

Next, as shown in FIG. 2D, the conductive layer 2a, the intermediate insulating film 30 and the polysilicon layer 28a shown in FIG. 2C are etched into a predetermined pattern by using the same photomask to control them. Gate 32, intermediate insulating film 3
0 and floating gate 28 are obtained.

Next, as shown in FIG. 1, the surface of the semiconductor substrate 22 located below both sides of the floating gate 28 and the control gate 32 is doped with, for example, arsenic by an ion implantation method to form a source region. 34 and drain region 36 are formed. After that, an interlayer insulating film 38 is formed, a contact hole 40 is opened in the interlayer insulating film 38, and the contact hole 4 is formed.
When the metal wiring layer 42 is formed in a predetermined pattern so as to enter into 0, the memory cell 20 for EPROM, for example, is completed. The wiring process for the control gate 32 is omitted for the sake of explanation.

The memory cell 20 manufactured in this way
In the semiconductor device having the above, due to the fine uneven surface formed on the surface of the floating gate 28 on the control gate side, the capacitance of the capacitor between the floating gate 28 and the control gate 32 increases. Therefore, the voltage applied to the control gate 32 is efficiently reduced with a small voltage drop.
8 to improve the data writing efficiency and the data erasing efficiency with respect to the floating gate 28.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, as shown in FIG. 5, the floating gate 28 is formed on the conductive thin film 44 formed on the gate insulating film 44 and the surface of the conductive thin film 44, and many fine irregularities are formed on the surface. The polysilicon layer 28a may be formed by the CVD method under the above conditions. The conductive thin film 44 is not particularly limited, but is composed of, for example, a polysilicon layer formed by a CVD method under normal conditions. When the conductive thin film 44 is composed of a polysilicon layer, the conductive thin film 44 and the polysilicon layer 28 formed by the CVD method under specific conditions are used.
“A” can be continuously formed by changing the CVD conditions. In that case, the interface between the conductive thin film 44 and the polysilicon layer 28a becomes unclear.

Further, as shown in FIG. 6, the conductive thin film 44
The polysilicon layer 28a formed by the CVD method under the specific conditions may be divided in the plane direction by the fine unevenness formed on the surface of the polysilicon layer 28a. good. In the case of this embodiment, the surface area for the capacitor between the control gate 32 and the floating gate 28 is further increased, and the capacitor capacitance is increased.

[0024]

As described above, according to the present invention, the fine uneven surface formed on the control side surface of the floating gate increases the capacitance of the capacitor between the floating gate and the control gate. Therefore, the capacity of the capacitor between the floating gate and the control gate can be increased without thinning the intermediate insulating film, and the efficiency of writing and erasing data in the floating gate can be improved. Moreover, even if the intermediate insulating film is thicker than the conventional one,
Since the fine unevenness on the surface of the floating gate can maintain a capacitor capacitance equal to or higher than that of the conventional one, a leak current from the floating gate to the control gate can be prevented, and the data retention ability and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor device having a floating gate according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of the embodiment.

FIG. 3 is a graph showing conditions for forming fine irregularities formed on the surface of a floating gate used in the semiconductor device of the same example.

FIG. 4 is a graph showing conditions for forming fine irregularities formed on the surface of the floating gate used in the semiconductor device of the same example.

FIG. 5 is a schematic sectional view of a main portion of a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a main part of a semiconductor device having a floating gate according to a conventional example.

8 is a schematic diagram showing an equivalent circuit corresponding to the gate structure shown in FIG. 7. FIG.

[Explanation of symbols]

 20 ... Memory cell 22 ... Semiconductor substrate 26 ... Gate insulating film 28 ... Floating gate 28a ... Polysilicon layer 30 ... Intermediate insulating film 32 ... Control gate 44 ... Conductive thin film

Claims (3)

[Claims] 1. In a semiconductor device in which a floating gate, an intermediate insulating film, and a control gate are stacked in this order on a gate insulating film, at least a part of the floating gate is formed with a large number of fine irregularities on the surface. The floating gate, which is composed of a polysilicon layer formed by chemical vapor deposition under the conditions described above, has fine irregularities formed on it, and an intermediate insulating film and a control gate are laminated along the irregularities. A semiconductor device having a floating gate. 2. The floating gate comprises a conductive thin film, and a polysilicon layer formed on the surface of the conductive thin film by chemical vapor deposition under the condition that many fine irregularities are formed on the surface. The semiconductor device having a floating gate according to claim 1, comprising: 3. The semiconductor device having a floating gate according to claim 2, wherein the polysilicon layer is divided in the plane direction by fine irregularities formed on the surface of the polysilicon layer. ..