JP5450846B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device using a variable resistance element that stores resistance values as data.

  Conventionally, as an electrically rewritable nonvolatile memory, a flash memory in which a memory cell having a floating gate structure is NAND-connected or NOR-connected to form a cell array is well known. A ferroelectric memory is also known as a non-volatile memory capable of high-speed random access.

  On the other hand, as a technique for further miniaturizing a memory cell, a resistance change type memory using a variable resistance element as a memory cell has been proposed. Examples of the variable resistance element include a phase change memory element that changes a resistance value according to a change in state of crystal / amorphization of a chalcogenide compound, an MRAM element that uses a resistance change due to a tunnel magnetoresistance effect, and a polymer in which a resistance element is formed of a conductive polymer. A memory element of a ferroelectric RAM (PFRAM), a ReRAM element that causes a resistance change by applying an electric pulse, and the like are known (Patent Document 1).

  In this resistance change type memory, a memory cell can be constituted by a series circuit of a Schottky diode and a variable resistance element instead of a transistor. Therefore, stacking is easy, and further integration can be achieved by forming a three-dimensional structure. There is an advantage (Patent Document 2).

  However, the variable resistance element and the non-ohmic element generate heat when the state of the variable resistance element is changed by writing or erasing data in the memory cell. Therefore, if data writing and erasing are simultaneously performed on a large number of memory cells, the influence of this heat generation becomes large, resulting in a loss of data stability. This problem becomes more apparent as the non-volatile memory is highly integrated.

JP 2006-344349, paragraph 0021 JP-A-2005-522045

  Accordingly, an object of the present invention is to provide a non-volatile memory that realizes high-speed operation by simultaneous writing and erasing of a plurality of memory cells and that reduces the influence of heat generation of the memory cells during operation.

  A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of first wirings, a plurality of second wirings intersecting with the plurality of wirings, and an intersection portion of the first and second wirings. A cell array in which memory cells including a series circuit of a variable resistance element and a non-ohmic element that are electrically rewritable and store resistance values in a nonvolatile manner as data are connected between wirings, and the cell array is physically connected to each other. And an access circuit that simultaneously accesses a plurality of the memory cells spaced apart from each other.

  A non-volatile semiconductor memory device according to another aspect of the present invention includes a plurality of first wirings, a plurality of second wirings intersecting with the plurality of wirings, and an intersection of the first and second wirings. A plurality of MATs (unit cell arrays) having a memory cell composed of a series circuit of a variable resistance element and a non-ohmic element that can be electrically rewritten and can store resistance values in a nonvolatile manner as data connected between wirings. A cell array and a plurality of access circuits connected to the respective MATs and accessing internal memory cells for each of the MATs, wherein the plurality of access circuits include a predetermined number of memory cells in the corresponding MAT. Are simultaneously accessed.

1 is a block diagram of a nonvolatile memory according to a first embodiment of the present invention. FIG. It is a perspective view which shows a part of MAT of the non-volatile memory which concerns on the same embodiment. FIG. 3 is a cross-sectional view of one memory cell taken along line II ′ in FIG. 2 and viewed in the direction of an arrow. It is a typical sectional view showing an example of a variable resistance element in the embodiment. It is a circuit diagram which shows MAT at the time of write-in operation | movement. It is a circuit diagram showing MAT at the time of page unit writing operation. It is the schematic which shows the example of the write-in order of a page unit. It is the schematic which shows the other example of the order of write operation of a page unit. FIG. 2A is a schematic diagram showing an erasing operation in units of MATs, and FIG. FIG. 6 is a schematic diagram illustrating a page-unit write operation of the nonvolatile memory according to the first embodiment. It is a block diagram which shows the cell array in the same embodiment. FIG. 3 is a block diagram showing a MAT arrangement of a cell array and logical addresses of memory cells in the same embodiment. FIG. 3 is a circuit diagram showing a part of a row control circuit in the same embodiment. It is a block diagram which shows arrangement | positioning of MAT of the cell array of the non-volatile memory which concerns on 2nd Embodiment, and the logical address of a memory cell. It is a block diagram which shows arrangement | positioning of MAT and the logical address of a memory cell of the cell array of the non-volatile memory based on 3rd Embodiment. It is a block diagram which shows arrangement | positioning of MAT of the cell array of the non-volatile memory which concerns on 4th Embodiment, and the logical address of a memory cell. It is a block diagram which shows arrangement | positioning of MAT of the cell array of the non-volatile memory which concerns on 5th Embodiment, and the logical address of a memory cell. It is a block diagram which shows arrangement | positioning of MAT and the logical address of a memory cell of the cell array of the non-volatile memory based on 6th Embodiment. 2 is a circuit diagram of a sense amplifier circuit S / A in the same embodiment. FIG. It is a block diagram which shows arrangement | positioning of MAT and the logical address of a memory cell of the cell array of the non-volatile memory which concerns on other embodiment.

  Hereinafter, embodiments of a nonvolatile memory according to the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram of a nonvolatile memory according to the first embodiment of the present invention.
This nonvolatile memory includes a plurality of MATs (unit cell arrays) 1 arranged in a matrix using resistance change elements such as ReRAM (variable resistance elements) described later as memory cells. Each MAT 1 is provided with a column control circuit 2 and a row control circuit 3 which are access circuits. The column control circuit 2 includes a single sense amplifier circuit (not shown) that detects and amplifies data in the memory cell that appears on the bit line, and controls the bit line BL in the MAT 1 to erase data in the memory cell and Data writing and data reading from the memory cell are performed. The row control circuit 3 selects the word line WL of the MAT 1 and applies a voltage necessary for erasing data in the memory cell, writing data into the memory cell, and reading data from the memory cell.

  The data input / output buffer 4 is connected to an external host (not shown) via an I / O line, and receives write data, receives an erase command, outputs read data, and receives address data and command data.

  The data input / output buffer 4 is connected to a read / write circuit (hereinafter referred to as “R / W circuit”) 8. The data input / output buffer 4 sends the received write data to the column control circuit 2 via the R / W circuit 8 and receives the data read from the column control circuit 2 via the R / W circuit 8 to the outside. Output. An address supplied from the outside to the data input / output buffer 4 is sent to the column control circuit 2 and the row control circuit 3 via the address register 5. The command supplied from the host to the data input / output buffer 4 is sent to the command interface 6. The command interface 6 receives an external control signal from the host, determines whether the data input to the data input / output buffer 4 is write data, a command, or an address, and if it is a command, transfers it to the controller 7 as a received command signal. . The controller 7 manages the entire nonvolatile memory, receives commands from the host, and performs read, write, erase, data input / output management, and the like. An external host can also receive status information managed by the controller 7 and determine an operation result. Further, this status information is also used for control of writing and erasing.

  The R / W circuit 8 is controlled by the controller 7. By this control, the R / W circuit 8 can output pulses of arbitrary voltage / current and arbitrary timing. Here, the formed pulse can be transferred to an arbitrary wiring selected by the column control circuit 2 and the row control circuit 3.

  In the figure, the column control circuit 2, the row control circuit 3, and the R / W circuit 8 are shown to be formed on the same plane as the MAT1, but peripheral circuit elements other than these MAT1 are formed in the wiring layer. It can be formed on the Si substrate immediately below the formed MAT 1, whereby the chip area of the nonvolatile memory can be made substantially equal to the combined area of the plurality of MATs 1.

  FIG. 2 is a perspective view of a part of the MAT 1, and FIG. 3 is a cross-sectional view of one memory cell taken along the line II ′ in FIG.

  Word lines WL0 to WL2 are arranged in parallel as a plurality of first wirings, and bit lines BL0 to BL2 are arranged in parallel as a plurality of second wirings so as to intersect therewith. The memory cells MC are arranged so as to be sandwiched between the two wirings. The first and second wirings are preferably made of a material that is resistant to heat and has a low resistance value. For example, W, WSi, NiSi, CoSi, or the like can be used.

  As shown in FIG. 3, the memory cell MC includes a series connection circuit of a variable resistance element VR and a non-ohmic element NO.

As the variable resistance element VR, the resistance value can be changed by applying voltage, through current, heat, chemical energy, etc., and electrodes EL1 and EL2 functioning as a barrier metal and an adhesive layer are arranged above and below. . As the electrode material, Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al, PtIrO _x , PtRhO _x , Rh, TaAlN, or the like is used. It is also possible to insert a metal film that makes the orientation uniform. It is also possible to insert a buffer layer, a barrier metal layer, an adhesive layer, etc. separately.

  The variable resistance element VR has a resistance value changed by a phase transition between a crystalline state and an amorphous state such as chalcogenide (PCRAM), and deposits metal cations to form a bridging (contacting bridge) between the electrodes. Or change the resistance value by ionizing the deposited metal to break the bridge (CBRAM), there is no consistent theory (as a factor of resistance change, trapped in the charge traps present at the electrode interface) There are two main types: the resistance change due to the presence or absence of a charge, and the resistance change depending on the presence or absence of a conduction path due to oxygen deficiency. It is possible to use the one whose resistance value changes due to (ReRAM).

FIG. 4 is a diagram illustrating an example of the ReRAM. The variable resistance element VR shown in FIG. 4 has a recording layer 12 disposed between electrode layers 11 and 13. The recording layer 12 is composed of a composite compound having at least two kinds of cationic elements. At least one of the cation elements is a transition element having a d orbital incompletely filled with electrons, and the shortest distance between adjacent cation elements is 0.32 nm or less. Specifically, the formula _A x _M y _X z _(A and M are different elements) is represented by, for example, spinel structure _{(AM 2 O} 4), ilmenite structure _(AMO 3), delafossite structure _(AMO 2) , LiMoN ₂ structure _(AMN 2), wolframite structure _(AMO 4), olivine structure _(A 2 _MO 4), hollandite structure _(A x _MO 2), ramsdellite structure _(A x _MO 2), perovskite structure (AMO ₃ ) Or the like.

  In the example of FIG. 4, A is Zn, M is Mn, and X is O. Small white circles in the recording layer 12 represent diffusion ions (Zn), large white circles represent anions (O), and small black circles represent transition element ions (Mn). The initial state of the recording layer 12 is a high resistance state, but when a fixed potential is applied to the electrode layer 11 and a negative voltage is applied to the electrode layer 13 side, some of the diffused ions in the recording layer 12 move to the electrode layer 13 side. As a result, the diffusion ions in the recording layer 12 decrease relative to the anions. The diffused ions that have moved to the electrode layer 13 side receive electrons from the electrode layer 13 and are deposited as metal, so that the metal layer 14 is formed. Inside the recording layer 12, anions become excessive, and as a result, the lower layer of transition element ions in the recording layer 12 is raised. As a result, the recording layer 12 has electron conductivity by carrier injection, and the setting operation is completed. For reproduction, it is sufficient to pass a minute current value that does not cause a change in resistance of the material constituting the recording layer 12. In order to reset the program state (low resistance state) to the initial state (high resistance state), for example, a large current is allowed to flow through the recording layer 12 for a sufficient period of time to promote the oxidation-reduction reaction of the recording layer 12. good. The reset operation can also be performed by applying an electric field in the direction opposite to that at the time of setting.

  The non-ohmic element NO includes, for example, various diodes such as a Schottky diode, a PN junction diode, and a PIN diode, a MIM (Metal-Insulator-Metal) structure, a SIS structure (Silicon-Insulator-Silicon), and the like. Also here, electrodes EL2 and EL3 for forming a barrier metal layer and an adhesive layer may be inserted. Further, when a diode is used, a unipolar operation can be performed due to its characteristics, and a bipolar operation can be performed in the case of an MIM structure, an SIS structure, or the like. Note that the arrangement of the non-ohmic element NO and the variable resistive element VR may be upside down with respect to FIG. 3, or the polarity of the non-ohmic element NO may be reversed upside down.

Next, the operation in this embodiment will be described.
FIG. 5 is a circuit diagram showing the MAT 1 during the write (set) operation of the nonvolatile memory.

  The MAT 1 has, for example, 1024 word lines WL as the first wiring, and 512 bit lines BL as the second wiring intersecting with the word lines WL, for example. Further, at the intersection of each of the 1024 × 512 wirings, a diode Di which is a non-ohmic element NO whose anode is connected to the word line WL, and a variable resistance element connected between the cathode of the diode Di and the bit line BL A memory cell MC composed of VR is connected. The size of MAT1 is determined in consideration of the voltage drop of the word line WL and the bit line BL, the CR delay, the processing speed of the write operation, and the like, in addition to MAT1 shown in FIG. You can choose freely.

  Next, the writing operation for this MAT1 will be described. Here, a write operation to the memory cell MC1 surrounded by the dotted line in FIG. 5 connected to the intersection of the word line WL1 and the bit line BL1 will be described.

  In this case, a word line set voltage Vsetwl (for example, 3V) is applied to the word line WL1 connected to the memory cell MC1, and a bit line set voltage Vsetbl (for example, 0V) is applied to the bit line BL1. . As a result, a forward bias is applied to the diode Di of the memory cell MC1, so that the variable resistance element VR of the memory cell MC1 transitions to the low resistance state, and the write operation is completed.

  On the other hand, a word line non-selection voltage Vnswl (for example, 0 V) is applied to the word lines WL2,... Connected to the memory cells MC other than the memory cell MC1, and the bit lines BL2,. A bit line non-selection voltage Vnsbl (for example, 3 V) is applied. As a result, a reverse bias is applied to the diode Di of the memory cell MC, no current flows through the variable resistance element VR, and the resistance state does not transition.

  Although the write operation has been described above, the erase (reset) operation is performed except that a Joule heat is generated in the memory cell MC by applying a reset voltage lower than the set voltage for a longer period than the set voltage. It is the same.

  As described above, when data is written to only one memory cell MC1, heat is not generated from the other memory cells MC, and the entire cell array is less affected by heat generation, which is not a problem. However, since the memory cell MC is written one by one, it takes a considerable time to complete the write operation to all the memory cells MC included in the cell array.

  As a method for solving the above problem, it is conceivable to simultaneously write to a plurality of memory cells MC. In the following, a plurality of memory cells MC that are accessed simultaneously are referred to as a page.

  FIG. 6 is a circuit diagram showing MAT1 at the time of page unit write operation. Here, a case will be described in which writing is simultaneously performed on the memory cells MC2 to MC4 surrounded by a dotted line in FIG. 6 and connected to the word line WL1.

  In this case, the word line set voltage Vsetwl (3 V) is applied to the word line WL1. On the other hand, 0 V is applied as the bit line set voltage Vsetbl to the bit lines BL1 to BL3 connected to the memory cells MC2 to MC4. As a result, the diode Di of the memory cells MC2 to MC4 connected to the intersections of the word line WL1 and the bit lines BL1 to BL3 is forward biased, so that the variable resistance element VR of the memory cells MC2 to MC4 has a low resistance. A transition is made to the state, and a page-by-page write operation is performed. On the other hand, since no forward bias is applied to the diodes Di of the memory cells MC connected to the unselected word lines WL2, WL3, no current flows through the variable resistance elements VR of those memory cells MC, and the resistance state does not change. .

  The write operation has been described above. The erase operation is the same as the write operation except that Joule heat is generated in the memory cell MC by applying a reset voltage lower than the set voltage for a longer period than the set voltage. is there.

  As described above, since it is possible to simultaneously perform the write operation on the plurality of memory cells MC connected to the word line WL1, the write process can be performed more quickly than the case where the write operation is performed one by one.

  However, in this case, since a plurality of memory cells MC adjacent to each other generate heat at the same time, the influence of the adjacent memory cells and the heat generation of the entire cell array are larger than the operation of writing the memory cells one by one. This will impair the stability.

Next, a page unit write operation for the entire cell array will be described.
7 and 8 are schematic diagrams illustrating an example of the order of page-by-page write operations.
FIG. 7 shows a case where a write operation is sequentially performed on pages in the same MAT1 and a write operation is performed on each page of the next MAT1 after the write operation on pages included in all MAT1 is completed (S1 to S3). S4 to S6).

  In this case, since the write operation is performed in units of pages, not only the influence of heat generated simultaneously from the plurality of memory cells MC is large, but also the write operation is continuously performed in a short time on adjacent pages, so that the remaining heat amount As a result, the stability of the periphery of the page during the write operation may be significantly reduced.

  FIG. 8 shows a case in which after one page is sequentially written for each MAT1 (S11 to S18), the writing operation is again performed on one different page in which each MAT1 is not written (S19 to). By repeating this page unit write operation, the entire cell array write operation is performed.

  In this case, the write operation is performed on one page belonging to a predetermined MAT1, and then the write operation is performed on one page belonging to a different physically separated MAT1. Stability is improved because the influence of heat generated by the page writing operation is less likely to occur. However, even in this case, the write operation of each page is connected to one word line WL, and there is no change in that a plurality of physically close memory cells MC generate heat simultaneously. It cannot be said that it is sufficient to aim for stability.

  Further, for the erase operation, a collective operation in MAT1 units can be considered. Here, an erase operation for MAT1 surrounded by a dotted line in FIG. 9A will be described. FIG. 9B is a circuit diagram showing the MAT 1 surrounded by the dotted line in FIG.

  In this case, as shown in FIG. 9B, a word line reset voltage Vresetwl (for example, 1 V) lower than the word line set voltage Vsetwl (for example, 3 V) is applied to all the word lines WL, and all the bit lines A bit line reset voltage Vresetbl (for example, 0 V) is applied to BL. As a result, the diode Di of all the memory cells MC is forward-biased, the resistance state of the variable resistance element VR is changed to the high resistance state, and the erase operation is completed.

  As described above, since erasing is performed in units of MAT1, the erasing process can be made faster than erasing one memory cell MC or one page at a time. However, in this case, since many memory cells MC that are close to each other in the word line WL direction and the bit line BL direction generate heat at the same time, the nonvolatile memory is more insecure than the case where the memory cell MC or the page is erased. It is clear that qualitative increases.

  Therefore, in the present embodiment, as shown in FIG. 10, one memory cell MC is selected from each of the plurality of MATs 1, and the selected memory cells MC are collectively operated.

  As a result, even when writing and erasing operations are performed on the page surrounded by the dotted line in FIG. 10, each memory cell MC is separated from each other. The influence on MC can be reduced. Further, since the operation is performed in units of pages, the processing time is not inferior to the operations in units of pages shown in FIGS.

Hereinafter, a specific configuration of the present embodiment will be described.
FIG. 11 is a block diagram showing the cell array according to the first embodiment.
The cell array shown in FIG. 11 is divided into 12 partitions BLK, 4 columns in the x direction in which the word lines WL extend and 3 rows in the y direction in which the bit lines BL extend. In the following description, the upper section of FIG. 11 is BLK # 0, # 1, # 2, # 3 from the left, and the middle section is BLK # 4, # 5, # 6, # 7, and the lower section from the left. A certain partition is set as BLK # 8, # 9, # 10, and # 11.

Each partition BLK is provided with a MAT. Each MAT is assumed to have a total of 64 memory cells, 8 in the x direction and 8 in the y direction for simplification of description. The physical address of each memory cell of the MAT is allocated while increasing by 1 in the x direction and increasing by 8 in the y direction. That is, physical addresses 0, 7, 56, and 63 are assigned to the memory cells in the upper left corner, upper right corner, lower left corner, and lower right corner of each MAT.
Each MAT is provided with a column control circuit 2 and a row control circuit 3.

  Further, the MAT column control circuit 2 located in the partitions BLK # 0, # 4, and # 8 arranged in the y direction is connected to the IO pad 0 via the transfer transistors T0, T4, and T8. Similarly, the MAT column control circuit 2 located in the partitions BLK # 1, # 5, and # 9 is connected to the IO pad 1 via the transfer transistors T1, T5, and T9, and to the partitions BLK # 2, # 6, and # 10. The MAT column control circuit 2 located on the IO pad 2 via the transfer transistors T2, T6, and T10, and the MAT column control circuit 2 located on the partitions BLK # 3, # 7, and # 11 include the transfer transistors T3, Each is connected to the IO pad 3 via T7 and T11. The common input data selection signal IDST0 is input to the gates of the transfer transistors T0 to T3 arranged in the x direction. Similarly, common input data selection signals IDST1 and IDST2 are input to the gates of the transfer transistors T4 to T7 and T8 to T11, respectively. The input data selection signals IDST0 to IDST2 are signals determined based on the input address.

Next, allocation of logical addresses to the cell array configured as described above will be described.
FIG. 12 is a block diagram showing the MAT arrangement of the cell array and the logical addresses of the memory cells in this embodiment.
The MATs # 0 to # 11 are respectively arranged in the sections BLK # 0 to # 11 shown in FIG.

  If the physical address of each memory cell is i (i = 0, 1,...), The logical address of each memory cell in MATn is assigned to be n + 12 × i as shown in FIG. ing.

  Next, a write operation in units of pages with respect to the cell array to which the logical addresses are assigned will be described. Here, one page is made up of 12 memory cells, and the j (j = 1, 2,...) Page has logical addresses (j−1) × 12 to (j−1) × 12 + 11. It is assumed that the memory cell is configured. For example, in the case of the second page, it is composed of memory cells of logical addresses # 12 to # 23.

  First, input data given from the outside is transferred to the column control circuit 2 in each MAT via the IO pad. According to the configuration of FIG. 12, since there are four IO pads, when input data is transferred to the column control circuits 2 of all twelve MATs, it is necessary to transfer them in three steps. Specifically, first, 4-bit input data is prepared in IO pads 0-3. Thereafter, when the input data selection signal IDST0 becomes active (“H”), the transfer transistors T0 to T3 are turned on, and the IO pads 0 to 3 and the column control circuit 2 of the MATs # 0 to # 3 are connected. As a result, the input data in the IO pads 0 to 3 is transferred to the column control circuits 2 of the MATs # 0 to # 3. Next, the next 4-bit input data is prepared in IO pads 0-3. Thereafter, when the input data selection signal IDST1 becomes active, the transfer transistors T4 to T7 are turned on, and the IO pads 0 to 3 and the column control circuit 2 of the MATs # 4 to # 7 are connected. As a result, the input data in the IO pads 0 to 3 is transferred to the column control circuits 2 of the MATs # 4 to # 7. Similarly, the next 4-bit input data is transferred to the column control circuits 2 of MAT # 8 to # 11. As described above, 1-bit input data is prepared in the column control circuits 2 of all MATs # 0 to # 11. Here, the input data selection signals IDST0 to IDST2 are controlled to become sequentially active every operation cycle.

  In this state, each MAT simultaneously applies the word line set voltage Vsetwl (3 V) to the word line WL connected to the memory cell of the physical address # 0 and the bit line set voltage Vsetbl (3 V or 0 V) to the bit line BL. Apply. On the other hand, a word line non-selection signal Vnswl (0 V) is applied to the word lines WL connected to other memory cells, and a bit line non-selection voltage Vnsbl (3 V) is applied to the bit lines BL. As a result, the input data in the column control circuit 2 of each MAT is held in the memory cell at the physical address # 0, and the first page write operation is performed.

  By repeating the above for all pages, the write operation for the entire cell array is completed.

  Here, according to the configuration of FIG. 11, 12 bits of input data for one page are transferred separately to the column control circuit 2 of each MAT, but by preparing more IO pads than the above example, The number of transfers can be reduced. For example, if there are 12 IO pads, data for one page can be prepared by one transfer. On the other hand, even if there are few IO pads, it can be handled by increasing the number of transfers.

Next, the operation of the row control circuit 3 that realizes the above writing will be described.
FIG. 13 is a circuit diagram showing a part of the row control circuit 3.
The row control circuit 3 of each MAT 1 is supplied with an address for selecting a MAT via a global word line (Global Select) and local address lines (Block Select 1 to 3) provided to reduce the number of address lines. Further, an address for selecting a word line in the MAT is supplied via a local address line (not shown). As shown in FIG. 5A, transistors P1 and N1 to N3 are activated by a global word line (Global Select) and local address lines (Block Select 1 to 3) to select MAT. Further, the row control circuit 3 is provided with a latch circuit including inverters IV4 and IV5 and transistors N6 and N8 that are set or reset depending on whether or not each MAT is a defective block, thereby isolating the defective block. . When the transistors P1 and N1 to N4 are turned on, the transistor P2 is turned on, the transfer gate select n signal rises via the inverters IV1 and IV2, and the transfer gate synchronized with the trigger signal via the inverter IV3 and the transistor N5. The select signal falls.

  In response to the transfer gate select signal and the select n signal, a set voltage Vsetwl + α is supplied to a transfer gate (not shown) through transistors N9 and P3 as shown in FIG. A word line selection signal obtained by decoding the local address controls on / off of a transfer gate (not shown) via transistors N11 to N14 that are gate-controlled via a transistor N10. As a result, the set voltage Vsetwl + α is transferred to the selected word line WL of the selected MAT.

  Of these circuits, the global word line and the local address line may be configured with internal logic so that a plurality of MATs are selected simultaneously.

  According to the present embodiment, since it is possible to simultaneously perform a write operation on a plurality of memory cells constituting a plurality of pages, the time required for the write operation is shortened compared with the case where the memory cells are written one by one. be able to. Furthermore, since the memory cells that are simultaneously operated for writing are dispersed in different MATs and physically separated from each other, similarly to the case where the memory cells are operated for writing one by one, the influence of heat generation of each memory cell is small, A nonvolatile memory with high stability can be provided.

[Second Embodiment]
FIG. 14 is a block diagram showing the MAT arrangement of the cell array of the nonvolatile memory and the logical address of the memory cell according to the second embodiment.

  Compared to the first embodiment, the logical address allocation order for each MAT is changed.

  The logical addresses assigned to the memory cells belonging to each MAT are assigned with 12 differences as in the case of the first embodiment. However, in the case of this embodiment, each MAT is logically divided into two in the x direction, the logical address n is assigned to the memory cell of the physical address # 0 of MATn, the logical address n + 12 is assigned to the memory cell of the physical address # 4, and the physical address The logical address n + 24 is allocated to the memory cell at address # 2, and the logical address n + 36 is allocated to the memory cell at physical address # 5. Thus, in this embodiment, logical addresses are assigned alternately to the left part 1a and the right part 1b of the MAT.

  In this case, the memory cells of logical addresses # 0 to # 11 constituting the first page and the memory cells of logical addresses # 12 to # 23 constituting the second page are respectively in the x direction within the same MAT. It is arranged with a predetermined distance.

  That is, according to the present embodiment, not only can the influence of heat generation between the memory cells constituting one page be mitigated, but also the positional relationship between the memory cells constituting different pages is arranged at a predetermined distance. Therefore, the influence of heat generated by the memory cells constituting the page written immediately before does not easily affect the operation of the page during the writing operation. In this respect, the stability can be further improved as compared with the case of the first embodiment.

[Third Embodiment]
FIG. 15 is a block diagram showing the MAT arrangement of the cell array and the logical address of the memory cell of the nonvolatile memory according to the third embodiment.

  The logical addresses assigned to the memory cells belonging to each MAT are assigned with 12 differences, as in the first and second embodiments. However, in the present embodiment, each MAT is logically divided into two in the y direction. The logical address n is assigned to the memory cell of the physical address # 0 of MATn, the logical address n + 12 is assigned to the physical address # 32 of the memory cell of the physical address # 32. The logical address n + 24 is assigned to the memory cell at address # 1, and the logical address n + 36 is assigned to the memory cell at physical address # 33. Thus, in the present embodiment, logical addresses are alternately assigned to the upper part 1c and the lower part 1d of the MAT.

  Also in the present embodiment, since the memory cells constituting the jth page and the j + 1th page are arranged with a predetermined distance in the y direction, the same effect as in the second embodiment can be obtained. it can.

[Fourth Embodiment]
FIG. 16 is a block diagram showing the MAT arrangement of the cell array of the nonvolatile memory and the logical address of the memory cell according to the fourth embodiment.

  The logical addresses assigned to the memory cells belonging to each MAT are assigned with 12 differences, as in the first to third embodiments. However, in the case of this embodiment, each MAT is logically divided into two in the x direction and y direction, respectively, for a total of four, and the logical address n is assigned to the memory cell of the physical address # 0 located in the upper left portion 1e of MATn. , The logical address n + 12 in the memory cell of the physical address # 4 located in the upper right portion 1f, the logical address n + 24 in the memory cell of the physical address # 32 located in the lower left portion 1g, and the memory of the physical address # 36 located in the lower right portion 1h. A logical address n + 36 is assigned to each cell. Thus, in the present embodiment, logical addresses are sequentially assigned to the upper left part 1e, upper right part 1f, lower left part 1g, and lower right part 1h of the MAT.

  According to this embodiment, the memory cells constituting the j-th, j + 1-th, j + 2-th, and j + 3-th pages are arranged with a predetermined distance in the x-direction and the y-direction. In comparison, the influence of the write operation between pages can be further alleviated.

[Fifth Embodiment]
In the fifth embodiment, a page composed of 12 memory cells is written in half by two operations.

  FIG. 17 is a block diagram showing the MAT arrangement of the cell array of the nonvolatile memory and the logical address of the memory cell according to the fifth embodiment.

  Allocation of logical addresses of memory cells in each MAT is the same as in the second embodiment. However, in the case of the present embodiment, MATn and MAT (n + 1) are arranged with a distance of one MAT. Specifically, the partitions BLK # 0, # 2, # 4, # 6, # 8, and # 10 include MATs # 0 to # 5, partitions BLK # 1, # 3, # 5, # 7, # 9, and # 10. 11, MAT # 6 to # 11 are arranged.

  In this logical address assignment, first, a write operation is performed on memory cells of logical addresses # 0 to # 5 among the memory cells constituting the first page. Next, a write operation is performed on the remaining memory cells of logical addresses # 6 to # 11 constituting the first page. One page can be written by these two writings. By repeating the above process for all pages, writing to the entire cell array is completed.

  According to the present embodiment, since the writing of one page is divided into two times, the writing process is delayed as compared with the first to fourth embodiments. However, since the memory cells that operate in the first writing for each page are arranged separated by one MAT in the x direction, the influence of the heat generation of the memory cells is more significant than in the first to fourth embodiments. Can be relaxed. Furthermore, since power consumed at a time is reduced, it is effective for power consumption measures.

  In the present embodiment, writing of one page is performed twice, but this number can be arbitrarily set in consideration of the speed of the writing process, power consumption, and the like.

[Sixth Embodiment]
FIG. 18 is a block diagram showing the MAT arrangement of the cell array of the nonvolatile memory and the logical address of the memory cell according to the sixth embodiment.

  In the present embodiment, the column control circuit 2 in the first embodiment is replaced with a new column control circuit 2 ′.

  Unlike the column control circuit 2, the column control circuit 2 ′ is characterized in that it includes a plurality of sense amplifier circuits S / A. Thereby, since a plurality of bit lines can be selected for each MAT, among the plurality of memory cells connected to the same word line, a write operation to the number of memory cells corresponding to the number of sense amplifiers S / A is performed simultaneously. Can do.

Next, the sense amplifier circuit S / A shown in FIG. 19 will be described.
A node TDC shown in FIG. 19 is a sense node for sensing the bit line voltage and a data storage node for temporarily storing data. The node TDC is connected to the bit line BL via the clamping NMOS transistor N101. The clamping transistor N101 functions to clamp the bit line voltage at the time of reading and transfer it to the node TDC. A bit line and a precharging NMOS transistor N102 for precharging the node TDC are connected to the node TDC.

  The node TDC is connected to the data storage nodes PDC and SDC of the data latches 112 and 113 via transfer NMOS transistors N103 and N104, respectively. The data latch 112 is a data storage circuit that holds read data and write data. The data latch 113 is a data cache that is disposed between the data latch 112 and the data lines IO and IOn and is used to temporarily hold write data and read data.

  The node of the data latch 113 is connected to the data line pair IO, IOn of the data bus 109 via the selection gate transistors N105, N106 driven by the column selection signal CSL.

  The selection gate transistors N105 and N106 are automatically turned on / off in conjunction with the column address.

  Data writing is performed by repeatedly applying a write voltage and writing verify in order to obtain a predetermined threshold distribution. Verification is performed for each sense amplifier included in each MAT, and it is necessary to determine write data for the next cycle based on the verification result.

  The gate of the NMOS transistor N111 to which the voltage VPRE is applied to the drain serves as a data storage node DDC for temporarily storing and holding the write data held by the node PDC of the data latch 112 at the time of writing. Write data in the node PDC of the data latch 112 is transferred to the data storage node DDC via the transfer NMOS transistor N114. The voltage VPRE is selectively Vdd or Vss.

  With the NMOS transistor N117 interposed between the NMOS transistor N111 and the data storage node TDC, it becomes possible to set the data of the data storage node TDC in accordance with the data of the data storage node DDC. That is, the NMOS transistors N111 and N117 constitute a write back circuit for writing back the write data of the next cycle to the storage node TDC at the time of writing.

  According to the data held in these data storage nodes DDC and BDC, and according to the selection of the drain voltage VPRE of the transistors N111 and N112, the data node TDC is forcibly discharged at the time of verify reading (ie, set to “L” level). Alternatively, it is possible to perform control such as charging (that is, setting to “H” level).

  A verify check circuit 114 is connected to the data latch 112. The NMOS transistor N122 whose gate is connected to one node of the data latch 112 is a check transistor, the source of which is grounded via an NMOS transistor N121 controlled by a check signal CHK1, and the drain of which is a transfer NMOS provided side by side. It is connected to a common signal line COM common to sense units for one page via transistors N123 and N124. The gates of the NMOS transistors N123 and N124 are controlled by the check signal CHK2 and the node TDC, respectively.

  Only when “0” write is insufficient as a result of the verify read, write-back in which the node PDC of the data latch 112 becomes “L” (= “0”) is performed. That is, when the writing of one page is completed, the verify control is performed so that the data latch 112 becomes all “1”.

  At the time of data writing, the verify check circuit 114 is turned on in the sense unit for one page after the verify read. If writing is not completed in a certain sense unit, the verify check circuit 114 discharges the common signal line COM that has been charged to “H” in advance. When the data latches 112 for one page are all in the “1” state, the common signal line COM is maintained at “H” without being discharged, and this becomes a pass flag indicating the completion of writing.

  In the present embodiment, as described in the first embodiment, for example, when there is a 4-bit data input at a time, it is possible to load data into 4 MATs one bit at a time, and a plurality of senses for each MAT. By providing the amplifier circuit S / A, the following data input is possible.

  For example, if there are 16 sense amplifier circuits for each MAT, 4 bits of input data are continuously loaded into one MAT four times. By repeating this operation sequentially for the next MAT, data loading for all MATs can be performed.

  As another example, the first 4-bit input data is loaded into a predetermined MAT, and the next 4-bit input data is loaded into the next MAT. By repeating the above operation, the number of data to be loaded for each MAT can be adjusted. This makes it possible to adjust the number of MATs that operate simultaneously during writing and erasing, or the number of sense amplifier circuits S / A.

  Note that the number of sense amplifier circuits S / A included in one MAT can be arbitrarily determined in consideration of an arrangement space immediately below the MAT, power consumption during an erase operation, the influence of heat generation of the memory cell, and the like. Furthermore, as described above, since the number of MATs to be simultaneously operated and the number of memory cells (or sense amplifier circuits S / A) to be simultaneously operated per MAT can be controlled, a more flexible device design is possible. .

  For example, in the case of this embodiment, the number of sense amplifier circuits S / A provided in one MAT can be determined to be about 16 to 32 in consideration of the arrangement space immediately below the cell array. In this case, at the time of a write operation in which the power consumption is relatively small and the influence of heat generation of the memory cell is small, the number of memory cells to be operated simultaneously per MAT is 16 to 32, which is the same as that of the sense amplifier circuit S / A. . On the other hand, during the erase operation, which consumes more power than the write operation and is greatly affected by heat generation between the memory cells, the number of MATs to be simultaneously operated and the number of memory cells to be simultaneously operated per MAT are controlled to be smaller. As a result, it is possible to ensure the stability during the erase operation while ensuring the high-speed operation during the write operation.

  According to the present embodiment, not only the same effects as in the first embodiment can be obtained, but also the writing process can be performed at a higher speed than in the first embodiment.

  Further, the column control circuit 2 ′ of the present embodiment can be similarly applied to the second to fifth embodiments.

[Others]
Although several embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, when MAT # 11,..., # 0 are arranged in the cell array partitions BLK # 0,..., # 11 as shown in FIG. Each MAT may be arranged so that the positions of memory cells constituting different pages are separated from each other, or a logical address may be assigned.

  In the above embodiment, the write operation is mainly described, but the same applies to the erase operation.

  Furthermore, the present invention can be applied to various semiconductor memory devices other than the nonvolatile memory.

  DESCRIPTION OF SYMBOLS 1 ... MAT (unit cell array) 2, 2 '... Column control circuit, 3 ... Row control circuit, 4 ... Data input / output buffer, 5 ... Address register, 6 ... Command I / F, 7 ... controller, 8 ... R / W circuit, 11, 13 ... electrode layer, 12 ... recording layer, 14 ... metal layer, 112, 113 ... data latch 114 ... Verify check circuit, BL ... Bit line, Di ... Diode, EL ... Electrode, MC ... Memory cell, NO ... Non-ohmic element, S / A ... Sense Amplifier circuit, VR: variable resistance element, WL: word line.

Claims (5)

A plurality of MATs (unit cell arrays) arranged in a matrix, and each of the plurality of MATs separately includes a plurality of first wirings, a plurality of second wirings intersecting with the plurality of first wirings; A cell array having a memory cell composed of a series circuit of a variable resistance element and a non-ohmic element which are electrically rewritable and which store resistance values in a nonvolatile manner as data connected at both intersections of the first and second wirings When,
A plurality of access circuits connected to each of the plurality of MATs;
Each of the plurality of access circuits simultaneously accesses the same number of memory cells in the corresponding MAT ;
A group is formed by the plurality of memory cells accessed simultaneously,
A plurality of memory cells included in another group having addresses logically adjacent to the plurality of memory cells included in the predetermined group;
A plurality of memory cells included in the predetermined group and a plurality of memory cells included in the other group are arranged in a predetermined direction and spaced apart by one or more memory cells . Semiconductor memory device. A plurality of MATs (unit cell arrays) arranged in a matrix, and each of the plurality of MATs separately includes a plurality of first wirings, a plurality of second wirings intersecting with the plurality of first wirings; A cell array having a memory cell composed of a series circuit of a variable resistance element and a non-ohmic element which are electrically rewritable and which store resistance values in a nonvolatile manner as data connected at both intersections of the first and second wirings When,
A plurality of access circuits connected to each of the plurality of MATs;
With
Each of the plurality of access circuits simultaneously accesses the same number of memory cells in the corresponding MAT;
A group is formed by the plurality of memory cells accessed simultaneously,
A plurality of memory cells included in another group having addresses logically adjacent to the plurality of memory cells included in the predetermined group;
Each of the memory cells in each of the groups is included in the different MATs and is spaced apart by one or more MATs in a predetermined direction.
A non-volatile semiconductor memory device. A global word line and a local address line;
Each of the plurality of access circuits includes a row control circuit connected to the global word line and the local address line;
Wherein the plurality of access circuits, the nonvolatile semiconductor memory device according to claim 1, wherein selecting said plurality of MAT simultaneously. A buffer;
When n-bit (n is an integer of 2 or more) data is input, the n-bit data is transferred bit by bit to the n access circuits via the buffer. Item 4. The nonvolatile semiconductor memory device according to any one of Items 1 to 3 . The nonvolatile semiconductor memory device according to claim 4, wherein each of the n access circuits accesses one memory cell of the corresponding MAT.

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