JP5368717B2 - Display device and Cu alloy film used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Cu alloy film for a display apparatus which is excellent in adhesiveness to an insulating film (for example, SiN film) while maintaining low electric resistivity that is a characteristic of Cu based material. <P>SOLUTION: The Cu alloy film is used for a source electrode and/or drain electrode as well as a signal line and/or a gate electrode and a scan line of a thin film transistor of a display apparatus, and contains Ge by 0.1-0.5 atom%. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention relates to a display device and a Cu alloy film used therefor, and in particular, a thin film transistor (Thin Film Transistor, hereinafter referred to as TFT) in a display device (for example, a flat panel display such as a liquid crystal display or an organic EL display). Source electrode and / or drain electrode and signal line, and / or
A Cu alloy film used for the gate electrode and the scanning line, and the liquid crystal display in which the Cu alloy film is used for the source electrode and / or the drain electrode and the signal line and / or the gate electrode and the scanning line, The present invention relates to a display device such as an organic EL display and a sputtering target used for forming the Cu alloy film. In the following, a liquid crystal display will be described as an example of the display device, but it is not intended to be limited to this.

  For example, liquid crystal displays are used in various fields ranging from small mobile phones to large televisions exceeding 100 inches. This liquid crystal display is classified into a simple matrix type liquid crystal display and an active matrix type liquid crystal display according to a pixel driving method. Of these, active matrix liquid crystal displays incorporating TFTs as switching elements are the mainstream of liquid crystal displays because of their high image quality and high-speed moving images.

  FIG. 1 shows a configuration of a typical liquid crystal display applied to an active matrix liquid crystal display. The configuration and operating principle of this liquid crystal display will be described with reference to FIG.

  First, the liquid crystal display 100 includes a TFT substrate 1, a counter substrate 2 disposed to face the TFT substrate 1, and a liquid crystal layer 3 that is disposed between the TFT substrate 1 and the counter substrate 2 and functions as a light modulation layer. Are unit pixel units, which are arranged in a two-dimensional array.

  The TFT substrate 1 has a TFT 4 disposed on an insulating glass substrate 1a, a pixel electrode (transparent conductive film) 5, and a wiring portion 6 including a scanning line and a signal line.

  The counter substrate 2 includes a common electrode 7 formed on the entire surface of the glass plate, a color filter 8 disposed at a position facing the pixel electrode (transparent electrode film) 5 on the TFT substrate 1 side, and the TFT substrate 1. And a light shielding film 9 disposed at a position facing the TFT 4 and the wiring portion 6. The counter substrate 2 further has an alignment film 11 for aligning liquid crystal molecules contained in the liquid crystal layer in a predetermined direction.

  Polarizing plates 10a and 10b are disposed outside the TFT substrate 1 and the counter substrate 2 (opposite the liquid crystal layer), respectively.

  In the liquid crystal display 100, in each pixel, the electric field between the counter substrate 2 and the pixel electrode (transparent conductive film) 5 is controlled by the TFT 4, and the orientation of the liquid crystal molecules in the liquid crystal layer 3 is changed by this electric field. The light passing through 3 is modulated (shielded or translucent). As a result, the amount of light transmitted through the counter substrate 2 is controlled and displayed as an image.

  A backlight 22 is installed in the lower part of the liquid crystal display 100, and this light passes from the lower part to the upper part in FIG.

  Further, the TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected via a TAB tape 12.

  FIG. 2 is an enlarged view of a main part A in FIG. In FIG. 2, a scanning line (gate wiring) 25 is formed on the glass substrate 1a, and a part of the scanning line 25 functions as a gate electrode 26 for controlling on / off of the TFT. A gate insulating film (SiN) 27 is formed so as to cover the gate electrode 26. A signal line (source-drain wiring) 34 is formed so as to intersect the scanning line 25 via the gate insulating film 27, and a part of the signal line 34 functions as a source electrode 28 of the TFT. On the gate insulating film 27, an amorphous silicon channel layer (active semiconductor layer), a signal line (source-drain wiring) 34, and a passivation film (protective film, SiN) 30 are sequentially formed. This type is generally called a bottom gate type.

The pixel region on the gate insulating film 27, for example _(In 2 _{O 3)} tin oxide in an indium oxide-tin containing (SnO) about 10 wt% (Indium Tin OXide; ITO) film _{or, (In 2 O} 3) A pixel electrode (transparent conductive film) 5 formed by an indium zinc oxide (IZO) film containing zinc oxide is disposed therein. In FIG. 2, the drain electrode 29 of the TFT is a pixel electrode (transparent electrode). The conductive film) 5 is in direct contact with and electrically connected.

  When a gate voltage is applied to the TFT substrate via the scanning line to the gate electrode 26, the TFT 4 is turned on, and the driving voltage previously applied to the signal line passes from the source electrode 28 to the pixel via the drain electrode 29. Applied to the electrode (transparent conductive film) 5. When a predetermined level of driving voltage is applied to the pixel electrode (transparent conductive film) 5 in this way, a sufficient potential difference is generated between the counter substrate 2 and the liquid crystal molecules contained in the liquid crystal layer 3 are aligned. Light modulation occurs.

  In addition, a reflective electrode (not shown) may be provided on the TFT to improve luminance. Further, the pixel electrode may be in contact with the reflective electrode.

  Although a voltage is applied between the source electrode 28 and the drain electrode 29 of the TFT shown in FIG. 2, the voltage of the gate electrode 26 is controlled to be turned ON / OFF, so that the voltage from the source electrode 28 can be reduced via the channel layer. The current to the drain electrode 29 is controlled, and the electric field of the liquid crystal layer 3 is controlled via the pixel electrode 5. As a result, the light transmission amount of each pixel is modulated, and a moving image can be displayed.

  The source-drain wiring 34, the scanning line 25, and the gate electrode 26 are formed from a thin film of an Al alloy such as Al-Nd for reasons such as easy processing.

However, in recent years, due to circumstances such as an increase in the size of a liquid crystal display and a change in operating frequency from 60 kHz to 120 kHz, further reduction of the electrical resistance of wiring has become an essential issue, and wiring that exhibits a lower electrical resistivity There is a growing need for materials. Therefore, the electrical resistivity is lower than that of Al-based materials such as pure Al and Al alloys, mainly in large panels for television applications (the electrical resistivity of metal [bulk material] is 2.7 × 10 ^{− While} Cu is ⁶ Ω · cm, pure Cu is 1.8 × 10 ⁻⁶ Ω · cm), and a Cu-based material having excellent hillock resistance has attracted attention.

  However, when a Cu-based material is applied to the wiring, there is a problem that the adhesion with a glass substrate or an insulating film (for example, a gate insulating film) is poor. In particular, when forming on an insulating film, there are the following problems. That is, a SiN film formed by normal CVD is used as the insulating film. Conventionally used electrodes / wirings made of Al-based materials have good adhesion to insulating films, but electrodes / wirings made of Cu-based materials (Cu-based electrodes / wirings) are insulating films (especially insulating films). Adhesiveness to the SiN film) is poor, and there is a problem that the Cu-based electrode / wiring is peeled off from the insulating film (SiN film). However, improvement in adhesion with an insulating film (SiN film) has not been sufficiently studied yet.

  Therefore, in a conventional liquid crystal display employing a Cu-based electrode / wiring, a structure in which a base film (Mo-containing base layer such as a pure Mo layer or Mo-Ti alloy layer) is interposed between the SiN film and the Cu-based electrode / wiring. Is taking. That is, there is an example in which a wiring having a two-layer structure in which a pure Cu thin film is formed on a Mo-containing underlayer is used. However, in such a two-layer structure wiring, since the Mo-containing base layer having a high electrical resistivity is on the wiring base, the wiring resistance (effective wiring resistance) of the entire two layers becomes high; the process becomes complicated However, since thin films of different materials are stacked, it is difficult to control the taper by wet etching when patterning into a wiring shape.

  The present invention has been made in view of such circumstances, and the object thereof is excellent in adhesion to an insulating film (for example, a SiN film) while maintaining the low electrical resistivity characteristic of the Cu-based material. Cu alloy film, and a flat panel display represented by, for example, a liquid crystal display, which is used without forming the Mo-containing underlayer on the TFT (particularly, the source electrode and / or drain electrode and signal line of the TFT). (Display device) is to be provided. Another object of the present invention is to provide a sputtering target for forming a Cu alloy film having excellent performance as described above.

The Cu alloy film for a display device according to the present invention is a thin film transistor source electrode and / or drain electrode and a signal line in the display device, and / or
A Cu alloy film used for gate electrodes and scanning lines, characterized by containing 0.1 to 0.5 atomic percent of Ge.

Further, according to the present invention, the Cu alloy film for a display device includes: a thin film transistor, a source electrode and / or a drain electrode, a signal line, and / or
-It also includes a display device characterized in that it is used for gate electrodes and scanning lines.

  As the display device, the thin film transistor has a bottom-gate structure, and a part of the source electrode and / or drain electrode is formed on an insulating film (particularly a silicon nitride film). Since the effect of Cu alloy film is fully exhibited, it is preferable.

  The present invention also includes a sputtering target used for forming the Cu alloy film, which is made of a Cu alloy containing 0.1 to 0.5 atomic% of Ge.

  ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which has a Cu alloy film | membrane of the low electrical resistivity which can respond to the enlargement of a liquid crystal display and the raise of an operating frequency is realizable. In addition, since the Cu alloy film of the present invention is excellent in adhesion to an insulating film (particularly, a SiN film), the Mo-containing underlayer is applied to a source-drain wiring for a display device (for example, a liquid crystal display). It is possible to provide a high-performance display device in which the Mo-containing base layer can be omitted.

  The present inventors have disclosed a Cu alloy film having excellent adhesion to an insulating film (for example, a silicon nitride film) while maintaining the low electrical resistivity characteristic of a Cu-based material, and a display device using the same in a TFT We conducted intensive research to realize this. As a result, a specific method was found based on the idea that a Cu alloy film containing a small amount of Ge may be used. Hereinafter, the present invention will be described in detail.

  The Cu alloy film of the present invention contains 0.1 to 0.5 atomic% (at%) of Ge (hereinafter, such Cu alloy film of the present invention is particularly referred to as “Cu—Ge-containing alloy film”). There). In the present invention, it has been found that the adhesion to an insulating film is remarkably improved by containing 0.1 atomic% or more (preferably 0.15 atomic% or more, more preferably 0.20 atomic% or more) of Ge. It was.

  The reason why the high adhesiveness is expressed by adding Ge in this way is not sufficiently elucidated, but when silicon nitride (hereinafter sometimes referred to as “SiN”) is used for the insulating film, The following are considered.

  That is, the SiN film formed by CVD contains a small amount of oxygen. When a pure Cu film is formed on the SiN film, Cu constituting the pure Cu film reacts with the oxygen at the interface between the pure Cu film and the SiN film (hereinafter referred to as “Cu / SiN interface”) to form an oxide. Is formed. Due to this oxide formation, residual stress is generated at the Cu / SiN interface, and the adhesion between the pure Cu film and the SiN film is lowered.

On the other hand, when a Cu—Ge containing alloy film is formed on the SiN film, oxygen and Ge contained in the SiN film react preferentially, and oxygen is exchanged between the Cu—Ge containing alloy film and the SiN film ( Hereinafter, the Cu—Ge containing alloy film is drawn from the “Cu alloy / SiN interface” to the Cu—Ge containing alloy film side (ie, the Cu—Ge containing alloy film instead of the above interface). It is thought that an oxide (GeO ₂ ) is formed in the middle. As a result, no oxide is formed at the Cu alloy / SiN interface, and no residual stress is generated at the Cu alloy / SiN interface, so the adhesion between the Cu—Ge-containing alloy film and the SiN film is expected to improve. . In addition, there is a possibility that GeO ₂ is formed at the Cu alloy / SiN interface, and through this, high adhesion between the Cu—Ge containing alloy film and the SiN film is expressed. Further, when the insulating film is silicon nitride, since Si and Ge are elements of the same group in the periodic table and have high chemical affinity, Ge in the Cu—Ge-containing alloy film and Si in the SiN film are chemical. It is also considered as a reason for improving the adhesion by forming a proper bond to improve the adhesion at the interface.

  In the above description, the case where a silicon nitride film is used as the insulating film has been described. However, the present invention is not limited to this, and the insulating film may include other insulating films that can contain a small amount of oxygen; an aluminum nitride film, a titanium nitride film. In some cases, a Cu-Ge-containing alloy film may be formed on a tantalum nitride film or the like.

  The above effect is exhibited when the Ge content is 0.1 atomic% or more, and the adhesiveness increases as the Ge content increases. However, the effect is saturated even when the Ge content is excessive. Further, since the electrical resistivity increases as the Ge content increases, the Ge content needs to be suppressed to 0.5 atomic% or less. From the viewpoint of keeping the electrical resistivity lower, Ge is preferably 0.2 atomic% or less.

  The Cu—Ge-containing alloy film is excellent in adhesion even in an as-deposited state, but exhibits excellent adhesion even when post-annealing (heat treatment up to 350 ° C. after film formation) is performed.

  The Cu-Ge-containing alloy film contains the specified amount of Ge, and the remainder is Cu and inevitable impurities. Examples of the inevitable impurities include oxygen, nitrogen, carbon, argon, and the like. Atomic% or less.

  Moreover, the following elements can also be positively added for the purpose of imparting other characteristics within a range not impairing the action of the present invention. That is, when the Cu—Ge-containing alloy film is applied to, for example, a source electrode and / or drain electrode and a signal line of a TFT having a bottom gate type structure, its characteristics are “adhesion with an SiN film as an insulating film”, “Oxidation resistance (contact stability with ITO film (low contact resistance))”, “diffusion suppression to α-Si constituting semiconductor film (ensuring stability of TFT characteristics)”, “corrosion resistance”, etc. are required. . Among these, by adding Ge, the above-mentioned “adhesion with the SiN film” and further “oxidation resistance (contact stability with ITO film (low contact resistance))” can be secured. Therefore, a third element may be added in order to further improve the “suppression of diffusion into α-Si” and the “corrosion resistance”.

  Further, in order to ensure adhesion to the glass used as the substrate, the third element is selected from the group consisting of Ni, Pt, Au, Ce, Ru, W, Cr, Ir, Mo, Fe, Al and Zr. It is effective to contain one or more of the above-described elements, and the multi-element Cu—Ge-containing alloy film containing the third element is applied to the gate electrode and the scanning line, the source electrode and / or the drain. It can also be used for electrodes and signal lines.

In addition, the Cu-Ge-containing alloy film is used for the TFT source electrode and / or drain electrode and signal line, and / or
-When used for a gate electrode and a scanning line, a lower electrical resistivity may be required. When the Ge content is increased to give properties other than the low electrical resistivity, the electrical resistivity increases as described above. However, in order to further reduce the electrical resistivity while containing Ge, Ni, It is effective to contain one or more selected from the group consisting of Zn, Fe and Co.

  It is desirable to employ a sputtering method for forming the Cu—Ge-containing alloy film. In sputtering, an inert gas such as Ar is introduced into a vacuum, a plasma discharge is formed between a substrate and a sputtering target (hereinafter sometimes referred to as a target), and Ar ionized by the plasma discharge is formed. This is a method of making a thin film by colliding with the target and knocking out atoms of the target and depositing them on a substrate. Compared to thin films formed by ion plating, electron beam vapor deposition, or vacuum vapor deposition, it is easier to form thin films with better in-plane uniformity of components and film thickness, and alloy elements are in an as-deposited state. Since a uniformly thin film can be formed, high-temperature oxidation resistance can be effectively expressed. As the sputtering method, for example, any sputtering method such as a DC sputtering method, an RF sputtering method, a magnetron sputtering method, or a reactive sputtering method may be employed, and the formation conditions may be set as appropriate.

  Further, in order to form the Cu—Ge containing alloy film by the sputtering method, the target is made of a Cu alloy containing 0.1 to 0.5 atomic% of Ge, and a desired Cu— If a Cu—Ge containing alloy sputtering target having the same composition as that of the Ge containing alloy film is used, a Cu—Ge containing alloy film having a desired component / composition can be formed without causing a composition shift.

  The shape of the target includes those processed into an arbitrary shape (such as a square plate shape, a circular plate shape, or a donut plate shape) according to the shape or structure of the sputtering apparatus.

  As a method for producing the above target, a method for producing an ingot made of a Cu-based alloy by a melt casting method, a powder sintering method, or a spray forming method, or a preform made of a Cu-based alloy (the final dense body is formed). Examples thereof include a method obtained by producing an intermediate before being obtained) and then densifying the preform by a densification means.

The Cu alloy film of the present invention (Cu-Ge-containing alloy film)
Thin-film transistor source electrode and / or drain electrode and signal line in display device, and / or
-It is used for a gate electrode and a scanning line, and the characteristic of a Cu-Ge containing alloy film is fully exhibited by applying to this location.

  In the present invention, it is particularly preferable that the TFT has a bottom gate structure, and a part of the source electrode and / or drain electrode is formed on an insulating film (particularly a silicon nitride film). Form.

  In addition, when using a Cu-Ge containing alloy film in multiple places of a source electrode and / or a drain electrode, a signal line, and / or a gate electrode, and a scanning line, the composition of a mutual Cu-Ge containing alloy film corresponds. The composition may be different within the specified range.

  Hereinafter, preferred embodiments of a display device of the present invention will be described with reference to the drawings. In the following, a liquid crystal display including an amorphous silicon TFT substrate will be described as a representative example, but the present invention is not limited to this, and is implemented with appropriate modifications within a range that can meet the purpose described above and below. All of which are within the scope of the present invention.

  In FIG. 2, the source electrode 28 and the drain electrode 29, the signal line (not shown in FIG. 2), and / or the scanning line (gate wiring) 25 and the gate electrode 26 are made of Cu—Ge containing alloy film (for example, Cu -0.3 atomic% Ge alloy film) can be cited as an embodiment.

  According to the present embodiment, the Cu—Ge containing alloy film can be directly laminated on the insulating film without interposing the Mo containing base layer as in the prior art, and the same or better than the conventional TFT substrate. TFT characteristics can be realized (see examples described later).

  Next, a manufacturing method of the TFT substrate according to the present embodiment shown in FIG. 2 will be described with reference to FIGS. 3 to 9 are given the same reference numerals as in FIG.

  First, as shown in FIG. 3, a Cu—Ge-containing alloy film (for example, Cu-0.3 atomic% Ge alloy film) having a thickness of about 200 nm is formed on a glass substrate (transparent substrate) 1a using a sputtering method. Film. By patterning this film, the gate electrode 26 and the scanning line 25 are formed. At this time, in FIG. 4 to be described later, the side surface of the alloy film is preferably etched into a taper shape having an inclination angle of about 30 ° to 60 ° so that the coverage of the gate insulating film 27 is improved.

  Next, as shown in FIG. 4, a gate insulating film (SiN film) 27 having a thickness of about 300 nm is formed by using a method such as plasma CVD. The film formation temperature of the plasma CVD method may be about 350 ° C. Subsequently, a hydrogenated amorphous silicon film (a-Si: H) having a thickness of about 50 nm and a silicon nitride film (SiNx) having a thickness of about 300 nm are formed on the gate insulating film 27.

Subsequently, as shown in FIG. 5, the silicon nitride film (SiNx) is patterned by backside exposure using the gate electrode 26 as a mask to form a channel protective film. Furthermore, as shown in FIG. 6, after forming an n ⁺ type hydrogenated amorphous silicon film (n ⁺ a-Si: H) doped with phosphorus and having a thickness of about 50 nm, a hydrogenated amorphous silicon film ( a-Si: H) and n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si: H) are patterned.

  Then, as shown in FIG. 7, a sputtering method is used to form a Cu—Ge-containing alloy film (for example, Cu-0.3 atomic% Ge alloy film) having a thickness of about 300 nm, and then patterning, thereby forming a signal. A source electrode 28 integrated with the line and a drain electrode 29 directly connected to the pixel electrode (transparent conductive film) 5 are formed.

  Then, as shown in FIG. 8, a protective film is formed by forming a silicon nitride film 30 with a film thickness of, for example, about 300 nm using, for example, a plasma CVD apparatus. The film formation at this time is performed at about 250 ° C., for example. Then, after a photoresist layer 31 is formed on the silicon nitride film 30, the silicon nitride film 30 is patterned, and contact holes 32 are formed in the silicon nitride film 30 by, for example, dry etching. Although not shown, a contact hole is formed at a portion corresponding to connection with TAB on the gate electrode at the end of the panel at the same time.

  Further, as shown in FIG. 9, after passing through an ashing process using, for example, oxygen plasma, the photoresist layer 31 is stripped using, for example, an amine-based stripping solution, and finally, as shown in FIG. A pixel electrode (transparent conductive film) 5 is formed by forming an ITO film having a thickness of about 40 nm and performing patterning by wet etching.

  In the above description, an ITO film is used as the pixel electrode (transparent conductive film) 5, but an IZO film (InOx—ZnOx-based conductive oxide film) may be used. Further, polysilicon may be used as the active semiconductor layer instead of amorphous silicon.

  Using the TFT substrate thus obtained, for example, the liquid crystal display shown in FIG. 1 is manufactured by the method described below.

  First, for example, polyimide is applied to the surface of the TFT substrate 1 manufactured as described above and dried, and then a rubbing process is performed to form an alignment film.

  On the other hand, the counter substrate 2 forms the light shielding film 9 on the glass substrate by patterning, for example, Cr in a matrix. Next, resin-made red, green, and blue color filters 8 are formed in the gaps between the light shielding films 9. A counter electrode is formed by disposing a transparent conductive film such as an ITO film as the common electrode 7 on the light shielding film 9 and the color filter 8. Then, for example, polyimide is applied to the uppermost layer of the counter electrode, and after drying, a rubbing process is performed to form the alignment film 11.

  Next, the TFT substrate 1 and the counter substrate 2 are arranged so as to face each other on the surface on which the alignment film 11 is formed, and the TFT substrate 1 and the counter substrate are removed by a sealing material 16 made of resin, excluding the liquid crystal sealing port. 2 and pasted together. At this time, a gap between the two substrates is kept substantially constant by interposing a spacer 15 between the TFT substrate 1 and the counter substrate 2.

  The empty cell thus obtained is raised in a vacuum, and gradually returned to atmospheric pressure with the sealing port immersed in liquid crystal, thereby injecting a liquid crystal material containing liquid crystal molecules into the empty cell to form a liquid crystal layer. Form and seal the sealing port. Finally, polarizing plates 10a and 10b are attached to both sides of the empty cell to complete the liquid crystal panel.

  Next, as shown in FIG. 1, the driver circuit 13 for driving the liquid crystal display is electrically connected to the liquid crystal display and disposed on the side portion or the back surface portion of the liquid crystal display. Then, the liquid crystal display is held by the holding frame 23 including the opening serving as the display surface of the liquid crystal display, the backlight 22 serving as the surface light source, the light guide plate 20, and the holding frame 23, thereby completing the liquid crystal display.

  Note that the Cu—Ge-containing alloy film of the present invention can also be applied to a gate electrode and a scanning line formed on an insulating film in a TFT having a top gate structure.

  Hereinafter, the present invention will be described in more detail with reference to examples. However, the following examples are not intended to limit the present invention, and may be implemented with appropriate modifications within a range that can meet the purpose described above and below. These are all possible and are within the scope of the present invention.

[Example 1]
In order to evaluate the adhesion between the Cu alloy film and the SiN film, the following peeling test using a tape was performed.

(Sample preparation)
First, a 200 nm SiN film was formed by CVD on a glass substrate (Corning Eagle 2000, diameter 50 mm × thickness 0.7 mm), and further on the SiN film by a DC magnetron sputtering method (deposition conditions are as follows). At room temperature, a pure Cu film, a pure Mo film, or a Cu alloy film having the components and compositions shown in Table 1 was formed to a thickness of 300 nm to prepare a sample. In addition, pure Cu and pure Mo are used for the sputtering target for forming the pure Cu film and pure Mo film, respectively, and elements other than Cu are included on the pure Cu sputtering target for forming the Cu alloy film of various components. A target with a chip was used.

(Deposition conditions)
・ Back pressure: 1.0 × 10 ⁻⁶ Torr or less ・ Ar gas pressure: 2.0 × 10 ⁻³ Torr
Ar gas flow rate: 30sccm
Sputtering power: 3.2 W / cm ²
・ Distance between electrodes: 50mm
-Substrate temperature: room temperature The composition of the formed Cu alloy film was confirmed by quantitative analysis using an ICP emission spectrometer (ICP emission spectrometer "ICP-8000 type" manufactured by Shimadzu Corporation).

(Evaluation of adhesion with SiN film)
A grid-like cut was made at 1 mm intervals on the film formation surface (the surface of the pure Cu film, the pure Mo film, or the above Cu alloy film) of the sample prepared in this manner using a cutter knife. Next, Scotch (registered trademark) mending tape is firmly attached onto the sample, and the tape is peeled off at once while being held at a tape peel angle of 60 °, and peeled off by the tape. The number of sections of the grid that were not performed was counted, and the ratio (film residual ratio) with respect to all sections was determined. The result is shown in the column “as-deposited” in Table 1. In addition, each sample was subjected to 150 ° C. × 30 min. In a vacuum atmosphere. The film remaining rate was also measured for those subjected to the heat treatment. The results are also shown in Table 1.

  From Table 1, it can be considered as follows. The film remaining rate of the pure Cu film is zero and does not show adhesion with the SiN film, whereas the film remaining rate of the pure Mo film is 100% and shows good adhesion with the SiN film. However, pure Mo has a demerit that the electrical resistivity at room temperature is considerably higher than that of pure Cu.

  Further, among the Cu alloy films, except for the Cu—Ge containing alloy film, the film remaining rate is almost zero or less than 50%, whereas the film remaining rate of the Cu-0.5 at% Ge alloy film is 100%. It can be seen that good adhesion to the SiN film is exhibited.

[Example 2]
The influence of the Ge content in the Cu alloy film and the heat treatment conditions on the adhesion with the SiN film (the film remaining rate) was examined.

(Sample preparation)
A SiN film having a thickness of 200 nm was formed by CVD on a glass substrate (Corning Eagle 2000) as in Example 1 above, and a pure Cu film or a Cu having a different Ge content was formed on the SiN film by DC magnetron sputtering. An alloy film was formed to 300 nm to prepare a sample. Note that pure Cu is used as a sputtering target for forming a pure Cu film, and Cu-Ge binary alloy targets having various compositions prepared by a vacuum melting method are used for forming Cu alloy films having different Ge contents. Used as a sputtering target.

(Evaluation of adhesion with SiN film)
(A) Sample prepared as described above (as-deposited sample),
(B) 150 ° C. × 30 min. In a vacuum atmosphere. Samples subjected to heat treatment of
(C) 350 ° C. × 30 min. In a vacuum atmosphere. Samples subjected to heat treatment of
Was prepared and the adhesion with the SiN film (the film remaining rate) was evaluated in the same manner as in Example 1.

  The results of measuring the film residual ratio of various Cu alloy films with different Ge contents and heat treatment conditions are summarized in FIG. FIG. 10 shows the relationship between the Ge content in the Cu alloy film and the remaining film, (a) as-deposited state, (b) after heat treatment at 150 ° C., and (c) after heat treatment at 350 ° C. Is shown.

  From FIG. 10, although the film remaining rate of the pure Cu film is zero, the film remaining rate rapidly increases by containing Ge at 0.1 at%, and shows good adhesion to the SiN film. Recognize. When the Ge content is further increased, the adhesion (film residual ratio) is improved, the film residual ratio is 90% or more when the Ge content is 0.1 at% or more, and the film is obtained when the Ge content is 0.5 at% or more. The remaining rate is 100%. It can be seen that such a tendency appears regardless of the presence or absence of heat treatment and the heat treatment conditions.

[Example 3]
Using a pure Cu film and various Cu alloy films having different Ge contents, the electrical resistivity was measured and evaluated as shown below.

(Sample preparation)
A pure Cu film or a Cu alloy film having a different Ge content was formed in a thickness of 300 nm on a glass substrate (Eagle 2000 manufactured by Corning) in the same manner as in Example 1 by DC magnetron sputtering. For the formation of the Cu alloy films having different Ge contents, Cu—Ge binary alloy targets having various compositions prepared by a vacuum melting method were used as sputtering targets.

(Measurement of electrical resistivity)
The pure Cu film or Cu alloy film having various Ge contents formed above is subjected to photolithography and wet etching to be processed into a stripe pattern (electric resistivity measurement pattern) having a width of 100 μm and a length of 10 mm. Thus, the electrical resistivity of the pattern was measured at room temperature by a direct current four-probe method using a prober.

The electrical resistivity was measured at 400 ° C. in a vacuum (≦ 1 × 10 ⁻⁶ Torr) by simulating the stripe pattern in the as-deposited state and the heat treatment after the Cu alloy film was formed. The striped pattern was subjected to a heat treatment for 5 minutes on the Cu alloy film.

  The results of measuring the electrical resistivity of various Cu alloy films with different Ge contents are summarized in FIG. FIG. 11 shows the relationship between the Ge content in the Cu alloy film and the electrical resistivity for the as-deposited state and after the 400 ° C. vacuum heat treatment.

  From FIG. 11, the electrical resistivity of the Cu alloy film increases almost linearly as the Ge content increases in the as-deposited state. The absolute value of the electrical resistivity of the sample subjected to the heat treatment is slightly lower than that of the sample in the as-deposited state. However, the electrical resistivity of the sample subjected to the heat treatment also increases the Ge content. It can be seen that there is a tendency to increase linearly. It can also be seen that when the Ge content in the Cu alloy is 0.5 at% or less, a low electrical resistivity of 5 μΩcm or less can be achieved.

FIG. 1 is an enlarged schematic cross-sectional explanatory view showing a configuration of a typical liquid crystal display to which an amorphous silicon TFT substrate is applied. FIG. 2 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the embodiment of the present invention, and is an enlarged view of a main part A in FIG. FIG. 3 is an explanatory view showing an example of a manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 4 is an explanatory view showing an example of a manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 5 is an explanatory diagram showing an example of a manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 6 is an explanatory view showing an example of the manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 7 is an explanatory diagram showing an example of a manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 8 is an explanatory view showing an example of a manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 9 is an explanatory diagram showing an example of a manufacturing process of the TFT substrate shown in FIG. 2 in order. FIG. 10 is a diagram showing the relationship between the Ge content in the Cu alloy film and the film remaining rate after the heat treatment at 150 ° C. and after the heat treatment at 350 ° C. in an as-deposited state. FIG. 11 shows the relationship between the Ge content in the Cu alloy film and the electrical resistivity for the as-deposited state and after the 400 ° C. vacuum heat treatment.

Explanation of symbols

1 TFT substrate 1a Glass substrate 2 Counter substrate (counter electrode)
3 Liquid crystal layer 4 Thin film transistor (TFT)
5 Pixel electrode (transparent electrode film)
6 Wiring part 7 Common electrode 8 Color filter 9 Light shielding film 10a, 10b Polarizing plate 11 Alignment film 12 TAB tape 13 Driver circuit 14 Control circuit 15 Spacer 16 Sealing material 17 Protective film 18 Diffusion plate 19 Prism sheet 20 Light guide plate 21 Reflecting plate 22 Backlight 23 Holding frame 24 Printed circuit board 25 Scan line (gate wiring)
26 Gate electrode 27 Gate insulating film 28 Source electrode 29 Drain electrode 30 Passivation film (protective film, SiN)
31 Photoresist layer 32 Contact hole 34 Signal line (source-drain wiring)
100 LCD display

Claims (5)

Source electrode and / or drain electrode and signal line of thin film transistor in display device, and / or
A Cu alloy film used for a gate electrode and a scanning line,
The Cu alloy film contains 0.1 to 0.5 atomic percent of Ge and is 150 ° C. × 30 min. Both before and after heat treatment are excellent in adhesion with an insulating film made of silicon nitride , and
The Cu alloy film of Cu alloy film for a display device comprising der Rukoto those used without a base film between the silicon nitride film.   The display device according to claim 1, further comprising one or more selected from the group consisting of Ni, Pt, Au, Ce, Ru, W, Cr, Ir, Mo, Fe, Al, and Zr. Cu alloy film. The Cu alloy film for a display device according to claim 1 or 2, wherein the source electrode and / or drain electrode of the thin film transistor and the signal line, and / or
A display device which is used for a gate electrode and a scanning line.   The display device according to claim 3, wherein the thin film transistor has a bottom-gate structure, and a part of the source electrode and / or drain electrode is formed on an insulating film.   It is a sputtering target used for formation of Cu alloy film of Claim 1, Comprising: It consists of Cu alloy containing 0.1-0.5 atomic% of Ge, Cu alloy sputtering target characterized by the above-mentioned.