JP4904625B2

JP4904625B2 - Semiconductor device

Info

Publication number: JP4904625B2
Application number: JP2001036353A
Authority: JP
Inventors: 博樹脇本; 功吉川; 勝典上野
Original assignee: Fuji Electric Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2001-02-14
Filing date: 2001-02-14
Publication date: 2012-03-28
Anticipated expiration: 2021-02-14
Also published as: JP2002246597A

Description

【０００１】
【発明の属する技術分野】
この発明は、電力変換装置などに用いられる絶縁ゲート型バイポーラトランジスタ（以下、ＩＧＢＴと称す。ＩＧＢＴ：ＩｎｓｕｌａｔｅｄＧａｔｅＢｉｐｏｌａｒＴｒａｎｓｉｓｉｔｏｒ）などの半導体装置に関する。
【０００２】
【従来の技術】
近年、６００〜１２００Ｖ耐圧のＩＧＢＴなどのＭＯＳ制御型の電力用半導体デバイスでは、動作時のエネルギー損失の低減と、ウェハコストの削減のために、エピタキシャル基板よりも安価なＦＺ（ＦｌｏｔｉｎｇＺｏｎｅ）基板を用いて、そのＦＺ基板の厚さを１５０μｍ以下と極めて薄く加工し、デバイスを作り込む技術が脚光を浴びている。特に、耐圧が１２００ＶクラスのＩＧＢＴでは、オン電圧や順阻止耐圧などで、良好な電気的特性が得られるフィールドストップ（ＦｉｅｌｄＳｔｏｐ）型ＩＧＢＴ（以下、ＦＳ−ＩＧＢＴと称す）と呼ばれるＩＧＢＴが注目されている。
【０００３】
図７は、従来のＦＳ−ＩＧＢＴであり、同図（ａ）は要部断面図、同図（ｂ）は同図（ａ）のＹ−Ｙ線上での不純物濃度分布図である。
同図（ａ）において、ｎ^-半導体基板２００の第１主面側の表面層にｐベース領域５２を形成し、ｐベース領域５２の表面層にｎ⁺エミッタ領域５３を形成し、ｎ^-半導体基板２００とｎ⁺エミッタ領域５３に挟まれたｐベース領域５２上にゲート絶縁膜５４を介してゲート電極５５を形成し、その上に層間絶縁膜５６を形成し、ｎ⁺エミッタ領域５３上とｐベース領域５２上にエミッタ電極６０を形成する。その上に図示しないパッシベーション膜を被覆する。
【０００４】
一方、ｎ^-半導体基板２００の第２主面側の表面層にｎ型ＦＳ領域５９を形成し、このｎ型ＦＳ領域５９の表面層にｐ⁺コレクタ領域５７を形成し、ｐ⁺コレクタ領域５７上にコレクタ電極６１を形成する。ｎ^-半導体基板２００の各領域が形成されない領域が、ｎ^-ベース領域５１となる。
この従来のＦＳ−ＩＧＢＴでは、前記したように、エミッタ電極６０が形成される前に、コレクタ側のウエハ表面に、リンイオンなどのｎ型不純物とボロンイオンなどのｐ型不純物をイオン注入により打ち込み、４００℃程度の低温で熱処理して電気的に活性化して、ｎ型ＦＳ領域５９とｐ⁺コレクタ領域５７を形成する。以下に説明するこれらの領域の不純物濃度は、活性化した不純物濃度のことである。
【０００５】
この従来のＦＳ−ＩＧＢＴは、エピタキシャル基板を用いて形成した従来のパンチスルー型ＩＧＢＴ（ＰＴ−ＩＧＢＴ）の数百μｍの厚いコレクタ領域を１μｍ以下と極めて薄くした構造であり、従って、全体の半導体基板２００の厚さも１５０μｍ以下と極めて薄くなっている。
同図（ｂ）において、空乏層の伸びを抑えるフィールドストップ領域となるｎ型ＦＳ領域５９を形成する。このｎ型ＦＳ領域５９は、従来のエピタキシャル基板を用いたパンチスルー型ＩＧＢＴ（以下、ＰＴ−ＩＧＢＴという）のｎバッファ領域よりも不純物濃度が低いことが特徴である。その理由をつぎに説明する。
【０００６】
図８は、従来のエピタキシャル基板を用いたパンチスルー型ＩＧＢＴ（ＰＴ−ＩＧＢＴ）であり、同図（ａ）は要部断面図、同図（ｂ）はＹ−Ｙ線上での不純物濃度分布図である。
図８に示すように、従来のエピタキシャル基板３００を用いたＰＴ−ＩＧＢＴでは、数百μｍと厚い高濃度のｐ⁺コレクタ領域７７となるｐ⁺半導体基材上に、比較的高濃度の空乏層をストップさせるｎバッファ領域７９をエピタキシャル成長で形成する。このｎバッファ領域７９上に低濃度のｎ^-半導体領域８０を形成し、このｎ^-半導体領域８０の表面層にｐベース領域５２やｎ⁺エミッタ領域５３などを形成する。このｎ^-半導体領域８０のｐベース領域５２を形成しない領域がｎ^-ベース領域７１となる。
【０００７】
このｎバッファ領域７９の不純物濃度を比較的高い値にするのは、不純物濃度が極めて高いｐ⁺コレクタ領域７７からの正孔の注入を抑え、空乏層の伸びを完全に止めるためである。
また、ｐ⁺コレクタ領域７７の不純物濃度を極めて高い値にするのは、ｐ⁺コレクタ領域７７の厚さが数百μｍと厚いために、小さなオン電圧（ＶCE(sat))を得るためには、このｐ⁺コレクタ領域７７の抵抗を極めて小さな値にしなければならないからである。
【０００８】
一方、従来のＦＳ−ＩＧＢＴでは、順阻止状態では空乏層の伸びを、ｐ⁺コレクタ領域５７に接して形成されるｎ型ＦＳ領域５９で、ストップするために、ＰＴ−ＩＧＢＴと同様にｎ^-ベース領域５１の厚さを薄くできる。また、前記したように、ｐ⁺コレクタ領域５７の厚さをＰＴ−ＩＧＢＴより大幅に薄くできるために、ｐ⁺コレクタ領域５７の不純物濃度を、ＰＴ−ＩＧＢＴに比べて低くできる。このｐ⁺コレクタ領域５７の不純物濃度を低くすることで、オン状態でｐ⁺コレクタ領域５７からのｎ^-ベース領域５１に蓄積されるキャリア量を、ＰＴ−ＩＧＢＴと比べて小さくできる。
【０００９】
ｎ^-ベース領域５１に蓄積されるキャリア量を少なくすることで、ライフタイムキラーの導入なしでターンオフ時間を短縮できる。また、ライフタイムキラーの導入がないことで、オン電圧を小さくできる。
また、ｐ⁺コレクタ領域５７からの正孔の注入効率を所定の値にするために、ｎ型ＦＳ領域５９の不純物濃度をｐ⁺コレクタ領域５７の不純物濃度より小さくする必要がある。その結果、ｎ型ＦＳ領域５９の不純物濃度は、ＰＴ−ＩＧＢＴのｎバッファ領域７９の不純物濃度に比べて低い値となる。このことがＦＳ−ＩＧＢＴの特徴である。
【００１０】
【発明が解決しようとする課題】
しかし、この従来のＦＳ−ＩＧＢＴのｐ⁺コレクタ領域５７は、前記したように、ＰＴ−ＩＧＢＴのｐ⁺コレクタ領域７７と比べて不純物濃度が低く、厚さが大幅に薄く、また、ｎバッファ領域７９に相当するｎ型ＦＳ領域５９の不純物濃度も低いために、ｐ⁺コレクタ領域５７やｎ型ＦＳ領域５９に部分的な欠損（欠落箇所）が生じ易い。
【００１１】
イオン注入前に、コレクタ側のウエハの表面に付着したごみ・ほこりなどによりｎ型ＦＳ領域５９の一部分でも形成されない箇所（欠損箇所）があると、ｐベース領域５２側からから伸びてきた空乏層が容易にｐ⁺コレクタ領域５７にパンチスルーして、ＩＧＢＴの耐圧が劣化する。
また、ｐ⁺コレクタ領域５７が形成されない箇所があると、ｎ型ＦＳ領域５９の不純物濃度が通常のｐｎダイオードのｎ領域と比べて大幅に高くなっているために、ｐ⁺コレクタ領域５７とｎ型ＦＳ領域５９からなるｐ／ｎ接合が順バイアスされ難くなり、その結果、ｐ⁺コレクタ領域５７からｎ型ＦＳ領域５９への正孔の注入が起こり難くなり、オン電圧が上昇する。
【００１２】
この発明の目的は、前記の課題を解決して、ｐ⁺コレクタ領域とｎ型ＦＳ領域の部分的な欠損が、オン電圧特性や耐圧特性に及ぼす影響を小さくできる半導体装置を提供することにある。
【００１３】
【課題を解決するための手段】
前記の目的を達成するために、第１導電型半導体基板の第１主面の表面層に、選択的に形成された第２導電型ベース領域と、該第２導電型ベース領域の表面層に選択的に形成された第１導電型エミッタ領域と、該第１導電型エミッタ領域と前記第１導電型半導体基板に挟まれた前記第２導電型ベース領域上にゲート絶縁膜を介して形成されたゲート電極と、前記第１導電型エミッタ領域上と前記第２導電型ベース領域上に形成されたエミッタ電極と、前記第１導電型半導体基板を１５０μｍ以下に薄くした第２主面の表面層に形成された厚さが１μｍ以下の第２導電型コレクタ領域と、該第２導電型コレクタ領域上に形成されたコレクタ電極とを具備する半導体装置であって、
前記第２導電型コレクタ領域と離して前記第１導電型半導体基板の不純物濃度より高い不純物濃度で、第１導電型半導体基板内に形成された第１導電型フィールドストップ領域とを有し、該第１導電型フィールドストップ領域と前記第２導電型コレクタ領域との間が前記第１導電型半導体基板の不純物濃度の領域で分離されている構成とする。
【００１４】
また、第１導電型半導体基板の第１主面の表面層に、選択的に形成された第２導電型ベース領域と、該第２導電型ベース領域の表面層に選択的に形成された第１導電型エミッタ領域と、該第１導電型エミッタ領域と前記第１導電型半導体基板に挟まれた前記第２導電型ベース領域上にゲート絶縁膜を介して形成されたゲート電極と、前記第１導電型エミッタ領域上と前記第２導電型ベース領域上に形成されたエミッタ電極と、前記第１導電型半導体基板を１５０μｍ以下に薄くした第２主面の表面層に形成された厚さが１μｍ以下の第２導電型コレクタ領域と、該第２導電型コレクタ領域上に形成されたコレクタ電極とを具備する半導体装置であって、
前記第２導電型コレクタ領域と離して前記第１導電型半導体基板の不純物濃度より高い不純物濃度で、第１導電型半導体基板内に形成された第１導電型フィールドストップ領域とを有し、該第１導電型フィールドストップ領域の不純物ピーク濃度が１０^１５〜１０^１７ｃｍ^−３であり、該第１導電型フィールドストップ領域と前記第２導電型コレクタ領域との間が前記第１導電型半導体基板の不純物濃度より1桁以内の不純物濃度高さの領域で分離されている構成とする。
【００１５】
また、前記第１導電型フィールドストップ領域が離れて複数個形成されるとよい。
また、前記第２導電型コレクタ領域の表面から前記第１導電型半導体基板内に到達するように形成された複数個の溝と、該溝内を充填する絶縁膜と、該溝の各先端部に個別に形成された前記第１導電型フィールドストップ領域とを有するとよい。
【００１６】
【００１７】
また、前記第１導電型フィールドストップ領域の前記第２主面に投影した平面形状が、格子状であるとよい。
また、前記第１導電型フィールドストップ領域の前記第２主面に投影した平面形状が、セル状もしくはストライプ状であるとよい。
【００１８】
【発明の実施の形態】
図１は、この発明の第１実施例の半導体装置であり、同図（ａ）は要部断面図、同図（ｂ）は同図（ａ）のＹ−Ｙ線上での不純物濃度分布（拡散プロフィル）図である。従来のＦＳ−ＩＧＢＴとの違いは、ｐ⁺コレクタ領域７とｎ型ＦＳ領域９が接していない点である。また、以下の実施例では、ゲート部分がトレンチ構造であっても同様の効果がある。
【００１９】
同図（ａ）において、ｎ^-半導体基板１００の第１主面側の表面層にｐベース領域２を形成し、このｐベース領域２の表面層にｎ⁺エミッタ領域３を形成する。ｎ^-半導体基板１００（ｎ^-ベース領域１）とｎ⁺エミッタ領域３に挟まれたｐベース領域２上にゲート絶縁膜４を介してゲート電極５を形成し、その上に層間絶縁膜６を形成し、層間絶縁膜にコンタクトホールを開けて、前記のｎ⁺エミッタ領域３上とｐベース領域２上にエミッタ電極１０を形成する。その後、表面に図示しないパッシベーション膜を被覆する。
【００２０】
一方、ｎ^-半導体基板１００の第２主面から所定の深さに、空乏層の伸びを抑える働きがあるｎ型ＦＳ領域９を形成し、このｎ型ＦＳ領域９より低い不純物濃度で、ｎ型ＦＳ領域９と第２主面の間にｎ領域８を形成し、このｎ領域８の表面層に、ｎ型ＦＳ領域９と離してｐ⁺コレクタ領域７を形成し、ｐ⁺コレクタ領域７上にコレクタ電極１１を形成する。ｎ^-半導体基板１００の各領域が形成されない領域がｎ^-ベース領域１となる。
【００２１】
前記のｎ型ＦＳ領域９とｐ⁺コレクタ領域７およびｎ領域８は、リンイオンなどのｎ型不純物およびボロンイオンなどのｐ型不純物をイオン注入し、４００℃程度の低温で熱処理してイオン注入された不純物を活性化する。以下の説明で、これらの領域の不純物濃度は、熱処理した後の活性化した不純物濃度のことである。
【００２２】
尚、図１（ａ）のｎ型ＦＳ領域９のｐ⁺コレクタ領域表面１２に投影した平面形状は、全面がｎ型ＦＳ領域９であるが、図６（ａ）に示すような格子状をしていてもよい。
同図（ｂ）において、ｎ型ＦＳ領域９がｐ⁺コレクタ領域７に接しないようにするためには、ｎ型ＦＳ領域９の不純物濃度ピーク位置１５（不純物濃度がピークとなる位置のこと）からｎ^-ベース領域と同等の不純物濃度になる位置まで（ｎ^-ベース領域１とｎ型ＦＳ領域９とのｐｎ接合の位置）の距離ａよりも、ｎ型ＦＳ領域の不純物濃度ピーク位置１５からｐ⁺コレクタ領域７とｎ領域８とのｐ／ｎ接合（以下、コレクタｐ／ｎ接合１３と称す）までの距離ｂを大きくする。つまり距離ｂ＜距離ａとする。
【００２３】
通常の工程では、ｐ⁺コレクタ領域表面１２からコレクタｐ／ｎ接合１３までの距離（ｐ⁺コレクタ領域の厚さ）は０．２〜０．３μｍ、ｐ⁺コレクタ領域表面１２からｎ型ＦＳ領域９の不純物濃度ピーク位置１５は０．８〜１μｍ程度である。コレクタｐ／ｎ接合１３とｎ型ＦＳ領域９が接する場合には、ｎ型ＦＳ領域の半分の厚み（距離ａに相当する）は、０．５〜０．８μｍとなる。従って、距離ｂが０．８μｍより大きい値（ｂ＞０．８μｍ）であれば、ｐ⁺コレクタ領域１３とｎ型ＦＳ領域９とは接することはない。
【００２４】
ｎ型ＦＳ領域９がｐベース領域２に近すぎると、ｎ型ＦＳ領域９内が空乏化してしまう可能性があるため、ｐベース領域２のボトム（ｐベース領域２とｎ^-ベース領域１のｐ／ｎ接合（以下、ベースｐ／ｎ接合１４と称す））からｎ型ＦＳ領域９の不純物濃度ピーク位置１５までの距離ｃに対して、距離ｂを２０％程度以下にすることが必要がある。
【００２５】
また、前記のｎ型ＦＳ領域９の不純物ピーク濃度が高すぎると、オン電圧の上昇を招くので、ｐ⁺コレクタ領域７の不純物ピーク濃度よりｎ型ＦＳ領域９の不純物ピーク濃度を２桁程度以上小さくなるように、設定するのが好ましい。しかし、このｎ型ＦＳ領域９の不純物ピーク濃度の高さ（図中、番号１５の位置での濃度の高さ）は、ｎ型ＦＳ領域９が完全に空乏化しない程度にすることが望ましい。
【００２６】
また、前記のｐ⁺コレクタ領域７を形成するために、イオン注入した不純物原子は、４００℃程度以下の低温で熱処理（アニール）し、活性化させるが、通常、この活性化した不純物ピーク濃度を１０¹⁷ｃｍ^-3〜１０¹⁹ｃｍ^-3程度にすることができる。従って、ｎ型ＦＳ領域９の不純物ピーク濃度は１０¹⁵〜１０¹⁷ｃｍ^-3程度とすることが好ましい。
【００２７】
また、ｐ⁺コレクタ領域７とｎ型ＦＳ領域９のそれぞれに接して、これらの領域の間に形成されるｎ領域８の不純物ピーク濃度は、ｎ^-半導体基板１００（ｎ^-ベース領域１）の不純物濃度より多少高く（１桁以内の高さ）、ｎ型ＦＳ領域９の不純物ピーク濃度より低く設定する。
このｎ領域８は、空乏層がｎ型ＦＳ領域９を突き抜けた場合やｎ型ＦＳ領域９に部分的な欠損があった場合に、ｐ⁺コレクタ領域７に空乏層が到達しないようにする働きと、ｐ⁺コレクタ領域７からの正孔の注入を抑制する働きがある。従って、ｎ型ＦＳ領域９により、空乏層がｐ⁺コレクタ領域７に達せず、且つ、ｐ⁺コレクタ領域７からの正孔の注入を抑制する必要がなければ、このｎ領域８は形成しなくても構わない。また、図１では、ｎ領域８がｎ型ＦＳ領域９に接しているが、接しなくても構わない。
【００２８】
前記のｐ⁺コレクタ領域７と離してｎ型ＦＳ領域９を形成するには、ｎ型不純物を高エネルギーで加速して、深くイオン注入し、低温の熱処理で活性化させる方法と、エピタキシャル成長による方法がある。イオン注入法では１μｍ程度の深さ程度であるが、エピタキシャル成長による方法では、ｐ⁺コレクタ領域表面１２から任意の深さに、ｎ型ＦＳ領域９を形成することができる。しかし、ｎ型ＦＳ領域９を深くし過ぎると、前記のように、ｎ^-ベース領域１の幅が狭くなる。その結果、前記のように、ｎ型ＦＳ領域内が空乏化してしまう可能性が生じるため、ｐ⁺コレクタ領域表面からの深さを１０μｍ程度以下にすることが望ましい。
【００２９】
本発明のＦＳ−ＩＧＢＴでは、ｐ⁺コレクタ領域７と離してｎ型ＦＳ領域９を形成し、これらに挟まれた箇所に低濃度のｎ領域８を形成することで、順阻止状態においては、従来のＦＳ−ＩＧＢＴと同様に、空乏層をｎ型ＦＳ領域９でストップさせて、耐圧を確保し、一方、オン状態では、ｐ⁺コレクタ領域７に低濃度のｎ領域８が接しているために、この箇所はノンパンチスルー型ＩＧＢＴ（ＮＰＴ−ＩＧＢＴ）のコレクタ側と類似しており、ｐ⁺コレクタ領域７からの正孔の注入効率が低下せず、オン電圧を小さくできる。
【００３０】
また、この構造では、ｐ⁺コレクタ領域７の部分的な欠損が、オン電圧に与える影響を小さくできる。それは、ｐ⁺コレクタ領域７と接するｎ領域８の不純物濃度が低いために、部分的にｐ⁺コレクタ領域７が欠損しても、容易にｐ⁺コレクタ領域７とｎ領域８のｐ／ｎ接合が順バイアスされて、ｐ⁺コレクタ領域７からｎ領域８へ正孔が注入されるためである。
【００３１】
図２は、この発明の第２実施例の半導体装置の要部断面図である。図１との違いはｎ型ＦＳ領域９ａが複数個に分割されている点である。
ｐ⁺コレクタ領域７と離して、部分的にｎ^-半導体基板１００の不純物濃度よりも大きい不純物濃度ピークを持つｎ型ＦＳ領域９ａが複数個、離して、ｎ^-ベース領域１に埋め込まれるように形成され、このｎ型ＦＳ領域９ａとｐ⁺コレクタ領域７の間に、ｎ型ＦＳ領域と離して、ｎ型ＦＳ領域９ａの不純物濃度より低いｎ領域８を形成する。この埋め込まれたｎ型ＦＳ領域９ａとｎ型領域８は、空乏層の伸びを抑える働きをして、ｎ型ＦＳ領域９ａのない領域でのｐ⁺コレクタ領域７へ、空乏層が達する電圧（パンチスルー電圧）を高めることができる。また、前記したように、コレクタｐ／ｎ接合１３からｎ型ＦＳ領域９ａの不純物濃度ピーク位置１５までの距離ｂは０．８μｍ以上であることが望ましい。
【００３２】
また、ベースｐ／ｎ接合１４からｎ型ＦＳ領域９ａの不純物濃度ピーク位置１５までの距離ｃに対して、ｎ型ＦＳ領域９ａの不純物濃度ピーク位置１５からコレクタｐ／ｎ接合１３までの距離ｂが、２０％程度以下で、十分空乏層の伸びを抑制する効果がある。
また、ｎ型ＦＳ領域９ａのｐ⁺コレクタ領域表面１２に垂直投影した平面形状（以下、単に平面形状という）は、図６（ｂ）に示すように、セル状（円形、楕円形、多角形など）、図６（ｃ）に示すように、ストライプ状のいずれでもよい。また、セル状のｎ型ＦＳ領域９ａの立体的な形状が、たとえば、球形や、ウェハ面に平行な方向に長く垂直な方向に短い楕円形およびウェハ面に垂直な方向に長く平行な方向に短い楕円形のいずれかの場合には、図６（ｄ）に示すような、ｎ型ＦＳ領域９ａがウェハ面に垂直な方向に長い楕円形のものが空乏層の伸びを抑える効果が高く、またチップの総面積（チップ面の総面積）に対するｎ型ＦＳ領域９ａの面積割合が小さいのでオン電圧の上昇も小さい。尚、図６（ｄ）の垂直の方向と水平の方向は、図２の垂直の方向と水平の方向のことである。
【００３３】
また、ｎ型ＦＳ領域９ａの面積割合が小さい場合には、オン電圧の上昇の割合が小さくなるため、ｎ型ＦＳ領域９ａの不純物ピーク濃度を高くして順阻止耐圧を向上させることができる。
また、この構造では、前記したように、ｎ領域８が低濃度であるため、コレクタ側の構造は、ＮＰＴ−ＩＧＢＴに近い構造となり、従来のＦＳ−ＩＧＢＴより、ｐ⁺コレクタ領域の一部分が欠損しても、オン電圧に及ぼす影響は小さい。尚、前記したように、ｎ型ＦＳ領域９ａにより、空乏層がｐ⁺コレクタ領域７に達せず、且つ、ｐ⁺コレクタ領域７からの正孔の注入を抑制する必要がなければ、このｎ領域８は形成しなくても構わない。
【００３４】
図３は、この発明の第３実施例の半導体装置の要部断面図である。コレクタ側からｎ^-半導体基板１００に形成された複数個の溝１６に絶縁材１７が埋め込まれ、その先端にｎ型ＦＳ領域９ｂが形成されている。ｎ型ＦＳ領域９ｂの不純物濃度は順阻止状態で空乏化しない程度の濃度とすることが望ましい。前記したように、コレクタｐ／ｎ接合１３からｎ型ＦＳ領域９ｂのもっともｐベース領域２側に近い不純物濃度ピーク位置１５までの距離ｂが０．８μｍ程度以上であることが望ましい。
【００３５】
また、前記したように、空乏層の伸びを抑るためには、ベースｐ／ｎ接合１４からｎ型ＦＳ層９ｂの不純物濃度ピーク位置１５までの距離ｃに対して、ｎ型ＦＳ層９ｂの不純物ピーク位置１５からコレクタｐ／ｎ接合１３までの距離ｂが、２０％程度以下で十分である。また、前記したように、ｎ型ＦＳ領域９ｂの面積割合が十分小さい場合には、オン電圧が上昇する割合が小さいため、ｎ型ＦＳ領域９ｂの不純物濃度ピーク濃度を高くすることで、順阻止耐圧を向上させることができる。
【００３６】
この構造は、溝１６を形成した後、イオン注入、または、ｎ型不純物を含有した材料を埋め込み、拡散によってｎ型ＦＳ領域９ｂとｎ領域８を形成し、最後に溝１６を絶縁材１７で埋めることにより形成できる。ｎ型ＦＳ領域９ｂの平面形状は、セル状、ストライプ状のいずれでも良い。また、ｎ領域８の働きは前記した通りであり、空乏層の伸びがｎ型ＦＳ領域９ｂによりｐ⁺コレクタ領域７に達せず、また、ｐ⁺コレクタ領域７からの正孔の注入を抑制する必要がなければ、形成しなくても構わない。
【００３７】
図４は、この発明の第１参考例の半導体装置の要部断面図である。図１から図３までとの違いは、複数個形成されたｎ型ＦＳ領域９ｃがｐ⁺コレクタ領域７に接している点である。このｎ型ＦＳ領域９ｃの不純物濃度は、前記したように、順阻止状態で完全に空乏化しない程度の濃度とすることが望ましい。ｎ型ＦＳ領域９ｃの面積割合が十分小さい場合にはオン電圧が上昇する割合が小さいため、ｎ型ＦＳ領域９ｃの不純物ピーク濃度を、高くすることで、順阻止耐圧を向上させることができる。
【００３８】
また、ｎ型ＦＳ領域９ｃの平面形状は、セル状およびストライプ状のいずれでも良い。この構造においても、順阻止状態では、ｎ型ＦＳ領域９ｃにより、ｎ型ＦＳ領域９ｃがない箇所の空乏層の伸びが抑制され、空乏層がｐ⁺コレクタ領域７に到達し難くなり、耐圧が確保しやすい。この空乏層の伸びは、前記のｎ領域８を形成することで、さらに抑えられて、耐圧の確保が容易になる。しかし、空乏層の伸びがｎ型ＦＳ領域９ｃによりｐ⁺コレクタ領域７へ達せず、且つ、ｐ⁺コレクタ領域７からの正孔の注入を抑制する必要がないならば、このｎ領域８は形成しなくても構わない。
【００３９】
また、ｎ型ＦＳ領域９ｃがない箇所では、ｐ⁺コレクタ領域７からの正孔の注入効率が低下しないため、オン電圧を低く保つことができる。このｎ型ＦＳ領域９ｃがない箇所の断面構造は、ｎ領域８の不純物濃度が十分低いために、ＮＰＴ−ＩＧＢＴに近い構造となり、前記したように、従来のＦＳ−ＩＧＢＴほどには、ｐ⁺コレクタ領域７の一部分の欠損が、オン電圧の上昇を招かない。
【００４０】
図５は、この発明の第２参考例の半導体装置の要部断面図である。コレクタ側からｎ^-半導体基板１００に形成された溝１６に絶縁材１７が埋め込まれ、それを囲むようにｎ型ＦＳ領域９ｄが形成されている。またｐ⁺コレクタ領域７と接するように、ｎ型ＦＳ領域９ｄより不純物濃度が低いｎ領域８が形成されている。ｎ型ＦＳ領域９ｄの不純物濃度は、順阻止状態で空乏化しない程度の濃度が望ましい。
【００４１】
また、溝１６の深さを深くすることにより、ｎ型ＦＳ領域９ｄのｐ⁺コレクタ領域表面１２からの深さを深くすることが可能であるが、空乏層の伸びを効果的に抑えるためには、ベースｐ／ｎ接合１４からｎ型ＦＳ層９ｄの不純物濃度ピーク位置１５までの距離ｃに対して、先端箇所１８のｎ型ＦＳ層９ｄの不純物ピーク位置１５からコレクタｐ／ｎ接合１３までの距離ｂが、２０％程度以下で十分である。
【００４２】
前記したように、ｎ型ＦＳ領域９ｄの面積割合が十分小さい場合には、オン電圧が上昇する割合が小さいため、ｎ型ＦＳ領域９ｄの不純物濃度のピーク濃度を高くすることで、順阻止耐圧を向上させることができる。
また、ｎ型ＦＳ領域９ｄの平面形状は、セル状およびストライプ状のいずれでも良い。また、前記したように、ｎ領域８は、空乏層の伸びがｎ型ＦＳ領域９ｄによりｐ⁺コレクタ領域７に達せず、且つ、ｐ⁺コレクタ領域９ｄからの正孔の注入を抑制する必要がなければ、形成しなくても構わない。
【００４３】
【発明の効果】
この発明によれば、ｐ⁺コレクタ領域に、ｎ型ＦＳ領域を接しないように形成し、ｐ⁺コレクタ領域とｎ型ＦＳ領域の間に低濃度のｎ領域を形成することで、ｐ⁺コレクタ領域、ｎ型ＦＳ領域の部分的な欠損が、オン電圧および順阻止耐圧に及ぼす影響を小さくできる。
【００４４】
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置であり、（ａ）は要部断面図、（ｂ）は（ａ）のＹ−Ｙ線上での不純物濃度分布図
【図２】この発明の第２実施例の半導体装置の要部断面図
【図３】この発明の第３実施例の半導体装置の要部断面図
【図４】この発明の第１参考例の半導体装置の要部断面図
【図５】この発明の第２参考例の半導体装置の要部断面図
【図６】ｎ型ＦＳ領域の形状で、（ａ）は格子状の図、（ｂ）はセル状の図、（ｃ）はストライプ状の図、（ｄ）は楕円状の図
【図７】従来のＦＳ−ＩＧＢＴであり、（ａ）は要部断面図、（ｂ）は（ａ）のＹ−Ｙ線上での不純物濃度分布図
【図８】従来のエピタキシャル基板を用いたパンチスルー型ＩＧＢＴ（ＰＴ−ＩＧＢＴ）であり、（ａ）は要部断面図、（ｂ）はＹ−Ｙ線上での不純物濃度分布図
【符号の説明】
１ｎ^-ベース領域
２ｐベース領域
３ｎ⁺エミッタ領域
４ゲート絶縁膜
５ゲート電極
６層間絶縁膜
７ｐ⁺コレクタ領域
８ｎ領域
９、９ａ、９ｂ、９ｃ、９ｄｎ型ＦＳ領域
１０エミッタ電極
１１コレクタ電極
１２ｐ⁺コレクタ領域表面
１３コレクタｐ／ｎ接合
１４ベースｐ／ｎ接合
１５不純物濃度ピーク位置
１６溝
１７絶縁材
１８先端箇所
２１ｐ⁺コレクタ領域表面に投影した形状
１００ｎ^-半導体基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as IGBT; IGBT: Insulated Gate Bipolar Transistor) used in a power conversion device or the like.
[0002]
[Prior art]
In recent years, MOS-controlled power semiconductor devices such as IGBTs with a breakdown voltage of 600 to 1200 V have been manufactured using FZ (Floating Zone) substrates that are less expensive than epitaxial substrates in order to reduce energy loss during operation and reduce wafer costs. The technology of fabricating a device by using the FZ substrate as thin as 150 μm or less and making a device is in the spotlight. In particular, in a IGBT with a withstand voltage of 1200 V class, an IGBT called a field stop type IGBT (hereinafter referred to as FS-IGBT) that can obtain good electrical characteristics with an on-state voltage, a forward blocking withstand voltage, and the like has attracted attention. ing.
[0003]
7A and 7B show a conventional FS-IGBT. FIG. 7A is a cross-sectional view of the main part, and FIG. 7B is an impurity concentration distribution diagram on the YY line of FIG.
In FIG. 9A, n ^- A p base region 52 is formed in the surface layer on the first main surface side of the semiconductor substrate 200, and n is formed on the surface layer of the p base region 52. ⁺ An emitter region 53 is formed and n ^- Semiconductor substrate 200 and n ⁺ A gate electrode 55 is formed on the p base region 52 sandwiched between the emitter regions 53 via a gate insulating film 54, an interlayer insulating film 56 is formed thereon, and n ⁺ Emitter electrodes 60 are formed on the emitter region 53 and the p base region 52. A passivation film (not shown) is coated thereon.
[0004]
On the other hand, n ^- An n-type FS region 59 is formed in the surface layer on the second main surface side of the semiconductor substrate 200, and p-type is formed on the surface layer of the n-type FS region 59. ⁺ A collector region 57 is formed and p ⁺ A collector electrode 61 is formed on the collector region 57. n ^- A region where each region of the semiconductor substrate 200 is not formed is n ^- A base region 51 is formed.
In this conventional FS-IGBT, as described above, before the emitter electrode 60 is formed, n-type impurities such as phosphorus ions and p-type impurities such as boron ions are implanted into the wafer surface on the collector side by ion implantation. The n-type FS region 59 and p are electrically activated by heat treatment at a low temperature of about 400 ° C. ⁺ A collector region 57 is formed. The impurity concentration of these regions described below is the activated impurity concentration.
[0005]
This conventional FS-IGBT has a structure in which a thick collector region of several hundreds μm of a conventional punch-through type IGBT (PT-IGBT) formed using an epitaxial substrate is extremely thin as 1 μm or less. The thickness of the substrate 200 is also extremely thin at 150 μm or less.
In FIG. 2B, an n-type FS region 59 serving as a field stop region that suppresses the growth of the depletion layer is formed. The n-type FS region 59 is characterized by a lower impurity concentration than an n buffer region of a punch-through IGBT (hereinafter referred to as PT-IGBT) using a conventional epitaxial substrate. The reason will be described next.
[0006]
8A and 8B show a punch-through IGBT (PT-IGBT) using a conventional epitaxial substrate. FIG. 8A is a cross-sectional view of the main part, and FIG. 8B is an impurity concentration distribution diagram on the YY line. It is.
As shown in FIG. 8, in the PT-IGBT using the conventional epitaxial substrate 300, a high concentration p having a thickness as large as several hundred μm. ⁺ P to be the collector region 77 ⁺ On the semiconductor substrate, an n buffer region 79 for stopping a relatively high concentration depletion layer is formed by epitaxial growth. On this n buffer area 79, a low concentration n ^- A semiconductor region 80 is formed and this n ^- The p base region 52 and n are formed on the surface layer of the semiconductor region 80. ⁺ An emitter region 53 and the like are formed. This n ^- The p base region 52 of the semiconductor region 80 is formed. Shi No region is n ^- A base region 71 is formed.
[0007]
The reason why the impurity concentration of the n buffer region 79 is set to a relatively high value is that the impurity concentration is very high. ⁺ This is to suppress the injection of holes from the collector region 77 and completely stop the depletion layer from extending.
P ⁺ The reason why the impurity concentration in the collector region 77 is set to a very high value is p. ⁺ In order to obtain a small on-voltage (VCE (sat)) because the collector region 77 is as thick as several hundred μm, this p ⁺ This is because the resistance of the collector region 77 must be made extremely small.
[0008]
On the other hand, in the conventional FS-IGBT, in the forward blocking state, the extension of the depletion layer is reduced to p. ⁺ In order to stop at the n-type FS region 59 formed in contact with the collector region 57, n is the same as PT-IGBT. ^- The thickness of the base region 51 can be reduced. In addition, as described above, p ⁺ In order to make the thickness of the collector region 57 significantly thinner than the PT-IGBT, p ⁺ The impurity concentration of the collector region 57 can be made lower than that of PT-IGBT. This p ⁺ By reducing the impurity concentration of the collector region 57, p is turned on in the on state. ⁺ N from collector region 57 ^- The amount of carriers stored in the base region 51 can be made smaller than that of PT-IGBT.
[0009]
n ^- By reducing the amount of carriers accumulated in the base region 51, the turn-off time can be shortened without introducing a lifetime killer. In addition, the on-voltage can be reduced by not introducing a lifetime killer.
P ⁺ In order to set the hole injection efficiency from the collector region 57 to a predetermined value, the impurity concentration of the n-type FS region 59 is set to p. ⁺ It is necessary to make it smaller than the impurity concentration of the collector region 57. As a result, the impurity concentration of the n-type FS region 59 is lower than the impurity concentration of the n-buffer region 79 of PT-IGBT. This is a feature of FS-IGBT.
[0010]
[Problems to be solved by the invention]
However, this conventional FS-IGBT p ⁺ As described above, the collector region 57 is made of PT-IGBT p. ⁺ The impurity concentration is lower than that of the collector region 77, the thickness is significantly reduced, and the impurity concentration of the n-type FS region 59 corresponding to the n buffer region 79 is also low. ⁺ Partial defects (missing portions) are likely to occur in the collector region 57 and the n-type FS region 59.
[0011]
A depletion layer extending from the p base region 52 side if there is a portion (defect portion) that is not formed even in a part of the n-type FS region 59 due to dust or dust attached to the surface of the wafer on the collector side before ion implantation. Is easily p ⁺ Punching through the collector region 57 causes the breakdown voltage of the IGBT to deteriorate.
P ⁺ If there is a portion where the collector region 57 is not formed, the impurity concentration of the n-type FS region 59 is significantly higher than the n region of a normal pn diode. ⁺ The p / n junction composed of the collector region 57 and the n-type FS region 59 is less likely to be forward-biased. ⁺ Hole injection from the collector region 57 into the n-type FS region 59 hardly occurs, and the on-voltage increases.
[0012]
The object of the present invention is to solve the above problems and ⁺ An object of the present invention is to provide a semiconductor device that can reduce the influence of partial defects in a collector region and an n-type FS region on on-voltage characteristics and breakdown voltage characteristics.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a second conductive type base region selectively formed on a surface layer of the first main surface of the first conductive type semiconductor substrate, and a surface layer of the second conductive type base region. A first conductive type emitter region formed selectively, and a first conductive type emitter region and the second conductive type base region sandwiched between the first conductive type semiconductor substrate and a gate insulating film; A gate layer; an emitter electrode formed on the first conductivity type emitter region and the second conductivity type base region; and a surface layer of a second main surface in which the first conductivity type semiconductor substrate is thinned to 150 μm or less. Formed in The thickness is less than 1μm A semiconductor device comprising a second conductivity type collector region and a collector electrode formed on the second conductivity type collector region,
A first conductivity type field stop region formed in the first conductivity type semiconductor substrate at an impurity concentration higher than the impurity concentration of the first conductivity type semiconductor substrate apart from the second conductivity type collector region; The first conductivity type field stop region and the second conductivity type collector region are separated by an impurity concentration region of the first conductivity type semiconductor substrate.
[0014]
In addition, a second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate and a second layer selectively formed on the surface layer of the second conductivity type base region. A first conductivity type emitter region, a gate electrode formed on the second conductivity type base region sandwiched between the first conductivity type emitter region and the first conductivity type semiconductor substrate via a gate insulating film; Formed on the surface layer of the second main surface of the emitter electrode formed on the first conductivity type emitter region and the second conductivity type base region, and the first conductivity type semiconductor substrate thinned to 150 μm or less. The thickness is less than 1μm A semiconductor device comprising a second conductivity type collector region and a collector electrode formed on the second conductivity type collector region,
A first conductivity type field stop region formed in the first conductivity type semiconductor substrate at an impurity concentration higher than the impurity concentration of the first conductivity type semiconductor substrate apart from the second conductivity type collector region; The impurity peak concentration of the first conductivity type field stop region is 10 ¹⁵ -10 ¹⁷ cm ^-3 The first conductivity type field stop region and the second conductivity type collector region are separated by a region having an impurity concentration height within one digit from the impurity concentration of the first conductivity type semiconductor substrate. And
[0015]
A plurality of the first conductivity type field stop regions may be formed apart from each other.
A plurality of grooves formed so as to reach the first conductivity type semiconductor substrate from the surface of the second conductivity type collector region; an insulating film filling the grooves; and each tip portion of the grooves And the first conductivity type field stop region formed individually.
[0016]
[0017]
Also, The first conductivity type field stop region of The planar shape projected on the second main surface may be a lattice shape.
The planar shape projected onto the second main surface of the first conductivity type field stop region may be a cell shape or a stripe shape.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
1A and 1B show a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view of an essential part, and FIG. 1B is an impurity concentration distribution (Y-Y line in FIG. 1A). (Diffusion profile) FIG. The difference from the conventional FS-IGBT is p ⁺ The collector region 7 and the n-type FS region 9 are not in contact with each other. In the following embodiments, the same effect can be obtained even if the gate portion has a trench structure.
[0019]
In FIG. 9A, n ^- A p base region 2 is formed in the surface layer on the first main surface side of the semiconductor substrate 100, and ⁺ Emitter region 3 is formed. n ^- Semiconductor substrate 100 (n ^- Base regions 1) and n ⁺ A gate electrode 5 is formed on the p base region 2 sandwiched between the emitter regions 3 via a gate insulating film 4, an interlayer insulating film 6 is formed thereon, a contact hole is opened in the interlayer insulating film, and the above-mentioned n ⁺ Emitter electrodes 10 are formed on the emitter region 3 and the p base region 2. Thereafter, a passivation film (not shown) is coated on the surface.
[0020]
On the other hand, n ^- An n-type FS region 9 that functions to suppress the growth of the depletion layer is formed at a predetermined depth from the second main surface of the semiconductor substrate 100, and the n-type FS region 9 has an impurity concentration lower than that of the n-type FS region 9. N region 8 is formed between the first main surface and the second main surface, and the surface layer of n region 8 is separated from n-type FS region 9 by p ⁺ A collector region 7 is formed and p ⁺ A collector electrode 11 is formed on the collector region 7. n ^- A region where each region of the semiconductor substrate 100 is not formed is n ^- Base region 1 is formed.
[0021]
N-type FS region 9 and p ⁺ The collector region 7 and the n region 8 are ion-implanted with n-type impurities such as phosphorus ions and p-type impurities such as boron ions, and are heat-treated at a low temperature of about 400 ° C. to activate the implanted ions. In the following description, the impurity concentration in these regions refers to the activated impurity concentration after heat treatment.
[0022]
Note that p in the n-type FS region 9 in FIG. ⁺ The planar shape projected on the collector region surface 12 is the n-type FS region 9 as a whole, but it may have a lattice shape as shown in FIG.
In FIG. 5B, the n-type FS region 9 is p ⁺ In order to avoid contact with the collector region 7, the n-type FS region 9 has an impurity concentration peak position 15 (a position where the impurity concentration reaches a peak) to n. ^- Up to the position where the impurity concentration is equivalent to the base region (n ^- P from the impurity concentration peak position 15 of the n-type FS region than the distance a) of the pn junction between the base region 1 and the n-type FS region 9). ⁺ The distance b to the p / n junction (hereinafter referred to as the collector p / n junction 13) between the collector region 7 and the n region 8 is increased. That is, distance b <distance a.
[0023]
In normal process, p ⁺ Distance from collector region surface 12 to collector p / n junction 13 (p ⁺ (Thickness of collector region) is 0.2 to 0.3 μm, p ⁺ The impurity concentration peak position 15 from the collector region surface 12 to the n-type FS region 9 is about 0.8 to 1 μm. When the collector p / n junction 13 and the n-type FS region 9 are in contact with each other, the half thickness (corresponding to the distance a) of the n-type FS region is 0.5 to 0.8 μm. Therefore, if the distance b is greater than 0.8 μm (b> 0.8 μm), p ⁺ The collector region 13 and the n-type FS region 9 do not contact each other.
[0024]
If the n-type FS region 9 is too close to the p base region 2, there is a possibility that the n-type FS region 9 is depleted, so that the bottom of the p base region 2 (p base region 2 and n ^- The distance b is about 20% or less with respect to the distance c from the p / n junction of the base region 1 (hereinafter referred to as the base p / n junction 14) to the impurity concentration peak position 15 of the n-type FS region 9. It is necessary.
[0025]
On the other hand, if the impurity peak concentration of the n-type FS region 9 is too high, the on-voltage is increased. ⁺ It is preferable to set the impurity peak concentration of the n-type FS region 9 to be smaller than the impurity peak concentration of the collector region 7 by about two digits or more. However, it is desirable that the height of the impurity peak concentration of the n-type FS region 9 (the concentration at the position of number 15 in the figure) is such that the n-type FS region 9 is not completely depleted.
[0026]
In addition, the above p ⁺ In order to form the collector region 7, the ion-implanted impurity atoms are activated by annealing (annealing) at a low temperature of about 400 ° C. or lower. ¹⁷ cm ^-3 -10 ¹⁹ cm ^-3 Can be about. Therefore, the impurity peak concentration of the n-type FS region 9 is 10 ¹⁵ -10 ¹⁷ cm ^-3 It is preferable to set the degree.
[0027]
P ⁺ The impurity peak concentration of the n region 8 formed between and in contact with the collector region 7 and the n-type FS region 9 is n ^- Semiconductor substrate 100 (n ^- The impurity concentration of the base region 1) is set slightly higher (height within one digit) and lower than the impurity peak concentration of the n-type FS region 9.
The n region 8 is formed when the depletion layer penetrates the n-type FS region 9 or when the n-type FS region 9 has a partial defect. ⁺ The function of preventing the depletion layer from reaching the collector region 7 and p ⁺ It functions to suppress the injection of holes from the collector region 7. Therefore, the n-type FS region 9 makes the depletion layer p ⁺ The collector region 7 is not reached and p ⁺ If it is not necessary to suppress the injection of holes from the collector region 7, the n region 8 may not be formed. In FIG. 1, the n region 8 is in contact with the n-type FS region 9, but may not be in contact.
[0028]
P above ⁺ To form the n-type FS region 9 apart from the collector region 7, there are a method in which n-type impurities are accelerated with high energy, deep ion implantation is performed, and activation is performed by low-temperature heat treatment, and a method by epitaxial growth. In the ion implantation method, the depth is about 1 μm. ⁺ The n-type FS region 9 can be formed at an arbitrary depth from the collector region surface 12. However, if the n-type FS region 9 is made too deep, as described above, n ^- The width of the base region 1 is narrowed. As a result, the n-type FS region may be depleted as described above. ⁺ The depth from the collector region surface is desirably about 10 μm or less.
[0029]
In the FS-IGBT of the present invention, p ⁺ By forming an n-type FS region 9 apart from the collector region 7 and forming a low-concentration n region 8 between the regions, in the forward blocking state, as in the conventional FS-IGBT, depletion is performed. The layer is stopped at the n-type FS region 9 to ensure a breakdown voltage, while in the on state, p ⁺ Since the low-concentration n region 8 is in contact with the collector region 7, this portion is similar to the collector side of a non-punch through type IGBT (NPT-IGBT), and p ⁺ The efficiency of hole injection from the collector region 7 is not lowered, and the on-voltage can be reduced.
[0030]
In this structure, p ⁺ The influence of the partial defect of the collector region 7 on the on-voltage can be reduced. It is p ⁺ Since the impurity concentration of the n region 8 in contact with the collector region 7 is low, it is partially p ⁺ Even if the collector region 7 is missing, ⁺ The p / n junction of the collector region 7 and the n region 8 is forward biased and p ⁺ This is because holes are injected from the collector region 7 to the n region 8.
[0031]
FIG. 2 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The difference from FIG. 1 is that the n-type FS region 9a is divided into a plurality of parts.
p ⁺ Separated from the collector region 7, partially n ^- A plurality of n-type FS regions 9a having an impurity concentration peak larger than the impurity concentration of the semiconductor substrate 100 are separated, and n ^- The n-type FS region 9a and p are formed so as to be embedded in the base region 1. ⁺ An n region 8 lower than the impurity concentration of the n-type FS region 9a is formed between the collector regions 7 apart from the n-type FS region. The buried n-type FS region 9a and n-type region 8 serve to suppress the growth of the depletion layer, and the p in the region without the n-type FS region 9a. ⁺ The voltage (punch through voltage) that the depletion layer reaches the collector region 7 can be increased. As described above, the distance b from the collector p / n junction 13 to the impurity concentration peak position 15 of the n-type FS region 9a is preferably 0.8 μm or more.
[0032]
Further, a distance b from the impurity concentration peak position 15 of the n-type FS region 9a to the collector p / n junction 13 with respect to a distance c from the base p / n junction 14 to the impurity concentration peak position 15 of the n-type FS region 9a. However, at about 20% or less, there is an effect of sufficiently suppressing the elongation of the depletion layer.
Further, p of the n-type FS region 9a ⁺ A planar shape (hereinafter simply referred to as a planar shape) vertically projected onto the collector region surface 12 is a cell shape (circular, elliptical, polygonal, etc.), as shown in FIG. 6B, and shown in FIG. 6C. Thus, any of stripe shapes may be used. The three-dimensional shape of the cellular n-type FS region 9a is, for example, a sphere, an ellipse that is long in a direction perpendicular to the direction parallel to the wafer surface, and a direction that is long and parallel to a direction perpendicular to the wafer surface. In the case of any of the short ovals, an ellipse whose n-type FS region 9a is long in the direction perpendicular to the wafer surface as shown in FIG. 6 (d) has a high effect of suppressing the extension of the depletion layer. Further, since the area ratio of the n-type FS region 9a with respect to the total area of the chip (total area of the chip surface) is small, the rise of the on-voltage is small. Note that the vertical and horizontal directions in FIG. 6D are the vertical and horizontal directions in FIG.
[0033]
In addition, when the area ratio of the n-type FS region 9a is small, the rate of increase of the on-voltage is small, so that the forward peak breakdown voltage can be improved by increasing the impurity peak concentration of the n-type FS region 9a.
In this structure, as described above, since the n region 8 has a low concentration, the structure on the collector side is a structure close to that of the NPT-IGBT. ⁺ Even if a part of the collector region is lost, the influence on the ON voltage is small. As described above, the n-type FS region 9a causes the depletion layer to be p. ⁺ The collector region 7 is not reached and p ⁺ If it is not necessary to suppress the injection of holes from the collector region 7, the n region 8 may not be formed.
[0034]
FIG. 3 is a cross-sectional view of a principal part of the semiconductor device according to the third embodiment of the present invention. N from collector side ^- An insulating material 17 is embedded in a plurality of grooves 16 formed in the semiconductor substrate 100, and an n-type FS region 9b is formed at the tip thereof. It is desirable that the impurity concentration of the n-type FS region 9b be a concentration that does not cause depletion in the forward blocking state. As described above, the distance b from the collector p / n junction 13 to the impurity concentration peak position 15 closest to the p base region 2 side of the n-type FS region 9b is desirably about 0.8 μm or more.
[0035]
As described above, in order to suppress the growth of the depletion layer, the n-type FS layer 9b has a distance c from the base p / n junction 14 to the impurity concentration peak position 15 of the n-type FS layer 9b. The distance b from the impurity peak position 15 to the collector p / n junction 13 should be about 20% or less. Further, as described above, when the area ratio of the n-type FS region 9b is sufficiently small, the rate of increase of the on-voltage is small. Therefore, the forward blocking is achieved by increasing the impurity concentration peak concentration of the n-type FS region 9b. The breakdown voltage can be improved.
[0036]
In this structure, after the groove 16 is formed, an n-type FS region 9b and an n region 8 are formed by ion implantation or embedding a material containing an n-type impurity, and finally, the groove 16 is formed with an insulating material 17. It can be formed by filling. The planar shape of the n-type FS region 9b may be either a cell shape or a stripe shape. The function of the n region 8 is as described above, and the extension of the depletion layer is reduced by the n-type FS region 9b. ⁺ The collector region 7 is not reached, and p ⁺ If it is not necessary to suppress the injection of holes from the collector region 7, it may not be formed.
[0037]
FIG. Is Of this invention First reference example It is principal part sectional drawing of this semiconductor device. The difference from FIG. 1 to FIG. 3 is that a plurality of n-type FS regions 9c are p. ⁺ This is a point in contact with the collector region 7. As described above, the impurity concentration of the n-type FS region 9c is desirably set to a concentration that does not completely deplete in the forward blocking state. When the area ratio of the n-type FS region 9c is sufficiently small, the rate of increase of the on-voltage is small. Therefore, the forward blocking breakdown voltage can be improved by increasing the impurity peak concentration of the n-type FS region 9c.
[0038]
The planar shape of the n-type FS region 9c may be either a cell shape or a stripe shape. Also in this structure, in the forward blocking state, the n-type FS region 9c suppresses the extension of the depletion layer where there is no n-type FS region 9c. ⁺ It becomes difficult to reach the collector region 7 and it is easy to secure a withstand voltage. The elongation of the depletion layer is further suppressed by forming the n region 8, and the breakdown voltage can be easily secured. However, the extension of the depletion layer is reduced by the n-type FS region 9c. ⁺ It does not reach the collector region 7 and p ⁺ If it is not necessary to suppress the injection of holes from the collector region 7, the n region 8 may not be formed.
[0039]
Further, in a place where the n-type FS region 9c is not present, p ⁺ Since the efficiency of hole injection from the collector region 7 does not decrease, the on-voltage can be kept low. The cross-sectional structure where the n-type FS region 9c is not present has a structure close to that of the NPT-IGBT because the impurity concentration of the n region 8 is sufficiently low, and as described above, the p-type structure is less than that of the conventional FS-IGBT. ⁺ A defect in a part of the collector region 7 does not cause an increase in the on-voltage.
[0040]
FIG. 5 shows the present invention. Second reference example It is principal part sectional drawing of this semiconductor device. N from collector side ^- An insulating material 17 is embedded in the groove 16 formed in the semiconductor substrate 100, and an n-type FS region 9d is formed so as to surround it. P ⁺ An n region 8 having an impurity concentration lower than that of the n-type FS region 9d is formed so as to be in contact with the collector region 7. The impurity concentration of the n-type FS region 9d is desirably a concentration that does not cause depletion in the forward blocking state.
[0041]
Further, by increasing the depth of the groove 16, the p of the n-type FS region 9d is increased. ⁺ Although the depth from the collector region surface 12 can be increased, in order to effectively suppress the extension of the depletion layer, from the base p / n junction 14 to the impurity concentration peak position 15 of the n-type FS layer 9d. The distance b from the impurity peak position 15 of the n-type FS layer 9d at the tip 18 to the collector p / n junction 13 is about 20% or less.
[0042]
As described above, when the area ratio of the n-type FS region 9d is sufficiently small, the rate of increase in the on-voltage is small, so that the impurity concentration of the n-type FS region 9d is low. of Peak concentration The By increasing the value, the forward blocking withstand voltage can be improved.
The planar shape of the n-type FS region 9d may be either a cell shape or a stripe shape. As described above, the n region 8 is , The extension of the depletion layer is p by the n-type FS region 9d. ⁺ The collector region 7 is not reached and p ⁺ If it is not necessary to suppress the injection of holes from the collector region 9d, it may not be formed.
[0043]
【Effect of the invention】
According to the invention, p ⁺ The collector region is formed so as not to contact the n-type FS region, and p ⁺ By forming a low concentration n region between the collector region and the n-type FS region, p ⁺ The influence of partial defects in the collector region and the n-type FS region on the ON voltage and the forward blocking breakdown voltage can be reduced.
[0044]
[Brief description of the drawings]
1A and 1B show a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view of an essential part, and FIG.
FIG. 2 is a cross-sectional view of an essential part of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of an essential part of a semiconductor device according to a third embodiment of the present invention.
FIG. 4 of the present invention First reference example Sectional view of the main part of the semiconductor device
FIG. 5 of the present invention Second reference example Sectional view of the main part of the semiconductor device
6A and 6B show the shape of an n-type FS region, where FIG. 6A is a lattice-like view, FIG. 6B is a cell-like view, and FIG. I (D) is an oval figure
7A and 7B are conventional FS-IGBTs, where FIG. 7A is a cross-sectional view of the main part, and FIG.
8 is a punch-through IGBT (PT-IGBT) using a conventional epitaxial substrate, (a) is a cross-sectional view of the main part, and (b) is an impurity concentration distribution diagram on the YY line.
[Explanation of symbols]
1 n ^- Base area
2 p base region
3 n ⁺ Emitter area
4 Gate insulation film
5 Gate electrode
6 Interlayer insulation film
7 p ⁺ Collector area
8 n region
9, 9a, 9b, 9c, 9d n-type FS region
10 Emitter electrode
11 Collector electrode
12 p ⁺ Collector area surface
13 Collector p / n junction
14 base p / n junction
15 Impurity concentration peak position
16 groove
17 Insulation material
18 Tip
21 p ⁺ Shape projected on the collector surface
100 n ^- Semiconductor substrate

Claims

A second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a first conductivity selectively formed on the surface layer of the second conductivity type base region. A first emitter region, a gate electrode formed on the second conductivity type base region sandwiched between the first conductivity type emitter region and the first conductivity type semiconductor substrate via a gate insulating film, and the first conductivity type A thickness formed on the surface layer of the second main surface obtained by thinning the first conductive semiconductor substrate to 150 μm or less on the emitter electrode formed on the type emitter region and the second conductive type base region, and 1 μm or less. A semiconductor device comprising: a second conductivity type collector region; and a collector electrode formed on the second conductivity type collector region,
A first conductivity type field stop region formed in the first conductivity type semiconductor substrate at an impurity concentration higher than the impurity concentration of the first conductivity type semiconductor substrate apart from the second conductivity type collector region; A semiconductor device characterized in that a first conductivity type field stop region and the second conductivity type collector region are separated by a region of impurity concentration of the first conductivity type semiconductor substrate.

A second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a first conductivity selectively formed on the surface layer of the second conductivity type base region. A first emitter region, a gate electrode formed on the second conductivity type base region sandwiched between the first conductivity type emitter region and the first conductivity type semiconductor substrate via a gate insulating film, and the first conductivity type A thickness formed on the surface layer of the second main surface obtained by thinning the first conductive semiconductor substrate to 150 μm or less on the emitter electrode formed on the type emitter region and the second conductive type base region, and 1 μm or less. A semiconductor device comprising: a second conductivity type collector region; and a collector electrode formed on the second conductivity type collector region,
A first conductivity type field stop region formed in the first conductivity type semiconductor substrate at an impurity concentration higher than the impurity concentration of the first conductivity type semiconductor substrate apart from the second conductivity type collector region; The impurity peak concentration of the first conductivity type field stop region is 10 ¹⁵ to 10 ¹⁷ cm ⁻³ , and the first conductivity type semiconductor substrate is between the first conductivity type field stop region and the second conductivity type collector region. The semiconductor device is characterized in that it is isolated in a region having an impurity concentration height within one digit from the impurity concentration.

3. The semiconductor device according to claim 1, wherein a plurality of the first conductivity type field stop regions are formed apart from each other.

A plurality of grooves formed so as to reach the inside of the first conductive type semiconductor substrate from the surface of the second conductive type collector region, an insulating film filling the inside of the grooves, and individual tip portions of the grooves 4. The semiconductor device according to claim 3 , further comprising: the first conductivity type field stop region formed on the semiconductor device.

3. The semiconductor device according to claim 1, wherein a planar shape projected onto the second main surface of the first conductivity type field stop region is a lattice shape. 4.

5. The semiconductor device according to claim 3, wherein a planar shape projected onto the second main surface of the first conductivity type field stop region is a cell shape or a stripe shape. 6.