JP4541060B2 - Semiconductor integrated circuit having built-in A / D conversion circuit and communication semiconductor integrated circuit - Google Patents

Description

  The present invention provides an analog-digital (A / D) conversion circuit for converting an analog signal into a digital signal, and an on-chip A / D conversion including a local A / D conversion circuit and a local D / A conversion circuit. The present invention relates to a technology for stabilizing a reference voltage used for A / D conversion in a circuit, for example, a technology effective for use in a ΣΔ (sigma delta) type A / D conversion circuit and a communication semiconductor integrated circuit incorporating the same. is there.

  Currently, a wireless communication system such as a cellular phone generally includes a semiconductor integrated circuit (RF-IC) having a modulation function of a transmission signal and a demodulation function of a reception signal, and an I signal having an in-phase component with respect to a fundamental wave and transmission data. A semiconductor integrated circuit such as a baseband circuit that converts the I and Q signals demodulated from the received signal into a quadrature component Q signal and restores the data by processing the signal, and amplifies the transmission signal to output from the antenna It is composed of a power module including a power amplifier. Conventionally, I and Q signals transmitted between the RF-IC and the baseband LSI are often analog signals.

  On the other hand, since most of the internal processing of the baseband LSI is performed by digital processing, an AD conversion circuit for converting the received analog I and Q signals input to the digital signal and the transmission digital I and Q signals on the baseband LSI side. A DA converter circuit for converting the signal into an analog signal has been provided. In this case, the baseband LSI incorporates an AD conversion circuit and a DA conversion circuit, which are analog circuits, even though most of them are digital circuits, so that an element constituting the analog circuit is formed in the LSI manufacturing process. There is a problem that the cost of the chip is increased.

  In view of this, the present inventors have considered providing an AD conversion circuit and a DA conversion circuit on the RF-IC side, and transmitting the I and Q signals as digital signals between the RF-IC and the baseband LSI. did. By providing an AD conversion circuit and a DA conversion circuit on the RF-IC side, an AD conversion circuit and a DA conversion circuit are not required on the baseband LSI side, and a process for forming an analog circuit element in the process is not required. This is because the chip cost can be reduced, and in the RF-IC reception system circuit, the high gain amplifier circuit and the filter provided in the subsequent stage of the demodulation circuit can be simplified to reduce the chip size.

  Also, by digitizing the I and Q signals, the signal-to-noise ratio (SNR) can be improved. Even if an AD conversion circuit and a DA conversion circuit are provided on the RF-IC side, the RF-IC originally includes an analog circuit, but the chip size is increased, but the process is not complicated. This can be smaller than the case where an AD conversion circuit and a DA conversion circuit are provided.

  Conventionally, various types of A / D converters such as a successive approximation type and an oversample type have been developed. In general, when an analog input signal is converted into a digital signal by an A / D converter, the SN characteristic near the signal frequency can be improved by increasing the sampling frequency. The oversampling A / D converter is a system in which the SN characteristic is improved by increasing the oversampling ratio (the ratio of the Nyquist (1/2 sampling frequency) frequency to the signal band frequency).

  The oversampled A / D converter can be roughly classified into a Δ (delta) modulation method, a ΣΔ modulation method, and a mixed method thereof. Of these, the ΣΔ modulation method integrates the difference between the output signal and the input signal with an integrator, and performs feedback control so that the output of the integrator is minimized. In this ΣΔ modulation method, the SN characteristic can be further improved by increasing the order of analog integration, that is, the number of integrators. That is, every time the order of analog integration is increased by one, a noise shaping characteristic (noise shaping) almost inversely proportional to the square of the oversampling ratio can be expected.

  As an A / D converter built in the RF-IC and which converts the I and Q signals demodulated by the demodulation circuit into a digital signal, the present inventors have used an oversampling type in terms of modulation accuracy and conversion speed. It was considered that an A / D converter, in particular, a ΣΔ modulation type A / D converter (hereinafter referred to as a ΣΔ A / D converter) was suitable. As an invention in which a ΣΔ A / D converter is provided on the RF-IC side, the I and Q signals demodulated by the demodulation circuit are converted into digital signals and transmitted to the baseband circuit. There is an invention described in 1.

Further, there is an invention described in Patent Document 2 as a prior invention related to the present invention. This prior invention generates a reference voltage for an AD converter circuit in a semiconductor integrated circuit including an AD converter circuit and a DA converter circuit. The reference voltage generation circuit for generating the reference voltage and the reference voltage generation circuit for generating the reference voltage of the DA conversion circuit are separately provided, and the reference voltage generation circuit is separately provided for the local A / D conversion circuit and the local D / A conversion circuit. This is different from the present invention in that it does not disclose a stabilization capacitor that stabilizes the generated reference voltage.
JP 2002-368621 A Japanese Patent Laid-Open No. 11-177423

  In general, a reference voltage is required for an AD conversion circuit or a DA conversion circuit, and the accuracy of the reference voltage must be high in order to obtain a highly accurate AD conversion result or DA conversion result. However, the DA converter circuit is provided with a switch element for switching the reference voltage. The switched capacitor type AD converter circuit is also provided with a switch element and a capacitor element for transferring charges. The reference voltage may vary due to the on / off operation of the switch element. In order to suppress the fluctuation of the reference voltage, conventionally, a stabilization capacitor (bypass capacitor) is generally connected to the output terminal of the reference voltage generation circuit that generates the reference voltage to reduce the impedance.

  In the AD conversion circuit, when it is desired to obtain an AD conversion result with high accuracy of 10 bits or more, a large capacity of about several μF is required as the stabilization capacity, and it is difficult to incorporate this in a semiconductor chip. . In addition, the ΣΔ A / D converter circuit requires at least two types of reference voltages, and the switched capacitor type requires three types of reference voltages, and accordingly three stabilization capacitors are required. It has been found that there are problems that the number of external terminals to be increased increases the chip size and the number of parts.

  An object of the present invention is to connect to an output terminal of a reference voltage generation circuit that generates a reference voltage when an A / D conversion circuit including a local A / D conversion circuit and a local D / A conversion circuit is built in a semiconductor chip. An object of the present invention is to provide a semiconductor integrated circuit including an A / D conversion circuit that can reduce the capacitance value of the stabilization capacitor and thereby avoid an increase in chip size and an increase in the number of external terminals.

Another object of the present invention is to provide a semiconductor integrated circuit incorporating an A / D conversion circuit capable of highly accurate A / D conversion while suppressing an increase in chip size.
Still another object of the present invention is to achieve downsizing of a system using a semiconductor integrated circuit incorporating an A / D conversion circuit.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
That is, in a semiconductor integrated circuit including a local A / D conversion circuit and an A / D conversion circuit having a local D / A conversion circuit, a reference voltage generation circuit for generating a reference voltage necessary for the local A / D conversion circuit and a local A reference voltage generation circuit that generates a reference voltage necessary for the D / A conversion circuit is separately provided.

  According to the above means, a reference voltage generation circuit that generates a reference voltage that does not require high accuracy by connecting a stabilizing capacitor having a large capacitance value to a reference voltage generation circuit that needs to generate a high accuracy reference voltage. In this case, a stabilization capacitor having a small capacitance value can be connected or the stabilization capacitor can be eliminated, so that the reference voltage for the local A / D conversion circuit and the reference voltage for the local D / A conversion circuit can be shared. The required capacitance value of the stabilization capacitor can be reduced as compared with the case where the voltage is generated by the reference voltage generation circuit, and the total capacitance value can be reduced even when the stabilization capacitors are separately connected.

  Here, as an A / D conversion circuit having a local A / D conversion circuit and a local D / A conversion circuit, an integration circuit that integrates a difference between an input and an output, and a local A / D that quantizes the output of the integration circuit. Particularly effective in the case of a ΣΔ A / D conversion circuit having a conversion circuit and a local D / A conversion circuit that D / A converts the output of the local A / D conversion circuit and feeds back to the input side of the integration circuit It is.

  In the ΣΔ A / D conversion circuit, if the output requires 14-bit accuracy, the local D / A conversion circuit is required to have 14-bit accuracy, while the local A / D conversion circuit outputs the output. Since the reference voltage used for the local A / D conversion circuit is much more accurate than the reference voltage used for the local D / A conversion circuit, it is sufficient that the accuracy is 3 bits. It can be low. Therefore, the capacitance value of the stabilization capacitor connected to the reference voltage generation circuit that generates the reference voltage for the local A / D conversion circuit may be considerably small, and may be omitted depending on circumstances.

  Furthermore, the present invention is effective when applied to the case where the ΣΔ A / D conversion circuit is composed of a switched capacitor circuit. Since the switched capacitor circuit is switched, the reference voltage is likely to fluctuate during switching. Therefore, it is desirable that the stabilization capacitance is as large as possible, but the reference voltage necessary for the local A / D converter circuit is generated. By separately providing a reference voltage generation circuit for generating a reference voltage and a reference voltage generation circuit for generating a reference voltage necessary for the local D / A conversion circuit, the reference voltage for the local A / D conversion circuit and the local D / A conversion circuit are provided. As compared with the case where the reference voltage is generated by a common reference voltage generation circuit, the necessary capacitance value of the stabilization capacitor can be reduced.

  In other words, when the reference voltage generation circuit is shared, the reference voltage fluctuation generated by the switching operation of the local A / D conversion circuit and the reference voltage fluctuation generated by the switching operation of the local D / A conversion circuit are converted into a desired conversion accuracy. However, by providing a separate reference voltage generation circuit, the stabilization capacity of the reference voltage generation circuit for the local D / A conversion circuit can be reduced by the local D / A converter. Since it is only necessary to suppress the fluctuation of the reference voltage generated in the switching operation of the A conversion circuit, the stabilization capacity can be reduced.

  At the same time, in the ΣΔ A / D converter circuit, the reference voltage used for the local A / D converter circuit may be less accurate than the reference voltage used for the local D / A converter circuit. The stabilization capacitance of the circuit reference voltage generation circuit can be considerably reduced, and the total capacitance value can be reduced even when the stabilization capacitances are connected separately. Further, by reducing the capacitance value of the stabilization capacitor, it is possible to incorporate it in the semiconductor chip, and an external terminal for connecting the stabilization capacitor becomes unnecessary, and an increase in chip size can be suppressed. . In addition, a highly accurate A / D conversion result can be obtained even if the capacitance value of the stabilization capacitor of the reference voltage generation circuit is small, and an external capacitor element is not required, so that a semiconductor with a built-in A / D conversion circuit It is possible to reduce the size of a system using an integrated circuit.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, when the A / D conversion circuit is built in the semiconductor chip, the capacitance value of the stabilization capacitor connected to the output terminal of the reference voltage generation circuit that generates the reference voltage is reduced, and the stabilization capacitor is integrated in the chip. A semiconductor integrated circuit that can be built in and can avoid an increase in the number of external terminals and an increase in chip size can be realized.

  According to the present invention, it is possible to obtain a semiconductor integrated circuit incorporating an A / D conversion circuit capable of performing high-precision A / D conversion while suppressing an increase in chip size, and incorporating an A / D conversion circuit. There is an effect that it is possible to reduce the size of the system using the semiconductor integrated circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a first embodiment of the ΣΔ modulation type A / D conversion circuit according to the present invention.
The A / D conversion circuit shown in FIG. 1 has a second-order ΣΔ modulation method and is formed on one semiconductor substrate such as a single crystal silicon chip by a known semiconductor integrated circuit manufacturing technique.

  The ΣΔ A / D converter circuit of the embodiment of FIG. 1 includes a first adder circuit 11 that takes the difference between the analog input signal Vin and the feedback signal Vf1, and a first integrator that integrates the output of the first adder circuit 11. A circuit 12, a second adder circuit 13 that takes a difference between the output of the first integrator circuit 12 and the feedback signal Vf2, a second integrator circuit 14 that integrates the output of the second adder circuit 13, and the second The local A / D conversion circuit 15 that converts the output of the integration circuit 14 into an N-bit digital signal and outputs the digital signal, and the output of the A / D conversion circuit 15 is D / A converted, respectively. A first local D / A conversion circuit (DAC1) 17 and a second local D / A conversion circuit (DAC2) 18 that are supplied to the second addition circuit 12 are configured.

  The local A / D conversion circuit 15 may include a quantization circuit 51 that quantizes the output of the second integration circuit 14 by comparing it with a reference voltage, and an encoder 52 that encodes the output of the quantization circuit 51. it can. When the output of the encoder 52 is N bits (N is an integer of 2 or more), the output signal of the quantization circuit 51 is 2 to the Nth power. The quantization circuit 51 includes a voltage comparison circuit that compares the output voltage of the second integration circuit 14 with 2 N reference voltages. The output signals of these voltage comparison circuits are encoded into N-bit signals by the encoder 16 and transmitted to the subsequent circuit as output signals of the ΣΔ A / D conversion circuit of this embodiment.

  At the same time, the output signal of the quantization circuit 51 comprising the voltage comparison circuit is also transmitted to the local D / A conversion circuits 17 and 18, and the signal converted into an analog signal by the local D / A conversion circuits 17 and 18 is The feedback signals Vf1 and Vf2 are supplied to the first addition circuit 11 and the second addition circuit 12. A subtraction circuit that subtracts b from a certain value a can be regarded as an addition circuit that adds -b to a. Therefore, in this specification, the subtraction circuit is referred to as an addition circuit.

  In this embodiment, reference voltage generation circuits 21a, 21b, and 21c that generate reference voltages Vref (+), Vcm, and Vref (−) required by the local A / D conversion circuit 15, and a local D / A conversion circuit. Reference voltage generation circuits 22a, 22b, and 22c that generate the reference voltages Vref (+), Vcm, and Vref (−) required by 17 and 18 are provided as separate circuits. At the same time, relatively small stabilizing capacitors Ca1, Cb1, and Cc1 are provided at the output terminals of the respective reference voltage generation circuits 21a, 21b, and 21c, and relatively large stability is provided at the output terminals of the reference voltage generation circuits 22a, 22b, and 22c. Capacitance capacitors Ca2, Cb2, and Cc2 are connected to each other. Vcm is an intermediate potential between Vref (+) and Vref (-). For example, when Vref (+) is 1.9V and Vref (-) is 0.9V, Vcm is 1.4V. Potential.

  In the ΣΔ A / D converter circuit, if the output requires 14-bit precision, the local D / A converter circuit 17 requires 14-bit precision, while the local A / D converter circuit 15 If the output is 3 bits, it is sufficient if the output has 3 bits precision, so the reference voltage used for the local A / D conversion circuit 15 is compared with the reference voltage used for the local D / A conversion circuit 17. The accuracy may be much lower. Therefore, in the present embodiment, the capacitance values of the stabilizing capacitors Ca1, Cb1, Cc1 connected to the reference voltage generation circuits 21a, 21b, 21c are set to a magnitude of several tens pF, and the reference voltage generation circuits 22a, 22b, 22c The capacitance values of the stabilization capacitors Ca2, Cb2, and Cc2 to be connected are set to a magnitude of several hundred pF.

  The stabilizing capacitors Ca1, Cb1, and Cc1 connected to the reference voltage generation circuits 21a, 21b, and 21c can be omitted. In addition, since the reference voltage Vref (+), Vcm, and Vref (−) may be slightly less accurate than Vref (+) and Vref (−), the reference voltage generation circuit that generates the reference voltage Vcm may be used. The stabilizing capacity Cb2 of 22b can be made smaller than Ca2 and Cc2.

  In the ΣΔ A / D converter circuit of FIG. 1, the reference voltage for the local A / D converter circuit and the reference voltage for the local D / A converter circuit are the same potential, so that they are generated by a common reference voltage generation circuit. The number of reference voltage generation circuits can be reduced. However, in that case, the reference voltages Vref (+), Vcm, Vref (−) are stabilized, and the local D / A conversion circuit 17 has very high precision reference voltages Vref (+), Vcm, Since Vref (−) needs to be supplied, the capacitance values of the stabilizing capacitors Ca0, Cb0, and Cc0 connected to the common reference voltage generation circuit need to be several thousand pF.

  Therefore, when the reference voltage generation circuit is shared, the necessary capacitance values of the stabilization capacitors Ca0, Cb0, and Cc0 are the stabilization capacitors Ca1, C1, and Cc connected to the reference voltage generation circuits 21a, 21b, and 21c of the embodiment. The capacitance value of Cb1, Cc1 and the capacitance value of the stabilization capacitors Ca2, Cb2, Cc2 connected to the reference voltage generation circuits 22a, 22b, 22c become larger than the total capacitance value. This means that a larger area is required when the stabilizing capacitor is formed on the semiconductor chip. When this embodiment is applied, the capacitance value of the stabilization capacitor can be reduced, so that there is an advantage that on-chip implementation is facilitated.

  2 shows a specific circuit example of the reference voltage generation circuits 21a and 22a, FIG. 3 shows a specific circuit example of the local A / D conversion circuit 15, and FIG. 4 shows the local D / A. A specific circuit example of the conversion circuits 17 and 18 is shown, and FIG. 5 shows a specific circuit example of the integration circuits 12 and 14. Although not particularly limited, a switched capacitor type circuit is used in this embodiment.

  As shown in FIG. 2, the reference voltage generation circuits 21a and 22a are generated with a constant voltage circuit CVG including a constant current source CS and a resistor Rc that converts the current Ic from the constant current source CS into a voltage. The voltage followers VF1 and VF2 convert impedance of the constant voltage. In this way, by sharing the constant voltage circuit CVG, it is possible to suppress an increase in circuit scale due to the provision of the reference voltage generation circuit in two. The same applies to the reference voltage generation circuits 21b and 22b and 21c and 22c. The constant current source CS may be composed of a band gap reference circuit that generates a reference voltage that does not depend on the power supply voltage and temperature, and a bipolar transistor or a MOS transistor that receives the generated reference voltage at the base or gate. it can.

  As shown in FIG. 3, the local A / D conversion circuit 15 includes eight comparators CMP1 to CMP8 each including a differential amplifier, and eight pairs of input capacitors C11 and C12 having the same capacitance value; , C82 and eight switches SW11 to SW14;... SW81 to SW84. Each of the comparators CMP1 to CMP8 includes reference voltages Vr1 (+) and Vr1 (−) generated by dividing the reference voltages Vref (+), Vcm, and Vref (−) by a voltage dividing circuit including ladder resistors R1 to R7. Vr4 (+) and Vr4 (-) can be applied to the input capacitors C11 and C12 via the switches SW11 and SW14; SW81 and SW84; The differential outputs Vin (+) and Vin (−) can be applied to the input capacitors C11, C12;... C81, C82 via the switches SW12, SW13,.

  In the first phase (the first half of one cycle of the reference clock φ0), the local A / D conversion circuit 15 in FIG. 3 turns on the switches SW11, SW14;... SW81, SW84 and turns on the input capacitors C11, C12. , C82, the reference voltages Vr1 (+), Vr1 (-);... Are accumulated in the second phase (the second half of one cycle of the reference clock φ0) after charges corresponding to Vr4 (+) and Vr4 (-) are accumulated. Switches SW11, SW14;... SW81, SW84 are turned off, and instead, SW12, SW13;... SW82, SW83 are turned on, and input capacitors C11, C12; ... Inputs Vin, Vin (−) to C81, C82 Is supplied, and the charges according to the voltage difference between Vin (-), Vin (-) and the reference voltages Vr1 (+), Vr1 (-); Vr4 (+), Vr4 (-) are C11, C12; ... remaining in C81 and C82, the comparators CMP1 to CMP8 are respectively It is determined which input voltage is high, and operates so as to output eight comparison results J1 to J8.

  Specifically, when Vin> Vr1 (+), J1 to J8 are all “1”, and when Vr1 (+)> Vin> Vr2 (+), J1 to J7 = “1”, J8 = “0”. Furthermore, when Vr2 (+)> Vin> Vr3 (+), J1 to J6 = “1”, J7, J8 = “0”, and when Vr2 (+)> Vin> Vr3 (+), J1 to J5. = "1", J6 to J8 = "0", ... When Vr3 (-)> Vin> Vr4 (-), J1 = "1", J2 to J8 = "0", Vr4 (-)> When Vin, J1 to J8 = "0".

  The local A / D conversion circuit 15 shown in FIG. 3 does not require the intermediate voltage Vcm in terms of circuit operation. However, by applying the voltage Vcm to the middle point of the ladder resistor, the accuracy of the divided voltage is increased and the cup is used. The divided voltage can be stabilized against noise that enters through the ring capacitance.

  As shown in FIG. 4, the local D / A conversion circuits 17 and 18 include eight capacitors C91 to C98 having the same capacitance value in which one terminal is commonly coupled, and these capacitors C91 to C98. Eight sets of switches S11, S12, S13, each connected to the other terminal, and connected between the common coupling node of capacitors C91 to C98 and the output terminal OUT. Switch SWO and a switch SWG connected between a common coupling node of capacitors C91 to C98 and an analog ground terminal to which a reference voltage Vcm is applied.

  Of the eight sets of switches S11 to S13;... S81 to S83, the first switches S11, S21, S31... S81 transmit the intermediate reference voltage Vcm to the capacitors C91 to C98, and the next switches S12, S22, S32. ... S82 transmits the positive reference voltage Vref (+) to the capacitors C91 to C98, and the remaining switches S13, S23, S33... S83 are for transmitting the negative reference voltage Vref (-) to the capacitors C91 to C98. is there. Switches S12, S22, S32... S82 for transmitting the positive reference voltage Vref (+) to the capacitors C91 to C98, and switches S13, S23, S33... S83 for transmitting the negative reference voltage Vref (-) to the capacitors C91 to C98. Are turned on and the other is turned off according to the outputs J1 to J8 of the eight comparators CMP1 to CMP8 of the local A / D conversion circuit 15.

  4, in the first phase, the switches S11, S21, S31... S81 and the output switch SWO are turned off and the switch SWG is turned on in the first phase, as shown in FIG. Then, the switches S12, S22, S32... S82 and S13, S23, S33... S83 are turned on or off according to the outputs J1 to J8 of the local A / D conversion circuit 15, and the switches of the on state are turned on. Charges corresponding to the potential difference between the input (Vref (+) or Vref (-)) and Vcm are accumulated in the capacitors C91, C92... C98.

  Thereafter, in the second phase, as shown in FIG. 4B, the switches S11, S21, S31... S81 and the output switch SWO are turned on, and the switch SWG and the switches S12, S22, S32. S23, S33... S83 are turned off, and the voltage obtained by adding the charges accumulated in the capacitors C91, C92... C98 is transmitted to the output terminal OUT via the switch SWO and output.

  As shown in FIG. 5, the integration circuits 12 and 14 include a differential amplifier AMP and a pair of integration capacitors CM1 connected between a differential output terminal and a differential input terminal of the differential amplifier AMP. CM2, switches SI1 and SI2 connected between the differential input terminal of the differential amplifier AMP and the input nodes N1 and N2, and an analog ground terminal to which the reference voltage Vcm is applied to the input nodes N1 and N2. Connected to a pair of switches SG1, SG2, a pair of input capacitors CI1, CI2 having one terminal coupled to the input nodes N1, N2, and the other terminals of these capacitors CI1, CI2, respectively. The two switches SI11, SI12 and SI21, SI22 are configured.

  Of the two sets of switch switches SI11, SI12 and SI21, SI22, the switch SI11, SI21 transmits the intermediate reference voltage Vcm to the input capacitors CI1, CI2, and the other switch SI12, SI22 receives the input signal Vin, This is for transmitting Vin (-) to the input capacitors CI1 and CI2. In the integration circuit of this embodiment, the output terminals of the local D / A conversion circuits 17a and 17b are connected to the input nodes N1 and N2. Accordingly, the integrating circuit of FIG. 5 is configured as a circuit including the adding circuit 11 and the integrating circuit 12 (or the adding circuit 13 and the integrating circuit 14) of FIG.

  The local D / A conversion circuits 17a and 17b are circuits that output a positive voltage and a negative voltage having the same absolute value with the reference voltage Vcm applied to the analog ground terminal as the center potential (0 V), respectively. When the circuits 12 and 14 are differential type circuits as shown in FIG. 5, apart from the local D / A conversion circuit (17a) of FIG. 4, the circuits 12 and 14 have the same configuration as that of FIG. A local D / A conversion circuit (17b) that performs reverse-phase operation is provided.

  Further, the capacitors CI1 and CI2 of the integrating circuits 12 and 14 are set so that the ratio with the capacitors C91 to C98 of the local D / A converter circuit is optimal, and the capacitance ratio is a transfer function of the ΣΔ A / D converter circuit. Determined by. The absolute value of the capacitance is determined according to the noise level and the processing accuracy when the capacitance is formed on the semiconductor chip. The transfer function of the ΣΔ A / D conversion circuit is determined by simulation in consideration of the required SN ratio and the stability of the ΣΔ A / D conversion circuit.

  FIG. 6 shows timings of operation clocks φ1 and φ2 having different phases to turn on and off the switches in the integrating circuit of FIG. The operation clocks φ1 and φ2 are formed so that high-level periods do not overlap with each other based on the reference clock φ0 in order to prevent a through current from flowing.

  In the integrating circuit of FIG. 5, the switches SG1, SG2 and SI11, SI21 are turned on by the operation clock φ1 in the first phase, and charges corresponding to the input signals Vin, Vin (−) are accumulated in the input capacitors CI1, CI2. After that, in the second phase, the switches SG1, SG2 and SI11, SI21 are turned off, and SI1, SI2, SI12, SI22 are turned on by the operation clock φ2 and the inputs Vin, Vin (-) and the reference voltage Vcm are set. Charges corresponding to the difference voltage remain in CI1 and CI2. At the same time, the output voltages from the local D / A conversion circuits 17a and 17b are applied to the nodes N1 and N2 and added to the differential input terminal of the differential amplifier AMP via the switches SI1 and SI2. Supplyed and operates to output a voltage obtained by integrating the input voltage by charge redistribution between the input capacitors CI1 and CI2 and the integration capacitors CM1 and CM2.

  As described above, the local A / D conversion circuit 15 and the local D / A conversion circuits 17 and 18 perform a switching operation, and the reference voltage Vref (+), When Vcm and Vref (−) are supplied, the output impedance of the reference voltage generation circuits 21 and 22 or the reference voltage generation circuits 21 and 22 to the local A / D conversion circuit 15 and the local D / A conversion circuits 17 and 18 are determined. If the impedance of the wiring that supplies the voltage is large, the reference voltages Vref (+), Vcm, and Vref (−) may fluctuate when the switch is turned on, but as shown in FIG. In the present embodiment, the stabilization capacitors Ca1, Cb1, and Cc1 are included in the reference voltage generation circuits 21a, 21b, and 21c, and the stabilization capacitor C is included in the reference voltage generation circuits 22a, 22b, and 22c. For 2, Cb2, Cc2 are connected, it is possible to lower the impedance, whereby the reference voltage Vref at the time of switching operation (+), Vcm, Vref - it is possible to suppress the fluctuation of ().

FIG. 7 shows a second embodiment of the A / D conversion circuit according to the present invention. The A / D conversion circuit of the present embodiment is also a secondary ΣΔ modulation type A / D conversion circuit similar to FIG.
In this embodiment, reference voltage generation circuits 21a, 21b, and 21c that generate reference voltages Vref (+), Vcm, and Vref (−) required by the local A / D conversion circuit 15, and a local D / A conversion circuit. 17 and 18, separate reference voltage generation circuits 22 a, 22 b, and 22 c that generate reference voltages Vref (+), Vcm, and Vref (−) required by the local D / A conversion circuit 17 on the first stage side. It is provided as. At the same time, the reference voltage generation circuit for generating the reference voltages Vref (+), Vcm, Vref (−) required by the local D / A conversion circuit 18 on the rear stage among the local D / A conversion circuits 17 and 18 is as follows. The reference voltage generation circuits 21a, 21b and 21c for the local A / D conversion circuit 15 are shared.

  Also in this embodiment, comparatively small stabilizing capacitors Ca1, Cb1, Cc1 are provided at the output terminals of the respective reference voltage generating circuits 21a, 21b, 21c, and comparison is made with the output terminals of the reference voltage generating circuits 22a, 22b, 22c. Large stabilization capacitors Ca2, Cb2, and Cc2 are connected to each other. The capacitance values of the stabilization capacitors Ca1, Cb1, Cc1 may be the same as or slightly larger than those of the first embodiment, and the capacitance values of the stabilization capacitors Ca2, Cb2, Cc2 may be the same as those of the first embodiment or It can be made slightly smaller.

  In the secondary ΣΔ A / D converter circuit, the local D / A converter circuit 17 on the first stage side is required to have the same level of accuracy as the output, while the local D / A converter circuit 18 on the rear stage side has Since high accuracy is not required, a reference voltage generation circuit that generates a reference voltage used for the local A / D conversion circuit 15 and a reference that generates a reference voltage used for the local D / A conversion circuit 18 as in this embodiment. Even if the voltage generation circuit is shared, there is no problem in accuracy.

FIG. 8 shows a third embodiment of the A / D conversion circuit according to the present invention. The A / D conversion circuit of this embodiment is a pipeline type A / D conversion circuit.
The input signal Vin sampled by the sample and hold circuit 31 is converted into a digital signal by the 1-bit local A / D conversion circuit 32a of the first stage and output as a MSB (most significant bit) signal. The output of the A / D conversion circuit 32a is returned to an analog signal by the local D / A conversion circuit 33a, and a difference from the input signal Vin is taken by the addition circuit 34a, and this difference is converted in the second stage.

  In the second stage, the difference between the input signal Vin output from the adder circuit 34a and the output of the D / A converter circuit 33a is amplified by the amplifier circuit 35a, and this is converted into a digital signal by the 1-bit local A / D converter circuit 32b. The signal is converted and output as a second bit signal, and the output of the local A / D conversion circuit 32b is converted back to an analog signal by the local D / A conversion circuit 33b and the output of the amplifier circuit 35a is output by the adder circuit 34b. A difference is taken and this difference is converted in the second stage.

  In the third stage, the difference between the output of the amplifier circuit 35a output from the adder circuit 34b and the output of the D / A converter circuit 33b is amplified by the amplifier circuit 35b, and this is digitally converted by the 1-bit local A / D converter circuit 32c. It is converted into a signal and output as a third bit signal. By repeating the above operation, an AD conversion output having a resolution corresponding to the number of stages can be obtained.

  In the A / D conversion circuit of this embodiment, the quantization error generated in the local A / D conversion circuit is amplified as the stage progresses, so the local A / D conversion circuit in the previous stage is the local A in the later stage. High accuracy is required as compared with the / D conversion circuit. Therefore, in this embodiment, the reference voltage generation circuits 22a, 22b, and 22c that generate the reference voltages Vref (+), Vcm (0V), and Vref (−) required by the first stage local A / D conversion circuit 32a are provided. The reference voltage generation circuits 21a, 21b, and 21c that generate the reference voltages Vref (+), Vcm, and Vref (−) required by the local A / D conversion circuits 32b, 32c,. It is provided as a circuit.

  At the same time, relatively small stabilizing capacitors Ca1, Cb1, and Cc1 are provided at the output terminals of the respective reference voltage generation circuits 21a, 21b, and 21c, and relatively large stability is provided at the output terminals of the reference voltage generation circuits 22a, 22b, and 22c. Capacitance capacitors Ca2, Cb2, and Cc2 are connected to each other. As a result, the same effect as the A / D conversion circuit of the first embodiment can be obtained. In FIG. 8, the reference voltages Vref (+), Vcm, and Vref (−) generated by the reference voltage generation circuits 22a, 22b, and 22c for the first stage local A / D conversion circuit 32a are converted into local A / D converters. Although only the wiring supplied to the circuit 32a is shown, the reference voltages Vref (+), Vcm, Vref (-) are also supplied to the local D / A conversion circuit 33a. The same applies to the reference voltages Vref (+), Vcm, and Vref (−) generated by the reference voltage generation circuits 21a, 21b, and 21c.

  As in the embodiment shown in FIG. 7, the reference voltage generation circuit for generating the reference voltages Vref (+), Vcm, Vref (−) required by the first stage local A / D conversion circuit 32a and the second A local A / D conversion circuit after the third stage is shared with a reference voltage generation circuit that generates reference voltages Vref (+), Vcm, Vref (−) required by the local A / D conversion circuit 32b of the stage. A reference voltage generation circuit that generates the reference voltages Vref (+), Vcm, and Vref (−) required in 32c may be provided as a separate circuit.

  Next, the RF-IC using the ΣΔ A / D conversion circuit of the above embodiment as an A / D converter that converts the I and Q signals that are built in the RF-IC and demodulated by the demodulation circuit into digital signals. A configuration example of the wireless communication system will be described with reference to FIG.

  As shown in FIG. 9, the radio communication system of this embodiment includes a radio wave transmission / reception antenna 100, a transmission / reception switching switch 110, and a high frequency filter 120a to 120a including a SAW filter for removing unnecessary waves from a received signal. 120d, a high-frequency power amplifier circuit (power module) 130 that amplifies the transmission signal, a high-frequency IC 200 that demodulates the reception signal or modulates the transmission signal, converts transmission data into I and Q signals, and controls the high-frequency IC 200 The baseband circuit 300 is configured. The high frequency IC 200 and the baseband circuit 300 are each configured as a semiconductor integrated circuit on separate semiconductor chips.

  Although not particularly limited, the high frequency IC 200 of this embodiment is configured to be capable of modulating / demodulating signals in four frequency bands by the communication schemes of GSM850, GSM900, DCS1800, and PCS1900. In response to this, the high frequency filter includes a filter 120a that passes a received signal in the GSM850 frequency band, a filter 120b that passes a received signal in the GSM900 frequency band, and a filter that passes a received signal in the DCS1800 frequency band. 120c and a filter 120d that allows a received signal in the frequency band of PCS1900 to pass therethrough are provided.

  The high-frequency IC 200 according to the present embodiment is roughly composed of a reception system circuit RXC, a transmission system circuit TXC, and a control system circuit CTC composed of circuits common to the transmission / reception system such as other control circuits and clock generation circuits. The

  The reception system circuit RXC includes low noise amplifiers 210a, 210b, 210c, and 210d that amplify reception signals in each frequency band of GSM850, GSM900, DCS1800, and PCS1900, and a high-frequency oscillation circuit (RFVCO) 251 that generates a local oscillation signal φRF. And an RF synthesizer 252 that constitutes an RF-PLL circuit together with the high-frequency oscillation circuit (RFVCO) 251, and a local oscillation generated by the RF-PLL circuit. Frequency-dividing phase shift circuits 211a and 211b that divide the signal φRF and generate orthogonal signals that are 90 ° out of phase with each other, and the frequency-dividing phase-shifting circuit 211 into the GSM reception signals amplified by the low noise amplifiers 210a and 210b. By demodulating the quadrature signal generated by In addition, the mixer circuit 212a that performs down-conversion and the DCS and PCS received signals amplified by the low noise amplifiers 210c and 210d are mixed with the orthogonal signal generated by the frequency-dividing phase shift circuit 211b to perform demodulation and down-conversion. A mixer circuit 212b is provided.

  The reception system circuit RXC further amplifies the I and Q signals demodulated by the mixer circuits 212a and 212b and outputs the amplified signals to the baseband circuit 300. The offset cancel circuit 213 for canceling the input DC offset of the amplifiers in the gain amplifying units 220A and 220B, and the I and Q signals amplified by the high gain amplifying units 220A and 220B are each converted into, for example, a 3-bit digital signal. A / D conversion circuits 231A and 231B having the configuration as in the above embodiment, and decimation for converting the converted 3-bit signal having a high resolution in the time axis direction into a 14-bit voltage direction having a high resolution. Filter circuits 232A and 232B are provided. By converting a 3-bit signal into a 14-bit low-frequency signal, the data transfer rate from the high-frequency IC 200 to the baseband circuit 300 can be reduced.

  The high gain amplifying unit 220A has a configuration in which a plurality of low pass filters LPF11, LPF12, LPF13, LPF14 and gain control amplifiers PGA11, PGA12, PGA13 are alternately connected in series, and the amplifier AMP1 is connected to the final stage. The demodulated I signal is amplified to a predetermined amplitude level while removing unnecessary waves. Similarly, the high gain amplifying unit 220B has a configuration in which a plurality of low pass filters LPF21, LPF22, LPF23, LPF24 and gain control amplifiers PGA21, PGA22, PGA23 are alternately connected in series, and an amplifier AMP2 is connected to the final stage. And amplifies the demodulated Q signal to a predetermined amplitude level.

  The offset cancel circuit 213 is provided corresponding to each of the gain control amplifiers PGA11 to PGA23, and converts an output potential difference between the input terminals into a digital signal in a state where the input terminals are short-circuited. Based on the conversion result of the / D conversion circuit, a D / A conversion circuit that generates an input offset voltage that makes the DC offset of the output of the corresponding gain control amplifiers PGA11 to PGA23 "0" and gives it to the differential input ( And a control circuit for controlling the A / D conversion circuit (ADC) and the D / A conversion circuit (DAC) to perform an offset cancel operation. The 14-bit digital I and Q signals converted by the decimation filter circuits 232A and 232B are output to the baseband LSI 300 via the digital interface circuit 240.

  Although not shown, the transmission circuit TXC includes a modulation circuit that modulates the I signal and the Q signal supplied from the baseband circuit 300, and a frequency conversion circuit that up-converts the modulated signal to a transmission frequency signal. It has been. The up-converted transmission signal is amplified by the power module 130, unnecessary waves are removed by the filters 141 and 142, and then supplied to the antenna 100 via the changeover switch 110. Although not particularly limited, the power module 130 is provided with a power amplifier 131 that amplifies a GSM transmission signal and a power amplifier 132 that amplifies DCS and PCS transmission signals. In the GSM system, since transmission and reception are performed separately in time, the RF-VCO 251 can be configured to be used as a common oscillation circuit for the reception system circuit RXC and the transmission system circuit TXC.

  Further, on the chip of the high frequency IC 200 of this embodiment, a control circuit 260 for controlling the entire chip, a reference oscillation circuit (VCXO) 261 for generating a reference oscillation signal φref, and the A based on the reference oscillation signal φref There are provided timing generation circuits 262 for generating clock signals φ1 and φ2 that give operation timings of the / D conversion circuits 231A and 231B and a clock signal that serves as a reference for a control signal inside the chip generated by the control circuit 260.

  Since the reference oscillation signal φref is required to have high frequency accuracy, an external crystal resonator is connected to the reference oscillation circuit 261. A frequency such as 26 MHz (or 13 MHz) is selected as the reference oscillation signal φref. This is because a crystal resonator having such a frequency is a general-purpose component and can be easily obtained. In the RF-IC of this embodiment, the clock signals φ1 and φ2 that give the operation timing of the A / D conversion circuits 231A and 231B are also 26 MHz. On the other hand, the converted signal input to the A / D conversion circuits 231A and 231B has a frequency of several hundred kHz. This enables A / D conversion by oversampling.

  The control circuit 260 is supplied with a synchronization clock signal CLK, a data signal SDATA, and a load enable signal LEN as a control signal from the baseband LSI 300, and the control circuit 260 has the load enable signal LEN at an effective level. , The data signal SDATA transmitted from the baseband circuit 300 is sequentially taken in synchronization with the clock signal CLK to generate a control signal inside the chip. Although not particularly limited, the data signal SDATA is transmitted serially. The baseband LSI 300 is composed of a microprocessor and the like.

  In the high frequency IC 200 of this embodiment, the A / D conversion circuits 231A and 231B are provided at the final stage of the reception system circuit so as to digitize the I and Q signals, so that transmission loss to the baseband circuit 300 is reduced. S / N can be improved. Further, by configuring the baseband circuit 300 that receives the digital I and Q signals to perform digital filter processing and the like, the high gain amplifying units 220A and 220B amplify the received signal with a very high gain to remove noise. Since it is possible to obtain received data with high accuracy even without it, it is possible to simplify the gain control amplifiers and filters connected in multiple stages of the high gain amplifying units 220A and 220B, thereby reducing the chip size. Is possible.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, in the embodiment, an example in which the stabilization capacitor is connected to both the reference voltage generation circuit for the local A / D conversion circuit and the reference voltage generation circuit for the local D / A conversion circuit has been described. If the reference voltage generation circuit for the local A / D conversion circuit having a low output impedance is used by configuring the follower with a transistor having a large size, the stabilization capacitor can be omitted. However, if this is done, the area occupied by the reference voltage generation circuit increases, so it is only necessary to decide which one to use in relation to the area that increases by providing a stabilizing capacitor. In particular, regarding the reference voltage generation circuit for the local A / D conversion circuit, since the accuracy required for the generated reference voltage is low, there is a high possibility that the stabilization capacitor can be omitted.

  In the above embodiment, the voltage followers VF1 and VF2 are separately provided for the reference voltages Vref (+) and Vref (−). However, the inverting output terminal has an inverting output terminal and a non-inverting output terminal. Reference voltages Vref (+) and Vref (-) are output from one differential output type amplifier in which resistors are connected between the non-inverting input terminal and between the non-inverting output terminal and the inverting input terminal, respectively. You may comprise as follows.

  Further, in the embodiments, the case where the present invention is applied to a second-order ΣΔ A / D converter circuit has been described. However, the present invention is not limited to a first-order ΣΔ A / D converter circuit or a third-order or higher ΣΔ-type converter. The present invention can also be applied to an A / D conversion circuit. In the embodiment, the case where the local A / D conversion circuit and the local D / A conversion circuit are configured by a switched capacitor type circuit has been described. However, the local A / D conversion that is not a switched capacitor type is described. The present invention can also be applied when using a circuit or a local D / A conversion circuit.

  In the above description, the case where the invention made by the present inventor is mainly applied to a high frequency IC used in a wireless communication system such as a mobile phone which is a field of use as a background has been described. However, the present invention is not limited thereto. In addition, the present invention can be applied to a semiconductor integrated circuit other than for communication that incorporates a ΣΔ A / D converter.

1 is a block diagram showing a first embodiment of an A / D conversion circuit of a ΣΔ modulation system according to the present invention. FIG. It is a circuit block diagram which shows the specific example of the reference voltage generation circuit in the delta-delta type | mold A / D converter of an Example. FIG. 3 is a circuit configuration diagram illustrating a specific example of a local A / D conversion circuit in the ΣΔ A / D conversion circuit of the embodiment. FIG. 3 is a circuit configuration diagram illustrating a specific example of a local D / A conversion circuit in the ΣΔ A / D conversion circuit according to the embodiment. It is a circuit block diagram which shows the specific example of the integration circuit in the (Sigma) delta type | mold A / D converter circuit of an Example. 6 is a timing chart showing timings of operation clocks φ1 and φ2 for turning on and off the switches in the integrating circuit of FIG. 5. FIG. 5 is a functional block diagram of a second embodiment of the ΣΔ modulation type A / D conversion circuit according to the present invention. It is a functional block diagram of the 3rd example of the A / D conversion circuit concerning the present invention. 1 shows a configuration example of an RF-IC and a wireless communication system in which the A / D conversion circuit of the embodiment is used as an A / D converter that converts the demodulated I and Q signals into a digital signal built in the RF-IC. It is a block diagram.

Explanation of symbols

11, 13 Adder circuit 12, 14 Integration circuit 15 Local A / D conversion circuit 17, 18 Local D / A conversion circuit 21, 22 Reference voltage generation circuit 51 Quantization circuit 52 Encoder 100 Antenna 130 Power module 200 High frequency IC (RF− IC)
210 Low Noise Amplifier 212 Mixer 220 High Gain Amplifier 231 3-bit A / D Converter Circuit 251 High Frequency Oscillator 261 Reference Oscillator

Claims (8)

  A semiconductor integrated circuit including an A / D conversion circuit including a local A / D conversion circuit and a local D / A conversion circuit, the first generating a reference voltage used in the local A / D conversion circuit A reference voltage generation circuit and a second reference voltage generation circuit that generates a reference voltage used in the local D / A conversion circuit are provided separately, and an output terminal of the first reference voltage generation circuit and the first reference voltage generation circuit Capacitance elements that stabilize the generated reference voltages are connected to the output terminals of the second reference voltage generation circuit, and the capacitance values of the stabilization capacitance elements connected to the output terminals of the second reference voltage generation circuit are A semiconductor integrated circuit characterized by being larger than a capacitance value of a stabilizing capacitive element connected to an output terminal of the first reference voltage generation circuit.   The A / D conversion circuit includes an integration circuit that integrates a difference between an input and an output of the local D / A conversion circuit, and the local A / D conversion circuit quantizes the output of the integration circuit, and 2. The semiconductor integrated circuit according to claim 1, wherein the / A conversion circuit is a [Sigma] [Delta] A / D conversion circuit that converts the quantized output of the local A / D conversion circuit into an analog signal.   The stabilization capacitor connected to the output terminal of the first reference voltage generation circuit and the output terminal of the second reference voltage generation circuit is the same as the semiconductor chip on which the elements constituting the A / D conversion circuit are formed. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is an on-chip element formed on a semiconductor chip.   The A / D conversion circuit is an n-order ΣΔ A / D conversion circuit including n (two or more) integration circuits and n local D / A conversion circuits, and a local D / A on the rear stage side. 3. The semiconductor integrated circuit according to claim 2, wherein a reference voltage generation circuit that generates a reference voltage used in the conversion circuit is shared with the first reference voltage generation circuit or the second reference voltage generation circuit. .   5. The first reference voltage generation circuit and the second reference voltage generation circuit each include a constant voltage circuit and an impedance conversion circuit, and the constant voltage circuit is shared. The semiconductor integrated circuit as described.   6. The semiconductor integrated circuit according to claim 1, wherein each of the local D / A conversion circuit and the local A / D conversion circuit includes a switched capacitor circuit. A communication semiconductor integrated circuit having a demodulation circuit that synthesizes a reception signal and an oscillation signal of a predetermined frequency and generates a demodulation signal including a frequency component corresponding to the difference between the frequency of the oscillation signal and the frequency of the reception signal. There,
A communication semiconductor integrated circuit comprising the A / D conversion circuit according to claim 2 as a circuit for converting an analog demodulated signal generated by the demodulation circuit into a digital signal.   A PLL circuit including a voltage-controlled oscillation circuit that generates an oscillation signal of the predetermined frequency to be combined with the received signal; and a reference oscillation circuit that generates an oscillation signal serving as a reference, the PLL circuit including the voltage-controlled oscillation The oscillation frequency of the voltage controlled oscillation circuit is controlled by comparing the oscillation output of the circuit with the reference oscillation signal generated by the reference oscillation circuit, and the operation clock signal of the A / D conversion circuit is based on the reference oscillation signal The communication semiconductor integrated circuit according to claim 7, wherein: is generated.

Images