JP4127562B2 - Microcomputer - Google Patents

Description

  The present invention relates to a microcomputer including a nonvolatile flash memory that can rewrite information by electrical erasing / writing.

  Japanese Patent Laid-Open No. 1-161469 discloses EPROM (erasable and programmable read-only memory) or EEPROM (electrically erasable and programmable read-only memory) as a programmable nonvolatile memory. A microcomputer mounted on a single semiconductor chip is described. Programs and data are held in such a non-volatile memory on-chip in a microcomputer. Since the EPROM erases stored information by ultraviolet rays, it cannot be rewritten unless it is removed from the mounting system. Since the EEPROM can be electrically erased and written, the stored information can be rewritten in a state where the EEPROM is mounted on the system. However, the memory cell constituting the EEPROM is MNOS (metal nitride oxide. Since a selection transistor is required in addition to a storage element such as a semiconductor, the size is about 2.5 to 5 times that of an EPROM, and a relatively large chip occupation area is required.

  Japanese Patent Laid-Open No. 2-289997 describes a batch erase type EEPROM. This collective erasure type EEPROM can be grasped in the same meaning as the flash memory in this specification. The flash memory can rewrite information by electrical erasing / writing, and its memory cell can be composed of one transistor as in the case of EPROM. All the memory cells can be collectively or memory cells. It has a function to electrically erase all blocks at once. Therefore, the flash memory can rewrite the stored information in the state where it is mounted on the system, and the batch erase function can shorten the rewrite time, and further contributes to the reduction of the chip occupied area. To do.

JP-A-1-161469 JP-A-2-289997

  The present inventor has studied about mounting a flash memory in a microcomputer, and has found the following points.

  (1) A program and data are stored in the built-in ROM of the microcomputer. Furthermore, there are large capacity data and small capacity data. When rewriting these programs and data, the former is usually rewritten in a large unit of several tens of KB (kilobytes), and the latter is rewritten in a small unit of several tens of B (bytes). At this time, if the erase unit of the flash memory is performed in a batch of chips or a memory block unit of the same size, it is just right for the program area, but the erase unit is too large for the data area, or vice versa. Cases can also occur.

  (2) When a part of the information held in the flash memory is rewritten after the microcomputer is mounted on the system, a part of the memory block holding the information may be rewritten. If the memory capacity of the erasable memory block is the same in all memory blocks, a memory block having a relatively large memory capacity even when only information having a smaller information amount than the memory capacity of the memory block needs to be rewritten. After the data is erased all at once, the entire memory block must be sequentially written, and a waste of time is spent on rewriting for information that does not substantially require rewriting.

  (3) The information to be written in the flash memory is determined according to the system to which the microcomputer is applied, but it is inefficient to write all the information from the beginning with the microcomputer mounted in the system. There are cases.

  (4) When the flash memory is rewritten with the microcomputer mounted, all the information to be written to the entire memory block after erasing at once, even if only a part of the information in the memory block to be rewritten needs to be rewritten In this case, it is only necessary to rewrite a part of the information in the memory block to be rewritten, but all the information to be written in the entire memory block is received from the outside. Information that does not need to be rewritten, that is, information that is held internally before rewriting must also be transferred from the outside in order to transfer information for partial rewriting of memory blocks. There is no use.

  (5) Since the time for rewriting the flash memory by batch erasure is considerably longer than the memory such as RAM (Random Access Memory) because of its information storage format, the flash memory in real time in synchronization with the device control operation by the microcomputer Cannot be rewritten.

  An object of the present invention is to provide a microcomputer having a built-in flash memory that is easy to use. More specifically, a first object of the present invention is to provide a microcomputer capable of improving the efficiency of the first information writing process performed on the built-in flash memory. The second object of the present invention is to rewrite part of the information held in a part of the memory block of the flash memory and eliminate the waste of the write operation after erasing the memory block at once, thereby improving the rewrite efficiency. It is to improve. The third object of the present invention is to improve the rewriting efficiency by eliminating the waste of the transfer operation of the write information from the outside necessary for the partial rewriting of the memory block. A fourth object of the present invention is to make it possible to change information held in a flash memory in real time in synchronization with a control operation of a microcomputer.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, on a single semiconductor chip, a central processing unit, a RAM accessible by the central processing unit, and a non-volatile flash in which information to be processed by the central processing unit can be rewritten by electrical erasing / writing A first operation mode in which a microcomputer having a memory controls rewriting to the flash memory by a built-in circuit of the semiconductor chip, for example, a central processing unit, and a second operation mode in which an external device of the semiconductor chip controls An input terminal for an operation mode signal for selectively specifying is provided.

  When the central processing unit performs rewrite control in accordance with the designation of the first operation mode, the rewrite control program to be executed by the central processing unit is held in the mask ROM or rewritten in advance in the flash memory. The control program can be transferred to the RAM and executed.

  When considering that the amount of information to be stored in the flash memory according to the application varies depending on the type of information such as a program, data table, control data, etc., some memory blocks of the flash memory hold In order to eliminate the waste of the write operation after batch erasing the memory block and improve the rewrite efficiency for partial rewrite of the information, the storage capacity is mutually stored as a batch erasable unit in the flash memory. A plurality of different memory blocks are allocated.

  When controlling the rewriting of flash memory from inside and outside the microcomputer, in order to be able to easily specify the memory block to be erased at once, a register for holding the rewritable memory block designation information Should be built into the flash memory.

  When the built-in flash memory has a plurality of memory blocks having different storage capacities as a unit that can be collectively erased, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory block. A memory block set below the storage capacity of the built-in RAM is provided. At this time, in order to eliminate the waste of the external write information transfer operation necessary for the partial rewrite of the memory block and improve the rewrite efficiency, the retained information of the memory block having a smaller storage capacity than the built-in RAM Is transferred to the built-in RAM, and all or a part of the transferred information is updated on the RAM, and the memory block is rewritten with the updated information. In addition, when tuning the control data held by the flash memory, etc., it is possible to change the information held in the flash memory in real time in synchronization with the control operation of the microcomputer. Is changed and arranged so as to overlap the address of the memory block having a smaller storage capacity than the built-in RAM, that is, when the memory block is accessed, the changed RAM is accessed and the specific address of the RAM is changed. After the operation is performed, the RAM arrangement address may be restored to the original state, and the process of rewriting the contents of the memory block with the information of the specific address of the RAM may be performed.

  According to the above means, when information is first written to the flash memory at a stage before the microcomputer according to the present invention is mounted on the system, the PROM writer is designated by designating the second operation mode. Information is efficiently written by the control of the external writing device.

  For example, a program, a data table, and control data are written in a plurality of memory blocks having different storage capacities as batch erasable units in the flash memory according to the respective storage capacities.

  When the flash memory is rewritten after the microcomputer is mounted on the system, the rewrite control is executed by the central processing unit or the like built in the microcomputer by designating the first operation mode. At this time, data having a relatively large amount of information can be written in a memory block having a relatively large storage capacity, and data having a relatively small amount of information can be written in a memory block having a relatively small storage capacity. That is, a memory block having a storage capacity corresponding to the amount of information to be stored can be used. Therefore, even if a required memory block is erased at once for partial rewriting of the information held in the flash memory, there is a waste of rewriting it after erasing information groups that do not substantially require rewriting. It is prevented as much as possible.

  In particular, the provision of a memory block set below the storage capacity of the built-in RAM among the plurality of memory blocks enables the built-in RAM to be used as a work area or a data buffer area for rewriting the memory block. That is, when the flash memory is rewritten in the mounted state of the microcomputer, the information on the memory block to be rewritten is transferred to the built-in RAM, and only a part of the information to be rewritten is received from the outside and rewritten on the RAM. If the flash memory is rewritten, it is not necessary to superimpose information held inside that does not need to be rewritten before it is transferred from the outside, thus eliminating waste of information transfer for partial rewriting of the memory block. . Also, the flash memory batch erase time is not so short even for small memory blocks, so the flash memory itself cannot be rewritten in real time in synchronization with the control operation by the microcomputer, but the internal RAM is rewritten to the memory block. By using it as a work area or a data buffer area, the same data that has been rewritten in real time can be obtained in the memory block as a result.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, since the microcomputer according to the present invention has the first operation mode and the second operation mode, a relatively large amount of information such as initial data or an initial program before mounting the microcomputer in the system is transferred to the general-purpose PROM writer. You can write efficiently. Furthermore, when tuning data while operating a system on which a microcomputer is installed, and when data is stored in a state where the microcomputer is installed in the system, such as program bug countermeasures or program changes associated with system upgrades, etc. When the program needs to be changed, the flash memory can be rewritten without removing the microcomputer from the mounting system.

  By providing a plurality of memory blocks having different storage capacities as a unit that can be collectively erased in a flash memory, relatively large amount of data is relatively transferred to memory blocks having a relatively large storage capacity. In particular, data with a small amount of information can be written in a memory block with a relatively small storage capacity, and a memory block with a storage capacity suitable for the amount of information to be stored can be used. Therefore, it is possible to prevent a situation where the erasing unit is too large for the program area but is difficult to use. In addition, even if a required memory block is erased at once for partial rewriting of information held in the flash memory, information that does not substantially need to be rewritten is erased together and then rewritten again. It can be prevented as much as possible.

  By providing a memory block set below the storage capacity of the built-in RAM among the plurality of memory blocks, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory block. Under these conditions, when the flash memory is rewritten with the microcomputer mounted, the information on the memory block to be rewritten is transferred to the built-in RAM, and only a part of the information to be rewritten is received from the outside and stored on the RAM. By rewriting the flash memory after rewriting, it is not necessary to superimpose information stored inside that does not need to be rewritten before being rewritten and transferred from the outside. It is possible to eliminate the waste of information transfer. Also, when tuning the data held in the flash memory, the address of the internal RAM is overlapped with the address of the memory block of the flash memory, tuning is performed on the RAM, and the tuning result is stored in the corresponding memory block of the flash memory. By transferring, even if the flash memory itself cannot be rewritten in real time in synchronization with the control operation by the microcomputer, the same data as that rewritten in real time can be obtained in the memory block as a result.

  By incorporating a rewritable register in the flash memory to specify the memory block specification information to be erased in a batch, the memory block to be erased in a batch can be easily designated from the inside and outside of the microcomputer in the same procedure. Become.

  With the above effects, the usability of the flash memory built in the microcomputer can be improved.

  Hereinafter, the microcomputer according to the present invention will be described in order.

[1] Microcomputer Employing Entire Flash Memory FIG. 1 is a block diagram showing an embodiment of a microcomputer employing an entire flash memory. The microcomputer MCU shown in the figure includes a central processing unit CPU, a non-volatile flash memory FMRY that can rewrite information to be processed by the central processing unit CPU by electrical erasing and writing, a timer TMR, a serial A peripheral circuit such as a communication interface SCI, a random access memory RAM, other input / output circuit I / O, and a control circuit CONT are formed by a known semiconductor integrated circuit manufacturing technique into a single semiconductor chip CHP such as silicon. Formed on top. The flash memory FMRY can rewrite information by electrical erasing / writing, and its memory cell can be composed of a single transistor as in the case of EPROM. Alternatively, the memory cell block (memory block) is electrically erased collectively. The flash memory FMRY has a plurality of memory blocks as a unit that can be collectively erased. In FIG. 1, LMB is a large memory block having a relatively large storage capacity, and SMB is a small memory block having a relatively small storage capacity. The storage capacity of the small memory block SMB is made smaller than the storage capacity of the random access memory RAM. Therefore, the random access memory RAM can receive the data transfer from the small memory block SMB and temporarily hold the information, and the work area for rewriting can be used as the data buffer area. Necessary data and programs are written in the flash memory FMRY. The details of the flash memory FMRY will be described later.

  The flash memory FMRY is rewritable on the basis of the control of the central processing unit CPU with the microcomputer MCU mounted on the system, and the external memory of the semiconductor chip CHP such as a general-purpose PROM writer. Based on the control, the stored information can be rewritten. In the figure, MODE is an operation mode signal for selectively designating a first operation mode in which the flash memory FMRY is controlled to be rewritten by the central processing unit CPU and a second operation mode in which the external device is controlled. It is given to the mode signal input terminal Pmode on the CHP.

[2] Microcomputer Employing Mask ROM and Flash Memory FIG. 2 is a block diagram showing an embodiment of a microcomputer employing a mask ROM together with the flash memory. In the microcomputer MCU shown in the figure, a part of the flash memory FMRY of FIG. 1 is replaced with a mask read only memory MASKROM. The mask read only memory MASKROM holds data and programs that do not require rewriting. The flash memory FMRY shown in FIG. 2 has a plurality of the small memory blocks SMB as a unit that can be collectively erased.

[3] Information writing by general-purpose PROM writer FIG. 3 is a block diagram focusing on rewriting of the flash memory FMRY by the general-purpose PROM writer. In the figure, MD0, MD1, and MD2 are shown as an example of the mode signal MODE. Mode signals MD1 to MD3 are supplied to the control circuit CONT. The decoder included in the control circuit CONT is not particularly limited, but the mode signals MD1 to MD3 are decoded to indicate an operation mode that does not require writing to the flash memory FMRY, or the first operation mode or the first operation mode. 2. It is determined whether the operation mode is instructed. At this time, when the instruction of the second operation mode is determined, the control circuit CONT designates the I / O port to be interfaced with the general-purpose PROM writer PRW, and the internal flash memory FMRY is directly connected to the external general-purpose PROM writer PRW. Control access. That is, I / O port PORTdata for inputting / outputting data to / from the flash memory FMRY, I / O port PORTaddr for supplying an address signal to the flash memory FMRY, and various control signals to the flash memory FMRY. An I / O port PORTcont for supply is designated. Furthermore, substantial operations of built-in functional blocks such as the central processing unit CPU, random access memory RAM, and mask read only memory MASKROM that are not directly related to the rewrite control by the general-purpose PRO writer PRW are suppressed. For example, as shown in FIG. 3, the connection between the built-in functional block such as the central processing unit CPU and the flash memory FMRY is cut off via the switch means SWITCH arranged in the data bus DBUS and the address bus ABUS. Release. The switch means SWITCH is a tri-state (3-state) type output circuit arranged in a circuit that outputs data from a built-in functional block such as the CPU to the data bus DBUS or a circuit that outputs an address to the address bus ABUS. It can also be grasped. Such a tri-state output circuit is controlled to a high output impedance state in response to the second operation mode. In the example of FIG. 3, the built-in functional blocks such as the central processing unit CPU, random access memory RAM, mask read only memory MASKROM, etc., which are not directly related to the rewrite control by the general-purpose PRO writer, have the standby signal STBY * (symbol * Means that the signal to which it is attached is a low active signal). If the tri-state output circuit is controlled to a high output impedance state in the low power consumption mode, the low power consumption mode is set in those functional blocks in response to the designation of the second operation mode by MD0 to MD2 with the mode signal. Thus, substantial operations of built-in functional blocks such as CPU, RAM, and ROM that are not directly related to the rewrite control by the general-purpose PRO writer PRW may be suppressed.

  The I / O ports PORTdata, PORTaddr, and PORTcont of the microcomputer MCU in which the second operation mode is set are coupled to the general-purpose PROM writer PRW via the conversion socket SOCKET. The conversion socket SOCKET has a terminal arrangement of I / O ports PORTdata, PORTaddr, and PORTcont on one side, and a terminal arrangement of a standard memory on the other side, and the same function terminals are mutually connected internally.

[4] Write Control Program Under CPU Control FIG. 4 is a block diagram focusing on rewriting of the flash memory FMRY under CPU control. A rewrite control program to be executed by the central processing unit CPU in the microcomputer MCU shown in FIG. 1 is previously written in the flash memory FMRY by the general-purpose PROM writer PRW. In the microcomputer MCU shown in FIG. 2, the rewrite control program to be executed by the central processing unit CPU can be held in the mask read only memory MASKROM. When the first operation mode is instructed by the mode signals MD0 to MD2, and the control circuit CONT recognizes this, the central processing unit CPU can execute the write control program already written in the flash memory FMRY, or the mask read Data is written into the flash memory FMRY in accordance with a rewrite control program held in the only memory MASKROM.

  FIG. 5 shows a memory map of a microcomputer (see FIG. 1) which is a full-scale flash memory. In the figure, a rewrite control program and a transfer control program are written in advance in a predetermined area of the flash memory. When the first operation mode is instructed, the central processing unit CPU executes the transfer control program and transfers the rewrite control program to the random access memory RAM. After the end of the transfer, the processing of the central processing unit CPU branches to the execution of the rewrite control program on the random access memory RAM, whereby erasing and writing (including verification) to the flash memory FMRY are repeated.

  FIG. 6 shows a memory map of a microcomputer (see FIG. 2) having a mask ROM together with a flash memory. In this case, the transfer control program described with reference to FIG. 5 is unnecessary. When the first operation mode is instructed, the central processing unit CPU sequentially executes a rewrite control program held in the mask read only memory MASKROM, whereby erasing and writing to the flash memory FMRY are repeated.

  FIG. 7 shows an example control procedure of erasure by the central processing unit CPU. First, the central processing unit CPU pre-writes the memory cells in the address range to be erased according to the rewrite control program. As a result, all the states of the memory cells before erasure are made to the written state. Next, the erase target memory cell is erased little by little, and the degree of erase is verified each time (erase / verify) to prevent over-erasure and the erase operation is completed. Erasing by the general-purpose PROM writer PRW is similarly performed. The erase sequence of the flash memory will be described later in detail.

  FIG. 8 shows an example control procedure of writing by the central processing unit CPU. First, the central processing unit CPU sets a write start address of the flash memory FMRY. Next, data sent from the outside is read via a peripheral circuit designated by the rewrite control program, for example, the serial communication interface SCI or the I / O port. The data thus read is written to the flash memory FMRY for a predetermined time, and the written data is read to verify whether it has been normally written (write / verify). Thereafter, reading, writing and verifying of the data are repeated until the write end address. Writing by the general-purpose PROM writer PRW is similarly performed. However, in this case, the data to be written is given from the PROM writer PRW through a predetermined port. The flash memory write sequence will be described later in detail.

[5] Use of General-Purpose PROM Writer and CPU-Controlled Writing The general-purpose PROM writer mainly writes the initial data before on-boarding the microcomputer MCU, that is, before the microcomputer MCU is installed in the system, or the initial program. Applies to Thereby, a relatively large amount of information can be written efficiently.

  CPU control writing is performed when data tuning is performed while a system (also referred to as a mounting machine) on which a microcomputer MCU is mounted, or when a program bug countermeasure or program change associated with a system upgrade is performed. This is applied when data or a program needs to be changed while the computer MCU is mounted on the system (on-board state). Thereby, the flash memory FMRY can be rewritten without removing the microcomputer MCU from the mounting system.

[6] Correspondence to real-time rewriting FIG. 9 shows an example of a technique for dealing with real-time rewriting of a flash memory. Since the flash memory FMRY has a storage format, the time required for erasure is not shortened even if the memory capacity of the memory block as a batch erasure unit is reduced. For example, it takes several tens of milliseconds to several seconds. As a result, it is difficult to tune data by rewriting control data and the like held in the flash memory FMRY in real time while operating a system in which the microcomputer MCU is mounted. In order to cope with this, the built-in RAM is used as a work area or a data buffer area for rewriting a memory block. That is, first, data of a predetermined small memory block SMB holding data to be tuned is transferred to a specific address of the random access memory RAM. Next, the specific address area of the random access memory RAM is overlapped with the address of a predetermined small memory block SMB. Such a change in the address arrangement can be realized by making it possible to switch the decoding logic of the random access memory RAM in response to the setting of a predetermined control bit or flag. Tuning of control data and the like is performed using a random access memory RAM in which addresses of a predetermined memory block SMB are overlapped. After completing the tuning, the address overlap between the random access memory RAM and the memory block SMB is released, and the arrangement address of the random access memory RAM is restored to the original state. Finally, the tuned data held in the random access memory RAM is used to rewrite the memory block SMB of the flash memory. As a result, the same data as when the control data held by the flash memory is rewritten in real time can be obtained in the memory block SMB as a result of operating the system in which the microcomputer MCU is mounted.

[7] Efficiency of Partial Rewriting of Memory Block FIG. 10 shows an example of a technique for improving the efficiency of partial rewriting of a memory block of a flash memory. When rewriting a part of information held in a predetermined memory block SMB of the flash memory FMRY when correcting a bug of the program or upgrading the version, information held in a memory block SMB having a smaller storage capacity than the RAM is incorporated. The data is transferred to the RAM, a part of the transferred information is updated on the RAM, and the memory block is rewritten with the updated information. As a result, even if one of the memory blocks SMB is erased at once, the retained information of the memory block SMB is stored in the RAM. Therefore, if only the data to be rewritten is received from the outside and rewritten on the RAM, The information that does not need to be rewritten and stored in the flash memory FMRY before the rewriting does not need to be transferred from the outside, and the waste of information transfer for partial rewriting of the memory block can be eliminated.

[8] Principle of Flash Memory FIG. 11 shows the principle of flash memory. The memory cell exemplarily shown in FIG. 2A is composed of an insulated gate field effect transistor having a two-layer gate structure. In the figure, 1 is a P-type silicon substrate, 2 is a P-type diffusion layer formed on the silicon substrate 1, and 4 is an N-type diffusion layer. 5 is a floating gate formed on the P-type silicon substrate 1 through a thin oxide film 6 (for example, 10 nm thick), 7 is a control gate formed on the floating gate 5 through an oxide film 8, Is a source and 10 is a drain. Information stored in the memory cell is substantially held in the transistor as a change in threshold voltage. Unless otherwise specified, a case where a transistor for storing information (hereinafter referred to as a storage transistor) is an N-channel type in a memory cell will be described below.

  The operation of writing information to the memory cell is realized, for example, by applying a high voltage to the control gate 7 and the drain 10 and injecting electrons from the drain 10 side to the floating gate 5 by avalanche injection. As shown in FIG. 11B, the threshold voltage seen from the control gate 7 of the memory transistor becomes higher than that of the memory transistor in the erased state where the programming operation is not performed.

  On the other hand, the erase operation is realized, for example, by applying a high voltage to the source and extracting electrons from the floating gate 7 to the source 9 side by a tunnel phenomenon. As shown in FIG. 11B, the threshold voltage viewed from the control gate 7 of the memory transistor is lowered by the erase operation. In FIG. 11B, the threshold value of the memory transistor is set to a positive voltage level in both the writing and erasing states. That is, the threshold voltage in the write state is increased and the threshold voltage in the erase state is decreased with respect to the word line selection level applied from the word line to the control gate. Since both the threshold voltages and the word line selection level have such a relationship, a memory cell can be configured with a single transistor without employing a selection transistor. In the case of electrically erasing stored information, the stored information is erased by pulling out the electrons accumulated in the floating gate to the source electrode. Therefore, if the erase operation is continued for a relatively long time, the write operation is performed. At this time, more electrons are drawn than the amount of electrons injected into the floating gate. For this reason, when over-erasing is performed such that electrical erasing is continued for a relatively long time, the threshold voltage of the storage transistor becomes, for example, a negative level, which is disadvantageous in that it is selected even at a non-selected level of the word line. Arise. Note that writing can also be performed using a tunnel current in the same manner as erasing.

  In the read operation, the voltage applied to the drain 10 and the control gate 7 is relatively low so that weak writing to the memory cell, that is, unwanted carrier injection into the floating gate 5 is not performed. Limited to value. For example, a low voltage of about 1 V is applied to the drain 10 and a low voltage of about 5 V is applied to the control gate 7. By detecting the magnitude of the channel current flowing through the memory transistor using these applied voltages, it is possible to determine “0” or “1” of the information stored in the memory cell.

  FIG. 12 shows the configuration principle of a memory cell array using the memory transistor. In the figure, typically four memory transistors (memory cells) Q1 to Q4 are shown. In memory cells arranged in a matrix in the X and Y directions, the control gates (selection gates of memory cells) of the storage transistors Q1, Q2 (Q3, Q4) arranged in the same row respectively correspond to the corresponding word lines WL1 (WL2). The drain regions (input / output nodes of the memory cells) of the storage transistors Q1, Q3 (Q2, Q4) arranged in the same column are connected to the corresponding data lines DL1, DL2, respectively. Source regions of the storage transistors Q1, Q3 (Q2, Q4) are coupled to a source line SL1 (SL2).

  FIG. 13 shows an example of voltage conditions for an erase operation and a write operation for a memory cell. In the figure, a memory element means a memory cell, and a gate means a control gate as a selection gate of the memory cell. In the figure, erasing in the negative voltage method forms a high electric field necessary for erasing by applying a negative voltage such as -10 V to the control gate. As is clear from the voltage conditions illustrated in the figure, at the time of erasing in the positive voltage system, at least batch erasing can be performed on memory cells whose sources are commonly connected. Therefore, in the configuration of FIG. 12, if the source lines SL1 and SL2 are connected, the four memory cells Q1 to Q4 can be erased collectively. In this case, the size of the memory block can be arbitrarily set by changing the number of memory bits connected to the same source line. In the case of the source line division method, the memory block which is the minimum batch erase unit is one data line. On the other hand, in the case of erasing using the negative voltage method, it is possible to perform batch erasing on at least memory cells to which control gates are commonly connected.

[9] Multiple Memory Blocks with Different Storage Capacities FIG. 14 is a circuit block diagram showing an example of a flash memory with different storage capacities for batch erasable memory blocks.

  The flash memory FMRY shown in the figure has 8-bit data input / output terminals D0 to D7, and includes a memory array ARY0 to ARY7 for each data input / output terminal. Memory arrays ARY0 to ARY7 are divided into two, memory block LMB having a relatively large storage capacity and memory block SMB having a relatively small storage capacity. In the figure, the details of the memory array ARY0 are representatively shown, but the other memory arrays ARY1 to ARY7 are similarly configured.

  In each of the memory arrays ARY0 to ARY7, memory cells MC constituted by the insulated gate field effect transistors having the two-layer gate structure described with reference to FIG. 11 are arranged in a matrix. In the same figure, WL0 to WLn are word lines common to all the memory arrays ARY0 to ARY7. The control gates of the memory cells arranged in the same row are connected to the corresponding word lines. In each of the memory arrays ARY0 to ARY7, the drain regions of the memory cells MC arranged in the same column are connected to the corresponding data lines DL0 to DL7, respectively. The source regions of the memory cells MC constituting the memory block SMB are commonly connected to the source line SL1, and the source regions of the memory cells MC constituting the memory block LMB are commonly connected to the source line SL2.

  The source lines SL1 and SL2 are supplied with a high voltage Vpp used for erasing from the voltage output circuits VOUT1 and VOUT2. The output operation of the voltage output circuits VOUT1 and VOUT2 is selected by the values of the bits B1 and B2 of the erase block designation register. For example, by setting “1” in the bit B1 of the erase block designation register, only the memory blocks SMB of the memory arrays ARY0 to ARY7 can be erased collectively. When “1” is set in the bit B2 of the erase block designation register, only the memory blocks LMB of the memory arrays ARY0 to ARY7 can be erased collectively. When both bits B1 and B2 are set to "1", the entire flash memory can be erased collectively.

  The selection of the word lines WL0 to WLn is performed by the row address decoder XADEC decoding the row address signal AX taken in via the row address buffer XABUFF and the row address latch XALAT. The word driver WDRV drives the word line based on the selection signal output from the row address decoder XADEC. In the data read operation, the word driver WDRV is operated using a voltage Vcc such as 5 V and a ground potential such as 0 V supplied from the voltage selection circuit VSEL as power sources, and drives a word line to be selected to a selected level by the voltage Vcc. Then, the word line to be unselected is maintained at a non-selected level such as the ground potential. In the data write operation, the word driver WDRV is operated with a voltage Vpp such as 12V supplied from the voltage selection circuit VSEL and a ground potential such as 0V as power supplies, and the word line to be selected is written as 12V. Drive to high voltage level. In the data erasing operation, the output of the word driver WDRV is set to a low voltage level such as 0V.

  In each of the memory arrays ARY0 to ARY7, the data lines DL0 to DL7 are commonly connected to a common data line CD via column selection switches YS0 to YS7. The column selection switches YS0 to YS7 are controlled by the column address decoder YADEC decoding the column address signal AY fetched through the column address buffer YABUFF and the column address latch YALAT. The output selection signal of the column address decoder YADEC is supplied in common to all the memory arrays ARY0 to ARY7. Therefore, when any one of the output selection signals of the column address decoder YADEC is set to the selection level, one data line is connected to the common data line CD in each of the memory arrays ARY0 to ARY7.

  Data read from the memory cell MC to the common data line CD is applied to the sense amplifier SAMP via the selection switch RS, where it is amplified and output to the outside from the data output buffer DOBUFF. The selection switch RS is set to a selection level in synchronization with the read operation. Write data supplied from the outside is held in the data input latch circuit DILAT via the data input buffer DIBUFF. When the data held in the data input latch circuit DILAT is “0”, the write circuit WRIT supplies a high voltage for writing to the common data line CD via the selection switch WS. The high voltage for writing is supplied to the drain of the memory cell to which the high voltage is applied to the control gate by the row address signal AX through the data line selected by the column address signal AY, thereby writing the memory cell. The selection switch WS is set to the selection level in synchronization with the write operation. The write / erase control circuit WECONT generates various write / erase timings and voltage selection control.

[10] Details of Microcomputer Corresponding to FIG. 1 FIG. 15 is a block diagram showing a more detailed embodiment of the microcomputer corresponding to the microcomputer of FIG. The microcomputer MCU shown in the figure includes a central processing unit CPU, a flash memory FMRY, a serial communication interface SCI, a control circuit CONT, and a random access memory RAM as the same functional blocks as the functional blocks shown in FIG. including. As equivalent to the timer of FIG. 1, a 16-bit integrated timer pulse unit IPU and a watchdog timer WDTMR are provided. Further, ports PORT1 to PORT12 are provided as equivalent to the input / output circuit I / O of FIG. As other functional blocks, a clock oscillator CPG, an interrupt controller IRCONT, an analog / digital converter ADC, and a wait state controller WSCONT are provided. The central processing unit CPU, flash memory FMRY, random access memory RAM, and 16-bit integrated timer pulse unit IPU include an address bus ABUS, a lower data bus LDBUS (for example, 8 bits), and an upper data bus HDBUS. (For example, 8 bits). The serial communication interface SCI, the watchdog timer WDTMR, the interrupt controller IRCONT, the analog / digital converter ADC, the wait state controller WSCONT, and the ports PORT1 to PORT12 are connected to an address bus ABUS and an upper data bus HDBUS.

  In FIG. 15, Vpp is a high voltage for rewriting the flash memory FMRY. EXTAL and XTAL are signals given to the clock oscillator CPG from a vibrator (not shown) externally attached to the microcomputer chip. φ is a synchronous clock signal output from the clock oscillator CPG to the outside. MD0 to MD2 are mode signals supplied to the control circuit CONT to set the first operation mode or the second operation mode when the flash memory FMRY is rewritten, and correspond to the mode signal MODE in FIG. RES * is a reset signal and STBY * is a standby signal, which are supplied to the central processing unit CPU and other circuit blocks. NMI is a non-maskable interrupt signal and gives an interrupt that cannot be masked to the interrupt controller ICONT. Other interrupt signals (not shown) are provided to the interrupt controller ICONT via the ports PORT8 and PORT9. AS * is an address strobe signal indicating the validity of an address signal output to the outside, RD * is a read signal notifying the outside that it is a read cycle, and HWR * is an externally indicating that it is a write cycle of upper 8 bits. The upper byte write signal to be notified, LWR * is a lower byte write signal for notifying the outside that it is a lower 8-bit write cycle, and is an access control signal to the outside of the microcomputer MCU.

  Except for the second operation mode in which the flash memory FMRY is directly rewritten and controlled by an external PROM writer, the input / output of the data BD0 to BD15 for the microcomputer MCU to access the outside is not particularly limited, but the ports PORT1, PORT2 Is assigned. The output of the address signals BA0 to BA19 at this time is not particularly limited, but the ports PORT3 to PORT5 are assigned.

  On the other hand, when the second operation mode is set in the microcomputer MCU, the ports PORT2 to PORT5 and PORT8 are assigned to the PROM writer for rewriting control of the flash memory FMRY, although not particularly limited. That is, the port PORT2 is assigned to input / output data ED0 to ED7 for writing and verifying, and input of address signals EA0 to EA16 and access control signals CE * (chip enable signal), OE * (output enable signal). , WE * (write enable signal) are assigned the ports PORT3 to PORT5 and PORT8. The chip enable signal CE * is an operation selection signal for the flash memory FMRY from the PROM writer, the output enable signal OE * is an output operation instruction signal for the flash memory FMRY, and the write enable signal WE * is for the flash memory FMRY. This is an instruction signal for a write operation. Incidentally, the input terminal of the signal NMI is assigned to the input of one bit EA9 of the address signals EA0 to EA16. Other necessary external terminals such as the external terminal of the port assigned in this way and the application terminal of the high voltage Vpp are connected to the general-purpose PROM writer PRW via the conversion socket SOCKET described in FIG. The assignment of the external terminals at this time can be considered so that the terminal arrangement is easy to connect the microcomputer MCU to the PROM writer PRW via the conversion socket SOCKET. In the second operation mode, the external terminal group assigned to the connection with the PROM writer PRW is assigned another function in the other operation mode of the microcomputer MCU.

  FIG. 16 shows an upper surface of a flat package having external terminals in four directions obtained by sealing the microcomputer MCU shown in FIG. 15 with, for example, resin. The signals shown in FIG. 16 are the same as those in FIG. External terminals (pins) not indicated by signal names are input pins for wait signals, input pins for bus request signals, output pins for bus acknowledge signals, serial communication interface SCI, and other peripheral circuits. Used for output pins.

  In the package FP shown in FIG. 16, the interval between the terminals (pins) derived from the package FP may be 0.5 mm or less. That is, when the user of the microcomputer MCU connects the flash memory FMRY in the microcomputer MCU to the PROM writer PRW via the conversion socket SOCKET and writes data into the flash memory FMRY, the terminal interval (pin pitch) of the package FP When PP is 0.5 mm or less, when the package FP is inserted into the conversion socket SOCKET, pin bending due to undesired contact between the conversion socket SOCKET and the external terminals of the package FP is likely to occur. Become. When such pin bending occurs, electrical connection between each terminal of the conversion socket SOCKET and each terminal of the package FP is not performed with respect to the terminal where pin bending occurs. As a result, data cannot be written to the flash memory FMRY by the PROM writer PRW.

  In this regard, in the present invention, since the central processing unit CPU can write data to the flash memory FMRY, the user does not use the external PROM writer PRW to write data to the flash memory FMRY, but the micro processor After the package of the computer MCU is mounted on a mounting board (printed board), if the central processing unit CPU writes data into the flash memory FMRY, the microcomputer MCU has a pin pitch PP of 0.5 mm or less. Even if sealed, the user can prevent lead bending of the external terminal led out of the package. Since the semiconductor manufacturer has an automatic handler, even if the microcomputer MCU is sealed in a package having a pin pitch of 0.5 mm or less, the microcomputer MCU can be reliably tested without causing pin bending. Can be executed.

[11] Rewrite Control Circuit for Flash Memory FMRY FIG. 17 shows an overall block diagram of the flash memory FMRY built in the microcomputer MCU shown in FIG. In the figure, ARY is a memory array in which memory cells constituted by the insulated gate field effect transistors having the two-layer gate structure described in FIG. 11 are arranged in a matrix. In the memory array ARY, similarly to the configuration described with reference to FIG. 14, the control gates of the memory cells are connected to the corresponding word lines, the drain regions of the memory cells are connected to the corresponding data lines, and the source regions of the memory cells. Are connected to a common source line for each memory block, but the division of the memory block is different from that of FIG. For example, as shown in FIG. 18, seven large memory blocks (large blocks) LMB0 to LMB6 having relatively large storage capacities, and eight small memory blocks having relatively small storage capacities ( Small block) is divided into SMB0 to SMB7. The large memory block is used as a program storage area or a large capacity data storage area. The small memory block is used for a small capacity data storage area or the like.

  In FIG. 17, ALAT is a latch circuit for address signals PAB0 to PAB15. In the first operation mode, the address signals PAB0 to PAB15 correspond to the output address signal of the central processing unit CPU. In the second operation mode, the address signals PAB0 to PAB15 correspond to the output address signals EA0 to EA15 of the PROM writer PRW. XADEC is a row address decoder for decoding a row address signal fetched through the address latch ALAT. WDRV is a word driver that drives a word line based on a selection signal output from the row address decoder XADEC. In the data read operation, the word driver WDRV drives the word line with a voltage such as 5V, and in the data write operation, drives the word line with a high voltage such as 12V. In the data erasing operation, all outputs of the word driver WDRV are set to a low voltage level such as 0V. YADEC is a column address decoder that decodes a column address signal fetched via the address latch YALAT. YSEL is a column address decoder that selects a data line in accordance with the output selection signal of the column address decoder YADEC. SAMP is a sense amplifier that amplifies a read signal from the data line selected by the column selection circuit YSEL in the data read operation. DOLAT is a data output latch that holds the output of the sense amplifier. DOBUFF is a data output buffer for outputting data held by the data output latch DOLAT to the outside. In the figure, PDB0 to PDB7 are lower 8 bits (1 byte) data, and PDB8 to PDB15 are upper 8 bits (1 byte) data. According to this example, the output data is a maximum of 2 bytes. DIBUFF is a data input buffer for taking in write data supplied from the outside. Data taken from the data input buffer DIBUFF is held in the data input latch circuit DILAT. When the data held in the data input latch circuit DILAT is “0”, the write circuit WRIT supplies a high voltage for writing to the data line selected by the column selection circuit YSEL. This high voltage for writing is supplied to the drain of the memory cell to which the high voltage is applied to the control gate in accordance with the row address signal, whereby the memory cell is written. ERASEC is an erasing circuit for supplying a high voltage for erasing to a source line of a specified memory block and performing batch erasing of the memory block.

  The FCONT is a control circuit that performs timing control of a data read operation in the flash memory FMRY, various timings for writing and erasing, and voltage selection control. The control circuit FCONT includes a control register CREG.

  FIG. 19 shows an example of the control register CREG. The control register CREG is composed of an 8-bit program / erase control register PEREG and erase block designation registers MBREG1 and MBREG2. In the program / erase control register PEREG, Vpp is a high voltage application flag that is set to “1” in response to the application of a rewrite high voltage. The E bit is a bit for instructing an erasing operation, and the EV bit is an instructing bit for a verify operation in erasing. The P bit is an instruction bit for a write operation (program operation), and the PV bit is an instruction bit for a verify operation in writing. Erase block designation registers MBREG1 and MBREG2 are registers for designating which memory blocks included in the large block divided into 7 and the small block divided into 8 are erased. For example, bit “1” means selection of the corresponding memory block, and bit “0” means non-selection of the corresponding memory block. For example, when the seventh bit of the erase block designation register MBREG2 is “1”, erase of the small memory block SMB7 is designated.

  The control register CREG can be read / written from the outside. The control circuit FCONT refers to the setting contents of the control register CREG, and performs control such as erasing / writing according to the setting contents. Externally, the state of the erase / write operation can be controlled by rewriting the contents of the control register CREG.

  In FIG. 17, the control circuit FCONT is supplied with FLM, MS-FLN, MS-MISN, M2RDN, M2WRN, MRDN, MWRN, IOWORDN, and RST as control signals, and further, upper one byte data PDB8 to PDB15 The predetermined bits of the address signals PAB0 to PAB15 are given.

  The control signal FLM is a signal that designates the operation mode of the flash memory FMRY, and “0” designates the first operation mode and “1” designates the second operation mode. The signal FLM is formed based on the mode signals MD0 to MD2, for example.

  The control signal MS-FLN is a selection signal for the flash memory FMRY, and “0” indicates selection and “1” indicates non-selection. In the first operation mode, the central processing unit CPU outputs the control signal MS-FLN. In the second operation mode, the control signal MS-FLN corresponds to the chip enable signal CE * supplied from the PROM writer PRW. .

  The control signal MS-MISN is a selection signal for the control register CREG. At this time, which one of the program / erase control register PEREG and the erase block designation registers MBREG1 and MBREG2 is selected is determined with reference to predetermined bits of the address signals PAB0 to PAB15. In the first operation mode, the central processing unit CPU outputs the control signal MS-MISN. In the second operation mode, although not particularly limited, the most significant address bit EA16 output from the PROM writer PRW is regarded as the control signal MS-MISN.

  M2RDN is a memory read strobe signal, M2WRN is a memory write strobe signal, MRDN is a read signal for the control register CREG, and MWRN is a write signal for the control register CREG. In the first operation mode, the central processing unit CPU outputs these control signals. In the second operation mode, although not particularly limited, the write enable signal WE * supplied from the PROM writer PRW is regarded as the signals M2WRN and MWRN, and the output enable signal OE * supplied from the PROM writer is the signal M2RDN, Considered MRDN. The memory write strobe signal M2WRN is regarded as a strobe signal for writing data to be written to the memory cell to the data input latch circuit DILAT. The actual writing to the memory cell is initiated by setting the P bit of the control register CREG.

  IOWORDN is a signal for switching between 8-bit read access and 16-bit read access to the flash memory FMRY. In the second operation mode, the control signal IOWORDN is fixed to a logical value instructing 8-bit read access.

  RST is a reset signal for the flash memory FMRY. When the flash memory FMRY is reset by this signal RST or the Vpp flag of the program / erase control register PEREG is set to “0”, the EV, PV, E, and E in the program / erase control register PEREG are set. Each mode setting bit of P is cleared.

  FIG. 20 shows an example timing chart of the memory read operation in the flash memory FMRY. In the figure, CK1M and CK2M are non-overlapping two-phase clock signals and are regarded as operation reference clock signals. tCYC is the cycle time, which is not much different from the access time to the RAM. The read operation for the control register CREG is also performed at the same timing.

  FIG. 21 shows an example timing chart of the memory write operation in the flash memory FMRY. In the memory write operation indicated by the write strobe signal M2WRN shown in the figure, as described above, the actual writing to the memory cell is not performed, and the input address signals PAB0 to PAB15 are held in the address latch circuit ALAT. The input data PB8 to PB15 are held in the data input latch DILAT, and the write cycle is completed. The write operation to the control register CREG is also performed at the same timing, but in this case, actual data writing to the control register CREG is performed.

[12] Details of Rewrite Control Procedure of Flash Memory FMRY In this item, a detailed example of a control procedure in which the central processing unit CPU or PROM writer writes and erases the flash memory via the control circuit FCONT will be described. Information writing to the flash memory is basically performed on an erased memory cell. In the first operation mode in which the flash memory is rewritten with the microcomputer mounted on the system, the rewrite control program to be executed by the central processing unit CPU includes an erasing program and a writing program. According to the designation of the first operation mode, the rewriting control program can be configured to execute the erasing processing routine first and then automatically execute the writing processing routine. Alternatively, the first operation mode may be designated separately by erasing and writing separately. The rewrite control by the PROM writer is also executed by the same operation as in the first operation mode. Hereinafter, the write control procedure and the erase control procedure will be described.

  FIG. 22 shows a detailed example of the write control procedure. The procedure shown in the figure is a procedure for writing, for example, 1-byte data, and is common to both the control of the central processing unit CPU in the first operation mode and the control of the PROM writer in the second operation mode. Is done. For example, the control main body will be described as a central processing unit CPU.

  In the first step of writing data in byte units, the central processing unit CPU sets 1 to its built-in counter n (step S1). Next, the central processing unit CPU performs the memory write operation described with reference to FIG. 21, sets the data to be written to the flash memory FMRY in the data input latch circuit DILAT of FIG. 17, and sets the address to which the data is to be written. The address latch circuit ALAT is set (step S2). The central processing unit CPU issues a write cycle to the control register CREG and sets the program bit P (step 3). As a result, the control circuit FCONT performs writing by applying a high voltage to the control gate and drain of the memory cell specified by the address based on the data and address set in the step 2. As the write processing time on the flash memory side, the central processing unit CPU waits for 10 μsec, for example (step S4), and then clears the program bit P (step S5).

  Thereafter, the central processing unit CPU issues a write cycle for the control register CREG to set the program verify bit PV in order to confirm the write state (step 6). As a result, the control circuit FCONT uses the address set in step 2 to apply a verify voltage to the word line to be selected by the address, and reads the data of the memory cell that has been written. . Here, the verify voltage is set to a voltage level such as 7V, which is higher than the power supply voltage Vcc, such as 5V, in order to guarantee a sufficient write level. The central processing unit CPU confirms the coincidence between the data read out and the data used for writing (step S7). When the central processing unit CPU confirms the coincidence by the verify, it clears the program verify bit PV (step S8), thereby completing the writing of the 1-byte data.

  On the other hand, when the central processing unit CPU confirms the mismatch by the verify in step S7, after clearing the program verify bit PV in step S9, the central processing unit CPU determines whether or not the value of the counter n has reached the write retry upper limit number N. It performs (step S10). As a result, when the write retry upper limit number N has been reached, the processing is terminated as a write failure. If the write retry upper limit number N has not been reached, the central processing unit CPU increments the value of the counter n by 1 (step S11), and repeats the processing from step S3.

  FIG. 23 shows a detailed example of the erase control procedure. The procedure shown in the figure is common to both the control of the central processing unit CPU in the first operation mode and the control of the PROM writer in the second operation mode. For example, the control main body will be described as a central processing unit CPU.

  The central processing unit CPU sets 1 to its built-in counter n for erasing (step S21). Next, the central processing unit CPU pre-writes the memory cells in the erase target area (step S22). That is, data “0” is written to the memory cell at the address to be erased. As the prewrite control procedure, the write control procedure described with reference to FIG. 22 can be used. This pre-write process is performed in order to make the charge amount in the floating gate before erasure uniform for all bits and to make the erase state uniform.

  Next, the central processing unit CPU issues a write cycle to the control register CREG and designates a batch erase target memory block (step S23). That is, the erase target memory block number is designated in the erase block designation registers MBREG1 and MBREG2. After designating the memory block to be erased, the central processing unit CPU issues a write cycle to the control register CREG and sets the erase bit E (step 24). As a result, the control circuit FCONT applies a high voltage to the source line of the memory block specified in step 23 to erase the memory block at once. The central processing unit CPU waits for 10 msec, for example, as the batch erasure processing time on the flash memory side (step S25). The time of 10 msec is shorter than the time required to complete the erase operation once. Then, erase bit E is cleared (step S26).

  Thereafter, in order to confirm the erase state, the central processing unit CPU first sets the beginning address of the batch erase target memory block as an address to be verified (step S27), and then performs a dummy write to the verify address (step S27). S28). That is, a memory write cycle is issued for the address to be verified. As a result, the memory address to be verified is held in the address latch circuit ALAT. Thereafter, the central processing unit CPU issues a write cycle to the control register CREG and sets the erase verify bit EV (step 29). As a result, the control circuit FCONT uses the address set in step S28 to apply the erase verify voltage to the word line to be selected by the address, and reads the data of the erased memory cell. . Here, the erase verify voltage is set to a voltage level such as 3.5 V, which is lower than the power supply voltage Vcc, such as 5 V, for example, in order to guarantee a sufficient erase level. The central processing unit CPU verifies whether or not the data read by the central processing unit CPU matches the data in the erase complete state (step S30). When the central processing unit CPU confirms the coincidence by verify, the erase verify bit EV is cleared (step S31), and then it is determined whether or not the current verify address is the final address of the erased memory block (step S32). If it is an address, a series of erase operations is terminated. If it is determined that the final address has not been reached, the verify address is incremented by 1 (step S33), and the processing from step S29 is repeated again.

  On the other hand, when the central processing unit CPU confirms the mismatch by the verification in step S30, after clearing the erase verification bit EV in step S34, the central processing unit CPU determines whether or not the value of the counter n has reached the gradual deletion upper limit number N. This is performed (step S35). As a result, if the erasure upper limit number N is reached, the process ends as an erasure failure. If the gradual erasure upper limit number N has not been reached, the central processing unit CPU increments the value of the counter n by 1 (step S36), and repeats the processing from step S24. Actually, in order to prevent over-erasure that the threshold voltage of the memory cell becomes a negative value due to over-erasing, gradually verifying is performed every time, such as 10 msec. Erasing is repeated.

  According to the said Example, there exist the following effects.

  (1) When information is first written in the flash memory FMRY built in the microcomputer MCU at a stage before the microcomputer MCU is mounted on a required system, the second operation mode is designated by Information can be efficiently written by controlling an external writing device such as a PROM writer PRW. Further, by designating the first operation mode to the microcomputer MCU, the storage information of the flash memory FMRY can be rewritten in a state where the microcomputer MCU is mounted on the system. At this time, the rewrite time can be shortened by the batch erasing function.

  (2) By providing a plurality of memory blocks (LMB, SMB) having different storage capacities as a unit that can be erased at once in the flash memory FMRY, each memory block has a corresponding memory capacity. For example, programs, data tables, control data, etc. can be held. That is, data having a relatively large information amount can be written in a memory block having a relatively large storage capacity, and data having a relatively small information amount can be written in a memory block having a relatively small storage capacity. In other words, a memory block having a storage capacity corresponding to the amount of information to be stored can be used. Therefore, it is possible to prevent a situation where the erasing unit is too large for the program area but is difficult to use. In addition, even if a required memory block is erased at once for partial rewriting of information held in the flash memory, information that does not substantially need to be rewritten is erased together and then rewritten again. It can be prevented as much as possible.

  (3) By providing a memory block set below the storage capacity of the built-in RAM among the plurality of memory blocks, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory block. .

  (4) In the above (3), when the flash memory is rewritten in the mounted state of the microcomputer, the information of the memory block to be rewritten is transferred to the built-in RAM, and only a part of the information to be rewritten is received from the outside and stored in the RAM. By rewriting the flash memory after rewriting with, it is not necessary to superimpose the information that does not need to be rewritten inside before rewriting and to transfer it from the outside. Therefore, it is possible to eliminate waste of information transfer.

  (5) Since the batch erase time of the flash memory is not so short even for a small memory block, the flash memory itself cannot be rewritten in real time in synchronization with the control operation by the microcomputer MCU. By using it as a work area or data buffer area for block rewriting, the same data as that rewritten in real time can be obtained in the memory block as a result.

  (6) A register MBREG for holding rewritable memory block designation information in the batch memory is built in the flash memory FMRY so that the memory block to be erased in batches is located inside and outside the microcomputer MCU (built-in central processing unit, It can be easily specified in the same procedure from an external PROM writer.

  (7) The usability of the flash memory FMRY built in the microcomputer MCU can be improved by the above-described effects.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the peripheral circuit built in the microcomputer is not limited to the above embodiment, and can be changed as appropriate. The memory cell transistor of the flash memory is not limited to the stacked gate structure MOS transistor of the above embodiment, and a FLOTOX type memory cell transistor using a tunnel phenomenon can also be used for the write operation. In the above embodiment, control of both erasing and writing to the flash memory is realized via software means as shown in FIGS. 22 and 23. However, the present invention is not limited to this, and for example, The batch erasure that takes a relatively long time may be controlled by dedicated hardware in the flash memory. For example, the dedicated hardware is provided with control logic for setting and clearing the E bit and the EV bit and verifying the erased state. The configuration in which the batch erase control logic is built in the flash memory improves the usability for the user in that the software burden on the batch erase is reduced, but the control logic increases the area. In addition to the memory block that uses the same source line as the unit for batch erase, it is possible to use a memory block that can share the word line for erasing. Which one is selected depends on the polarity of the erase voltage. Or, when trying to reduce the storage capacity of the batch erase unit as much as possible, whichever is the number of memory cells connected to a single word line or the number of memory cells connected to a single data line It can be decided in consideration of the circumstances such as few. The size of the memory block is not limited to the fixed size as in the above embodiment. For example, the size can be made variable according to the setting of the control register or the instruction of the mode signal. For example, when a batch erase voltage is applied with the word line as the minimum unit, the operation of the driver that drives the word line with the erase voltage may be selected according to the setting of the control register or the instruction of the mode signal. Further, as shown in FIG. 24, the memory block is divided into a plurality of large blocks LMB0 to LMB7, and each large block is further divided into a plurality of small blocks SMB0 to SMB7. It is also possible to enable batch erasure in units of large blocks or small blocks. In some memory cell transistors of a flash memory, the source and drain are grasped as relative ones determined by an applied voltage.

  The present invention can be widely applied to microcomputers having conditions that include a central processing unit and a nonvolatile flash memory that can be rewritten by electrical erasing and writing on at least a single semiconductor chip.

FIG. 1 is a block diagram showing an embodiment of a microcomputer adopting a full flash memory. FIG. 2 is a block diagram of an embodiment of a microcomputer adopting a mask ROM together with a flash memory. FIG. 3 is a block diagram focusing on the rewriting of the flash memory by the general-purpose PROM writer. FIG. 4 is a block diagram focusing on rewriting of flash memory under CPU control. FIG. 5 is an example memory map of a microcomputer that is a full-scale flash memory. FIG. 6 is an example memory map of a microcomputer having a mask ROM together with a flash memory. FIG. 7 is a diagram for explaining an example of a schematic control procedure for erasure. FIG. 8 is an explanatory diagram of a schematic example of the control procedure for writing. FIG. 9 is an explanatory diagram showing an example of a technique for dealing with real-time rewriting of a flash memory. FIG. 10 is an explanatory diagram showing an example of a technique for improving the efficiency of partial rewriting of the memory block of the flash memory. FIG. 11 is an explanatory diagram of the principle of the flash memory. FIG. 12 is an explanatory diagram of a configuration principle of a memory cell array using the memory transistor of FIG. FIG. 13 is an explanatory diagram showing an example of voltage conditions for the erase operation and the write operation for the memory cell. FIG. 14 is a circuit block diagram showing an example of a flash memory in which the memory capacity of the batch-erasable memory block is different. FIG. 15 is a block diagram showing a more detailed microcomputer corresponding to the microcomputer shown in FIG. FIG. 16 is a plan view showing a state in which the microcomputer of FIG. 15 is packaged. FIG. 17 is an overall block diagram of a flash memory built in the microcomputer of FIG. FIG. 18 is an explanatory diagram of an example of a division mode of the memory block. FIG. 19 is an explanatory diagram of an example of the control register. FIG. 20 is a timing chart showing an example of a memory read operation in the flash memory. FIG. 21 is an example timing chart of the memory write operation in the flash memory. FIG. 22 is a flowchart showing a detailed example of the write control procedure. FIG. 23 is a flowchart showing a detailed example of the erase control procedure. FIG. 24 is an explanatory diagram showing another example of the memory block division mode.

Explanation of symbols

MCU Microcomputer CHP Semiconductor chip FMRY Flash memory LNB Large memory block SMB Small memory block CPU Central processing unit RAM Random access memory CONT Control circuit MASKROM Mask read only memory MODE mode signal Pmode mode signal input terminal MD0 to MD2 mode Signal PORTdata port PORTaddr port PORTcont port socket Socket PRW General-purpose PROM writer ABUS Address bus DBUS Data bus 5 Floating gate 7 Control gate 9 Source 10 Drain ARY1 to ARY7 Memory array MC Memory cell WL0 to WLn Word line DL0 to DL7 Data line Source line B1, B Bits of erasing block designation register PORT1 to PORT12 Ports ED0 to ED7 Input / output data with PROM writer EA0 to EA16 Input address signal from PROM writer CE * Chip enable signal OE * Output enable signal WE * Write enable signal FCONT control circuit CREG Control register NBREG Erase block designation register PEREG Program / erase control register E Erase bit EV Erase verify bit P Program bit PE Program verify bit ERASEC Erase circuit LMB0 to LMB6 Large memory block SMB0 to SMB7 Small memory block

Claims (5)

  A CPU, an I / O port, a random access memory, and a flash memory are sealed in one resin package, and the flash memory is divided into a plurality of storage areas to be collectively erased and is outside the resin package. A first mode in which a program is written to the flash memory by a PROM writer; and a second mode in which the central processing unit rewrites data stored in the random access memory into the flash memory by executing a rewrite control program. The central processing unit and the random access memory are set in a low power consumption mode in response to the designation of the first mode,
  The flash memory has a rewrite control program written by a PROM writer in the first mode,
  In the second mode, the CPU executes a transfer control program written in the flash memory in advance, and the rewrite control program written in the flash memory by the PROM writer is transferred from the flash memory to the random access memory. By transferring and rewriting the transferred rewrite control program from the random access memory and executing it, a predetermined storage area to be collectively erased from the flash memory can be stored with the data stored in the random access memory. An information processing device that can be rewritten.   The information processing apparatus according to claim 1, wherein the data stored in the random access memory is data that has been tuned by operating the information processing apparatus.   The plurality of batch erasable storage areas include a storage area having a large storage capacity and a storage area having a small storage capacity, and the predetermined storage area to be subjected to the batch erasure that is rewritten with the tuned data 3. The information processing apparatus according to claim 2, wherein is a storage area having a small storage capacity.   4. The I / O port according to claim 1, wherein the I / O port is interfaced with the external PROM writer in the first mode and can input / output data to / from the flash memory. The information processing apparatus according to item.   5. The information processing apparatus according to claim 1, wherein the first mode and the second mode can be selectively designated by an operation mode signal given to a mode signal input terminal. 6.

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