JP3534781B2 - Microcomputer and flash memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile flash memory in which information can be rewritten by electrically erasing / writing, and a microcomputer incorporating the same.

[0002]

2. Description of the Related Art JP-A-1-161469 discloses an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) as a programmable nonvolatile memory. -A memory) is mounted on a single semiconductor chip. Programs and data are held in a non-volatile memory which is on-chip in such a microcomputer. Since the EPROM erases stored information by ultraviolet rays, rewriting cannot be performed without removing it from the mounting system. Since the EEPROM can be electrically erased and written, its stored information can be rewritten in the state where it is mounted in the system. However, the memory cell constituting the EEPROM is MNOS (metal nitride oxide Since a selection transistor is required in addition to a memory element such as a semiconductor), the number of transistors is 2.
It is about 5 to 5 times larger, and requires a relatively large chip occupation area.

Japanese Unexamined Patent Publication No. 2-289997 discloses a batch erase type EEPROM. This collective erasing type EEPROM can be understood in the same meaning as the flash memory in this specification. A flash memory can rewrite information by electrical erasing / writing, and like the EPROM, its memory cell can be configured by one transistor, and all the memory cells can be collectively or It has a function to electrically erase all blocks. Therefore, the flash memory can rewrite the stored information in the state where it is mounted in the system, and the batch erasing function can shorten the rewriting time, and further contributes to the reduction of the chip occupying area. To do.

In US Pat. No. 5,065,365, an array of electrically erasable / rewritable memory cells having a control gate, a drain and a source is divided into a plurality of memory blocks in units of data lines, and each block is divided into blocks. A flash memory is shown in which a common source line is drawn out and a source switch provided for each source line individually applies a voltage according to the operation to the source line. At this time, the ground potential is applied to the source line of the write selection block. A voltage VDI such as 3.5V is applied to the source line of the write non-selected block. This voltage V
Measure the word line disturb by DI. Here, the word line disturb is, for example, in a memory cell in which the word line is selected and the data line is deselected during writing, the potential difference between the control gate and the floating gate increases, and the charge is floating gate. Is a phenomenon in which the threshold voltage of the memory cell transistor is lowered by being discharged from the control gate to the control gate.

[0005]

DISCLOSURE OF THE INVENTION The present inventor first studied mounting a flash memory in a microcomputer, and found out the following points. (1) Programs and data are stored in the built-in ROM of the microcomputer. Further, the data includes large capacity data and small capacity data. When rewriting these programs and data, the former is usually rewritten in a large unit of tens of KB (kilobytes) and the latter is rewritten in a small unit of tens of B (bytes). At this time, if the erase unit of the flash memory is a batch of chips or a unit of memory blocks of the same size, it is suitable for the program area, but the erase unit is too large for the data area, which is difficult to use, or vice versa. Cases can happen. (2) When a part of the information held in the flash memory is rewritten after the microcomputer is installed in the system, a part of the memory blocks holding the information may be rewritten. If the memory capacity of erasable memory blocks is the same for all memory blocks, the memory block with a relatively large memory capacity can be used even if only the information with less information capacity than the memory block needs to be rewritten. Must be sequentially erased after all data is erased in a batch, and a wasteful time is spent in rewriting information that does not substantially require rewriting. (3) The information to be written in the flash memory is determined according to the system to which the microcomputer is applied, but it is inefficient to write all the information from the beginning with the microcomputer mounted in the system. There is a case. (4) When the flash memory is rewritten in the state where the microcomputer is mounted, all the information to be written to the entire memory block after batch erasing, even if only a part of the information in the rewriting target memory block needs to be rewritten Since the data is written while being sequentially received from the outside of the microcomputer, even if only a part of the information in the memory block to be rewritten needs to be rewritten, all the information to be written in the entire memory block is received from the outside. Must be
Information that does not substantially require rewriting, that is, information that is internally held before rewriting must also be transferred from the outside, and there is a waste of information transfer for partially rewriting a memory block. (5) Since the time required to rewrite the flash memory by batch erasing is considerably longer than the memory such as RAM (random access memory) because of its information storage format, the flash memory is real-time synchronized with the device control operation by the microcomputer. Cannot be rewritten.

Further, the present inventor has found that US Pat.
As a result of examining memory block division in units of data lines as described in No. 5, it is preferable to divide the memory blocks in units of word lines so that the source in the block is shared. It has been found that this is advantageous also in terms of improving the usability of the flash memory with a built-in microcomputer, which was first examined. Further, when the memory block division in which the data line is a unit is adopted, the data line disturb is applied to all the memory cells in one column whose drain is connected to the data line to which the write high voltage is applied in the write select block. Occurs. The data line disturb is, for example, in a memory cell in which the word line is not selected and the data line is selected in writing, the electric field between the source and the drain becomes large, which causes hot holes to be injected from the drain to the floating gate, This is a phenomenon in which the threshold value of the cell transistor is lowered.

An object of the present invention is to provide a microcomputer incorporating a flash memory which is easy to use. More specifically, the first object of the present invention is to provide a microcomputer capable of increasing the efficiency of the first information writing process performed on the built-in flash memory. A second object of the present invention is to improve the rewriting efficiency by eliminating the waste of the write operation after collectively erasing the memory block for rewriting a part of the information held by a part of the memory block of the flash memory. It is to improve. The third object of the present invention is to
This is to improve the rewriting efficiency by eliminating the waste of the transfer operation of the write information from the outside necessary for rewriting a part of the memory block. A fourth object of the present invention is to enable the information held in the flash memory to be changed in real time in synchronization with the control operation of the microcomputer.

A further object of the present invention is to provide a flash memory which can reduce the minimum size of a memory block which is formed by sharing a source of an electrically rewritable nonvolatile memory element. Still another object is to prevent the occurrence of malfunction due to the data line disturb in the write unselected memory block when the memory block is formed in word line units.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a microcomputer provided with a central processing unit and a non-volatile flash memory capable of rewriting information to be processed by the central processing unit by electric erasing / writing on a single semiconductor chip. On the other hand, a first circuit for controlling rewriting of the flash memory by a built-in circuit of the semiconductor chip, for example, a central processing unit
An operation mode signal input terminal for selectively designating an operation mode and a second operation mode to be controlled by an external device of the semiconductor chip is provided.

When the central processing unit performs the rewriting control according to the designation of the first operation mode, the rewriting control program to be executed by the central processing unit is stored in the mask ROM or stored in the flash memory in advance. The stored rewrite control program can be transferred to the RAM and executed.

Considering that the amount of information to be stored in the flash memory differs depending on the type of the information, such as a program, a data table, and control data, depending on the application, a partial memory block of the flash memory. In order to improve the rewriting efficiency by eliminating the waste of the write operation after collectively erasing the memory block for rewriting a part of the information held by the flash memory, it is necessary to set a unit that can be collectively erased in the flash memory as a mutual erasable unit. It is preferable to allocate a plurality of memory blocks having different storage capacities.

In order to easily specify the memory blocks to be collectively erased when controlling the rewriting of the flash memory from inside and outside the microcomputer, the designation information of the memory blocks to be collectively erased is rewritably held. It is advisable to incorporate a register for this in the flash memory.

When the built-in flash memory has a plurality of memory blocks having mutually different storage capacities as a batch erasable unit, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory blocks. In order to do so, it is preferable to provide a memory block whose storage capacity is less than or equal to that of the built-in RAM. At this time,
In order to eliminate the waste of the transfer operation of the write information from the outside necessary for rewriting a part of the memory block and improve the rewriting efficiency, the information held in the memory block having a smaller storage capacity than the internal RAM is stored in the internal RAM. And update all or part of the transferred information on the RAM,
The memory block may be rewritten with the updated information. In addition, when tuning the control data etc. held in the flash memory, in order to be able to change the holding information of the flash memory in real time in synchronization with the control operation of the microcomputer, the area of the specific address of the internal RAM should be changed. , The layout is changed so that it overlaps with the address of a memory block whose storage capacity is smaller than that of the built-in RAM, that is, the layout is changed so that when the memory block is accessed, the overlapped RAM is accessed, and work is performed at a specific address of that RAM After doing R
It is preferable that the arrangement address of the AM is restored to the original state, and the content of the memory block is rewritten with the information of the specific address of the RAM.

In order to make it possible to easily reduce the minimum block size as compared with the case of forming a memory block in units of data lines, a memory cell in which a control gate is coupled to one or more word lines in units of word lines is used. A common source line is connected to define a memory block.

At this time, in order to prevent the data line disturbance in the write-unselected memory block, during the write operation, the potential of the source line is set to the first potential in the memory block unit and the second potential having a higher level than the first potential. The potential is controllable, a predetermined potential is applied to the data line and the word line, and a first potential is applied to the source line of the memory block including the memory cell to be selected for writing. Voltage is applied to the word line and the word line is not applied with the predetermined voltage, and the source line of the memory block including the memory cell to be unselected for writing is provided with the voltage output means for applying the second potential.

In order to improve the usability of a memory block having word lines as a unit, one or a plurality of large memory blocks having a relatively large number of word lines and a relatively small number of word lines are provided. A plurality of memory blocks are configured to include both a single memory block or a plurality of small memory blocks.

At this time, in order to shorten the data line disturb time as much as possible, the large memory block and the small memory block are shared by arranging them separately before and after the data line is shared, and the data line is selected during the write and read operations. A selection circuit for performing the operation is arranged near the large memory block, a transfer gate circuit is arranged between the data lines shared by the large memory block and the small memory block, and the transfer gate circuit is cut when writing to the large memory block.・ Provide a control circuit to turn off.

[0020]

According to the above-mentioned means, when information is first written in the flash memory at a stage before mounting the microcomputer according to the present invention in the system, the second operation mode is designated. , Information is efficiently written by the control of an external writing device such as a PROM writer.

As a batch erasable unit in the flash memory, programs, data tables, control data, etc. are written in a plurality of memory blocks having mutually different storage capacities according to their respective storage capacities.

When the flash memory is rewritten after the microcomputer is mounted on the system, the rewriting control is executed by the central processing unit or the like having the microcomputer by designating the first operation mode. At this time, data having a relatively large amount of information can be written in a memory block having a relatively large storage capacity, and data having a relatively small amount of information can be written in a memory block having a relatively small storage capacity. That is, it is possible to use a memory block having a storage capacity commensurate with the amount of information to be stored. Therefore, even if a required memory block is collectively erased in order to partially rewrite the retained information in the flash memory, there is no waste of rewriting again after erasing the information group that does not substantially require rewriting. It is prevented as much as possible.

In particular, by providing a memory block of the plurality of memory blocks whose storage capacity is less than or equal to the storage capacity of the built-in RAM, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory block. To do. That is, when the flash memory is rewritten in the state where the microcomputer is mounted, the information of the rewriting target memory block is transferred to the built-in RAM, only a part of the information to be rewritten is received from the outside, and rewriting is performed on the RAM. When the flash memory is rewritten, it is not necessary to overlap the information that is internally stored before the rewriting and does not have to be transferred from the outside, and waste of information transfer for rewriting a part of the memory block can be omitted. . Also, the batch erase time of the flash memory does not become so short even for small memory blocks, so it is not possible to rewrite the flash memory itself in real time in synchronization with the control operation by the microcomputer, but rewriting the internal RAM to the memory block. By using it as a work area or a data buffer area for, the same data as the data rewritten in real time can be obtained in the memory block as a result.

When a memory block is defined in units of word lines, the storage capacity of the minimum memory block is the storage capacity of one word line, regardless of the number of parallel input / output bits. On the other hand, when defining a memory block in units of data lines, the minimum memory block is
The storage capacity corresponds to the number of data lines corresponding to the number of parallel input / output bits. This means that it is easier to reduce the storage capacity of the minimum memory block by defining the memory block in units of word lines. In the case of a memory that outputs data, the minimum size of the memory block is significantly reduced. This contributes to further improvement of usability of a flash memory incorporated in a microcomputer and further improvement of rewriting efficiency of small-scale data in memory block units.

In the region near the drain end of the non-volatile memory element, electron-hole pairs are generated due to the tunnel phenomenon between bands. At this time, if a relatively large electric field is generated between the source and drain,
The holes in the hole pair are accelerated by the electric field to become hot holes. The hot holes are injected into the floating gate through the tunnel insulating film of the nonvolatile memory element.
This state is the state of the data line disturb, and if the time for receiving the data line disturb becomes long, the threshold value of the storage element decreases, causing an undesired change in the stored information and a malfunction (data line disturb failure). Cause In the write non-selected block, if the source potential of the memory cell is given a second potential such as the data line disturb blocking voltage to raise the source potential, the electric field between the drain and the source is weakened, which causes the generation near the drain. It is prevented that the holes of the electron-hole pairs that are operating become hot holes, and the threshold value of the memory cell transistor is prevented from decreasing.

In order to prevent the data line disturb defect, it is effective to shorten the data line disturb time (time to be exposed to the data line disturb state) as much as possible.
At this time, the data line disturb time received by the small memory block due to the writing accompanying the rewriting of the memory block having the large storage capacity becomes relatively long as compared with the opposite case. Focusing on this, using the arrangement in which the memory block on the side of the Y selection circuit is a large memory block and the memory block on the opposite side is a small memory block across the transfer gate circuit is relatively different from the Y selection circuit. The data line disturb time received by the memory cells of the memory block relatively close to the Y selection circuit due to the writing of the distant memory block is significantly larger than that in the case where the arrangement of the large memory block and the small memory block is reversed. Shorten to Such an arrangement relationship between the large memory block and the small memory block makes the prevention of malfunction due to the data line disturb more complete.

[0027]

EXAMPLES Examples of the present invention will be sequentially described according to the following items. [1] Microcomputer adopting full-scale flash memory [2] Mask ROM, microcomputer adopting flash memory [3] Writing information by general-purpose PROM writer [4] Writing control program by CPU control [5] Writing by general-purpose PROM writer and CPU Use of control writing [6] Real-time rewriting [7] Efficient partial rewriting of memory block [8] Principle of flash memory

[9] Multiple memory blocks with different storage capacities in units of data lines [10] Details of microcomputer corresponding to FIG. 1 [11] Control circuit for rewriting flash memory FMRY [12] Rewriting flash memory FMRY Details of control procedure [13] Multiple memory blocks with different storage capacities on a word line basis [14] Countermeasures for data line disturb for write unselected blocks [15] Correlation of data line disturb time between memory blocks [16] ] Transfer gate circuit for data line separation [17] Dummy word line [18] Various modes of pluralization of memory block in word line unit [19] Layout configuration of memory block [20] Flash memory with countermeasure against data line disturbance [21] Manufacture of flash memory Law [22] the structure of the semiconductor substrate / well, corresponding to the sector erase

[1] Microcomputer adopting full-face flash memory

FIG. 1 shows a block diagram of an embodiment of a microcomputer adopting a full-face flash memory. The microcomputer MCU shown in the figure includes a central processing unit CPU, a non-volatile flash memory FMRY capable of rewriting information to be processed by the central processing unit CPU by electrical erasing / writing, a timer TMR, a serial memory. Communication interface SCI, random access memory RAM, other peripheral circuits such as input / output circuit I / O, and control circuit C
The ONT is formed on a single semiconductor chip CHP such as silicon by a known semiconductor integrated circuit manufacturing technique. The flash memory FMRY can rewrite information by electrical erasing / writing and
Like the OM, the memory cell can be composed of one transistor, and further, all the memory cells can be collectively formed,
Alternatively, it has a function of electrically erasing a block of memory cells (memory block) collectively. Flash memory F
The MRY has a plurality of memory blocks as a batch erasable unit. In FIG. 1, LMB is a large memory block having a relatively large storage capacity, and SMB is a small memory block having a relatively small storage capacity. The storage capacity of the small memory block SMB is made smaller than that of the random access memory RAM. Therefore,
The random access memory RAM can receive data transferred from the small memory block SMB and temporarily hold the information, and can be used as a work area for rewriting or a data buffer area. Required data and programs are written in this flash memory FMRY. The details of the flash memory FMRY will be described later.

The flash memory FMRY has its stored information rewritable under the control of the central processing unit CPU in a state where the microcomputer MCU is mounted in the system. The stored information can be rewritten based on the control of the external device. In the figure, MODE is an operation mode signal for selectively designating a first operation mode in which the central processing unit CPU controls rewriting of the flash memory FMRY and a second operation mode in which the external device is controlled. It is given to the mode signal input terminal Pmode on the CHP.

[2] Microcomputer employing mask ROM and flash memory

In FIG. 2, the mask R is shown together with the flash memory.
A block diagram of an embodiment of a microcomputer adopting an OM is shown. In the microcomputer MCU shown in the figure, a part of the flash memory FMRY of FIG. 1 is a mask read only memory MASKROM.
Has been replaced by. The mask read only memory MASKROM holds data and programs that do not require rewriting. Flash memory F shown in FIG.
The MRY has a plurality of the small memory blocks SMB as a batch erasable unit.

[3] Information writing by general-purpose PROM writer

FIG. 3 shows a block diagram focusing on rewriting of the flash memory FMRY by a general-purpose PROM writer. In the figure, MD0, MD1 and MD2 are shown as an example of the mode signal MODE. Mode signal MD1
Through MD3 are supplied to the control circuit CONT. The decoder included in the control circuit CONT is not particularly limited, but it decodes the mode signals MD1 to MD3 to instruct the flash memory FMRY to be in an operation mode that does not require writing, or the first operation mode or the first operation mode. 2 It is determined whether the operation mode is instructed. At this time, if the instruction of the second operation mode is determined, the control circuit CO
The NT specifies an I / O port to be interfaced with the general-purpose PROM writer PRW, and controls the built-in flash memory FMRY so that the external general-purpose PROM writer PRW can directly access it. That is, the flash memory F
I / O port PORTdata for inputting / outputting data to / from MRY and I / O port PORTad for supplying an address signal to the flash memory FMRY
dr and an I / O port PORTcont for supplying various control signals to the flash memory FMRY are designated. Further, the substantial operation of the built-in functional blocks such as the central processing unit CPU, the random access memory RAM, the mask read only memory MASKROM which are not directly related to the rewriting control by the general-purpose PRO writer PRW is suppressed. For example, as shown in FIG. 3 by way of example, the connection between the built-in functional block such as the central processing unit CPU and the flash memory FMRY is disconnected via the switch means SWITCH arranged on each of the data bus DBUS and the address bus ABUS. Let go. The switch means SWI
The TCH should be understood as a tri-state (3 state) type output circuit arranged in a circuit that outputs data from a built-in functional block such as the CPU to the data bus DBUS or a circuit that outputs an address to the address bus ABUS. You can also Such a tri-state output circuit is controlled to a high output impedance state in response to the second operation mode. In the example of FIG. 3, the built-in functional blocks such as the central processing unit CPU, the random access memory RAM, the mask read only memory MASKROM which are not directly related to the rewriting control by the general-purpose PRO writer,
The low power consumption mode is set by the standby signal STBY * (the symbol * means that the signal to which it is attached is a low active signal). If the tri-state output circuit is controlled to a high output impedance state in the low power consumption mode, the mode signals MD0 to MD are used.
In response to the designation of the second operation mode by D2, the low power consumption mode is set in those functional blocks, and the general-purpose PRO
CP not directly related to rewriting control by writer PRW
Substantial operations of built-in functional blocks such as U, RAM, and ROM may be suppressed.

The I / O port PORTdata of the microcomputer MCU in which the second operation mode is set,
PORTaddr and PORTcont are conversion sockets S
It is coupled to the general-purpose PROM writer PRW via OCKET. The conversion socket SOCKET has an I / O
O port PORTdata, PORTaddr, POR
It has a terminal arrangement of Tcont and a terminal arrangement of a standard memory on the other hand, and terminals having the same function are internally connected to each other.

[4] CPU-controlled write control program

FIG. 4 shows a block diagram focusing on rewriting of the flash memory FMRY under CPU control.
The rewrite control program to be executed by the central processing unit CPU in the microcomputer MCU of FIG. 1 is written in the flash memory FMRY by the general-purpose PROM writer PRW in advance. The microcomputer MCU of FIG.
Then, the rewrite control program to be executed by the central processing unit CPU is defined as a mask read only memory MASKRO.
It can be held in M. The mode signal MD
The first operation mode is instructed by 0 to MD2, and the control circuit CONT recognizes the first operation mode, whereby the central processing unit CPU causes the central processing unit CPU to write the write control program or the mask read only memory. Data is written in the flash memory FMRY according to the rewrite control program held by MASKROM.

FIG. 5 shows a memory map of a microcomputer (see FIG. 1) which is a full flash memory. In the figure, a rewrite control program and a transfer control program are written in advance in a predetermined area of the flash memory. When the first operation mode is instructed, the central processing unit CPU executes the transfer control program to execute the rewrite control program in the random access memory RAM.
Transfer to. After the transfer is completed, the processing of the central processing unit CPU is branched to the execution of the rewrite control program on the random access memory RAM, whereby erasing and writing (including verify) to the flash memory FMRY are repeated.

FIG. 6 shows a mask R together with a flash memory.
A memory map of a microcomputer having an OM (see FIG. 2) is shown. In this case, the transfer control program as described in FIG. 5 is unnecessary. Central processing unit C
When the PU is instructed to the first operation mode, the PU sequentially executes the rewrite control program held in the mask read only memory MASKROM, whereby erasing and writing to the flash memory FMRY are repeated.

FIG. 7 shows an example control procedure of erasing by the central processing unit CPU. First, the central processing unit CPU
According to the rewrite control program, prewriting is performed on the memory cells in the address range to be erased. As a result, all the states of the memory cells before erasing are brought to the written state. Next, while erasing the memory cells to be erased little by little, the degree of erasing is verified (erasing / verifying) each time, and overerasing is prevented to complete the erasing operation. General-purpose PROM writer PRW
The erasure by is similarly performed. The erase sequence of the flash memory will be described in detail later.

FIG. 8 shows an example control procedure of writing by the central processing unit CPU. First, the central processing unit CPU
Sets the write start address of the flash memory FMRY. Next, the data sent from the outside is read through the peripheral circuit designated by the rewrite control program, for example, the serial communication interface SCI or the I / O port. The data thus read is written to the flash memory FMRY for a predetermined time, and the written data is read to verify whether it was written normally (write / verify). Thereafter, reading, writing, and verification of the above data are repeated until the write end address. Writing by the general-purpose PROM writer PRW is similarly performed. However, in this case, the data to be written is given from the PROM writer PRW through a predetermined port. The write sequence of the flash memory will be described in detail later.

[5] Use of writing by general-purpose PROM writer and writing by CPU control

The writing by the general-purpose PROM writer is mainly applied to writing the initial data or the initial program before the microcomputer MCU is on-board, that is, before the microcomputer MCU is mounted in the system.
This allows a relatively large amount of information to be written efficiently.

CPU-controlled writing is performed by a system in which a microcomputer MCU is mounted (also called a mounting machine).
When tuning data while operating, or when the program MCU is installed in the system (on-board state), such as program bug countermeasures or program changes due to system version upgrades, data and program changes Applies when is needed. This enables the microcomputer MCU
The flash memory FMRY can be rewritten without removing it from the mounting system.

[6] Support for real-time rewriting

FIG. 9 shows an example of a method for dealing with real-time rewriting of the flash memory. Due to the storage format of the flash memory FMRY, the time required for erasing is not shortened even if the storage capacity of the memory block as a batch erasing unit is reduced, for example, several tens of milliseconds to several seconds. This allows the flash memory FM to operate while operating the system in which the microcomputer MCU is mounted.
It is difficult to tune the data by rewriting the control data held by RY in real time. In order to deal with this, the built-in RAM is used as a work area or a data buffer area for rewriting a memory block. That is, first, the data of a predetermined small memory block SMB holding the data to be tuned is transferred to a specific address of the random access memory RAM. Next, the specific address area of the random access memory RAM is overlapped with the address of a predetermined small memory block SMB. Such an address arrangement change can be realized by making the decoding logic of the random access memory RAM switchable in response to the setting of a predetermined control bit or flag. And tuning of control data etc.
This is performed by using a random access memory RAM in which addresses of a predetermined memory block SMB are overlapped. After the tuning is completed, the address overlap between the random access memory RAM and the memory block SMB is released, and the arrangement address of the random access memory RAM is restored to the original state. Finally, the tuned data held in the random access memory RAM is used to rewrite the memory block SMB of the flash memory. As a result, while operating the system in which the microcomputer MCU is mounted, the same data as that obtained by rewriting the control data held by the flash memory in real time can be obtained in the memory block SMB as a result.

[7] Efficiency of partial rewriting of memory block

FIG. 10 shows an example of a method for efficiently rewriting a part of the memory block of the flash memory.
When a part of the information held in the predetermined memory block SMB of the flash memory FMRY is rewritten when a program bug is corrected or the version is updated, the information held in the memory block SMB having a smaller storage capacity than the RAM is built in. The data is transferred to the RAM, a part of the transferred information is updated on the RAM, and the memory block is rewritten with the updated information. As a result, even if one of the memory blocks SMB is erased at once,
Since the retained information of the memory block SMB is stored in the RAM, if only the data to be rewritten is received from the outside and rewritten in the RAM, the rewriting held in the flash memory FMRY before the rewriting is not necessary. It is not necessary to overlap information and receive it from the outside, and waste of information transfer for rewriting a part of the memory block can be omitted.

[8] Principle of flash memory

FIG. 11 shows the principle of the flash memory. The memory cell exemplarily shown in FIG.
It is composed of an insulated gate field effect transistor having a layer gate structure. In the figure, 1 is a P-type silicon substrate, 14 is a P-type semiconductor region formed on the silicon substrate 1, 13 is an N-type semiconductor region, and 15 is a low-concentration N-type semiconductor region. 8 is a floating gate formed on the P-type silicon substrate 1 via a thin oxide film 7 (for example, 10 nm thick) as a tunnel insulating film, and 11 is formed on the floating gate 8 via an oxide film 9. It is a control gate. The source is composed of 13, 15 and the drain is composed of 13, 14. The information stored in this memory cell is substantially held in the transistor as a change in threshold voltage. Hereinafter, unless otherwise specified, a case where a transistor for storing information (hereinafter referred to as a storage transistor) in the memory cell is an N-channel type will be described.

The operation of writing information to the memory cell is realized, for example, by applying a high voltage to the control gate 11 and the drain and injecting electrons from the drain side to the floating gate 8 by avalanche injection. By this writing operation, the memory transistor is changed to the one shown in FIG.
As shown in FIG. 5, the threshold voltage seen from the control gate 7 becomes higher than that of the memory transistor in the erased state in which the write operation is not performed.

On the other hand, in the erase operation, for example, a high voltage is applied to the source and the floating gate 8 is caused by the tunnel phenomenon.
It is realized by extracting electrons from the source to the source side. As shown in FIG. 11B, the erase operation lowers the threshold voltage of the storage transistor seen from the control gate 11. In FIG. 11B, the threshold value of the storage transistor is set to a positive voltage level in both the write and erase states. That is, the threshold voltage in the written state is raised and the threshold voltage in the erased state is lowered with respect to the word line selection level applied from the word line to control gate 11. By having such a relationship between both threshold voltages and the word line selection level, it is possible to configure a memory cell with one transistor without employing a selection transistor. In the case of electrically erasing stored information, the stored information is erased by pulling out the electrons accumulated in the floating gate 8 to the source electrode. More electrons than the amount of electrons injected into the floating gate 8 during operation will be extracted. Therefore, when over-erasing is performed such that electrical erasing is continued for a relatively long time, the threshold voltage of the storage transistor becomes a negative level, for example, and the disadvantage that the word line is not selected may be selected. Occurs. Note that writing can be performed by utilizing a tunnel current as in the case of erasing.

In the read operation, the voltages applied to the drain and the control gate 11 are compared so that weak writing to the memory cell, that is, unwanted injection of carriers into the floating gate 8 is not performed. Restricted to very low values. For example, a low voltage of about 1 V is applied to the drain 10 and a low voltage of about 5 V is applied to the control gate 11. By detecting the magnitude of the channel current flowing through the memory transistor by these applied voltages, "0" or "1" of the information stored in the memory cell can be determined.

FIG. 12 shows the construction principle of a memory cell array using the storage transistor. 4 in the figure
Storage transistors (memory cells) Q1 to Q4 are shown. In the memory cells arranged in a matrix in the X and Y directions, the storage transistors Q1 arranged in the same row
The control gates (selection gates of the memory cells) of Q2 (Q3, Q4) are respectively associated with the corresponding word line WL1.
The drain regions (input / output nodes of memory cells) of the memory transistors Q1, Q3 (Q2, Q4) connected to (WL2) and arranged in the same column are connected to the corresponding data lines DL1, DL2, respectively. The source regions of the storage transistors Q1, Q3 (Q2, Q4) are coupled to the source line SL1 (SL2).

FIG. 13 shows an example of voltage conditions for the erase operation and the write operation for the memory cell. In the figure, the memory element means a memory cell, and the gate means a control gate as a selection gate of the memory cell. In the figure, in the negative voltage type erasing, a high electric field necessary for erasing is formed by applying a negative voltage such as −10 V to the control gate. As is clear from the voltage conditions illustrated in the figure, in the case of erasing by the positive voltage method, it is possible to carry out batch erasing at least for the memory cells whose sources are commonly connected. Therefore, in the configuration of FIG. 12, if the source lines SL1 and SL2 are connected, the four memory cells Q1 to Q4 can be collectively erased. In this case, the size of the memory block can be set arbitrarily by changing the number of memory bits connected to the same source line. In the source line division method, in addition to the case where the data line as shown in FIG. 12 is used as a unit (the common source line is extended in the data line direction), the case where the word line is used as a unit (the common source line) Is extended in the word line direction). On the other hand, in the erase of the negative voltage system, it is possible to collectively erase the memory cells to which the control gates are commonly connected.

[0056]

[9] Multiple memory blocks with different storage capacities in units of data lines

FIG. 14 is a circuit block diagram showing an example of a flash memory in which the memory capacities of the batch erasable memory blocks are different.

Flash memory FMRY shown in FIG.
Has 8-bit data input / output terminals D0 to D7, and memory mats ARY0 to ARY7 for each data input / output terminal.
Equipped with. The memory mats ARY0 to ARY7 are divided into two, a memory block LMB having a relatively large storage capacity and a memory block SMB having a relatively small storage capacity. Although the details of the memory mat ARY0 are typically shown in the drawing, the other memory mats ARY1 to ARY are shown.
7 is similarly configured.

In each of the memory mats ARY0 to ARY7, a memory cell M composed of the insulated gate field effect transistor having the two-layer gate structure described in FIG.
Cs are arranged in a matrix. Similarly, in the same figure, WL
0 to WLn are word lines common to all the memory mats ARY0 to ARY7. The control gates of the memory cells arranged in the same row are connected to the corresponding word lines. In each of the memory mats ARY0 to ARY7, the drain regions of the memory cells MC arranged in the same column are connected to the corresponding data lines DL0 to DL7. The source regions of the memory cells MC forming the memory block SMB are commonly connected to the source line SL1, and the source regions of the memory cells MC forming the memory block LMB are commonly connected to the source line SL2.

The source lines SL1 and SL2 are supplied with the high voltage Vpp used for erasing from the voltage output circuits VOUT1 and VOUT2. Voltage output circuit VOUT1, VO
The output operation of UT2 is selected by the values of bits B1 and B2 of the erase block designation register. For example, by setting "1" to the bit B1 of the erase block designating register, only the memory block SMB of each of the memory mats ARY0 to ARY7 can be collectively erased. When "1" is set to the bit B2 of the erase block designation register, only the memory block LMB of each of the memory mats ARY0 to ARY7 can be collectively erased. When "1" is set to both bits B1 and B2, the entire flash memory can be erased at once.

The selection of the word lines WL0 to WLn is performed by selecting the row address signal A fetched through the row address buffer XABUFF and the row address latch XALAT.
This is performed by decoding X by the row address decoder XADEC. The word driver WDRV drives the word line based on the selection signal output from the row address decoder XADEC. In the data read operation, the word driver WDRV is operated by using a voltage Vcc such as 5V supplied from the voltage selection circuit VSEL and a ground potential such as 0V as a power source, and drives a word line to be selected to a selection level by the voltage Vcc. Then, the word line to be unselected is maintained at the unselected level such as the ground potential. In data write operation, word driver WDR
V is operated by using a voltage Vpp such as 12V supplied from the voltage selection circuit VSEL and a ground potential such as 0V as a power source, and drives a word line to be selected to a high voltage level for writing such as 12V. . In the data erasing operation, the output of the word driver WDRV is set to a low voltage level such as 0V.

In each of the memory mats ARY0 to ARY7, the data lines DL0 to DL7 are commonly connected to the common data line CD via the column selection switches YS0 to YS7. The switch control of the column selection switches YS0 to YS7 is performed by using the column address decoder YADE to detect the column address signal AY fetched through the column address buffer YABUFF and the column address latch YALAT.
It is done by C decoding. The output selection signal of the column address decoder YADEC is commonly supplied to all the memory mats ARY0 to ARY7. Therefore,
By setting one of the output selection signals of the column address decoder YADEC to the selection level, the common data line C in each of the memory mats ARY0 to ARY7.
One data line is connected to D.

The data read from the memory cell MC to the common data line CD is given to the sense amplifier SAMP via the selection switch RS, amplified there, and then amplified via the data output latch DOLAT to the data output buffer DOBU.
It is output from the FF to the outside. The selection switch RS is set to the selection level in synchronization with the read operation. The write data supplied from the outside is the data input buffer DIBUFF.
Is held in the data input latch circuit DILAT via. When the data held in the data input latch circuit DILAT is "0", the write circuit WRIT supplies the high voltage for writing to the common data line CD via the selection switch WS. The high voltage for writing is the column address signal AY.
It is supplied to the drain of the memory cell to which a high voltage is applied to the control gate by the row address signal AX through the data line selected by, and thereby the memory cell is written. The selection switch WS is set to the selection level in synchronization with the writing operation. The programming / erasing control circuit WEC is used to control various programming / erasing timings and voltages.
ONT is generated.

[10] Details of the microcomputer corresponding to FIG.

FIG. 15 is a block diagram showing a detailed embodiment of a microcomputer corresponding to the microcomputer shown in FIG. The microcomputer MCU shown in the figure has a central processing unit CPU, a flash memory FMRY, a serial communication interface SCI, a control circuit CONT, and a random access memory RAM as the same functional blocks as those shown in FIG. including. A 16-bit integrated timer, which corresponds to the timer shown in FIG.
Pulse unit IPU and watchdog timer WDT
Equipped with MR. Further, ports PORT1 to PORT12 are provided as those corresponding to the input / output circuit I / O of FIG. Further, as other functional blocks, a clock oscillator CPG, an interrupt controller IRCONT, an analog / digital converter ADC, and a wait state controller WSCONT are provided. The central processing unit CPU, flash memory FMRY, random memory
The access memory RAM and the 16-bit integrated timer pulse unit IPU are connected to the address bus ABUS, the lower data bus LDBUS (for example, 8 bits), and the upper data bus HDBUS (for example, 8 bits). The serial communication interface SCI, watchdog timer WDT
MR, interrupt controller IRCONT, analog
Digital converter ADC, wait state controller WSCONT, and ports PORT1 to PORT1
2 is an address bus ABUS and an upper data bus HD
Connected to BUS.

In FIG. 15, Vpp is a high voltage for rewriting the flash memory FMRY. EXTAL and X
TAL is a signal given to the clock oscillator CPG from a vibrator (not shown) externally attached to the chip of the microcomputer. φ is a synchronous clock signal output from the clock oscillator CPG to the outside. MD0 through MD
Reference numeral 2 is a mode signal supplied to the control circuit CONT for setting the first operation mode or the second operation mode when rewriting the flash memory FMRY, and corresponds to the mode signal MODE in FIG. RES * is a reset signal,
STBY * is a standby signal, and the central processing unit CP
It is supplied to U and other circuit blocks. NMI is a non-maskable interrupt signal and is used to generate a non-maskable interrupt by the interrupt controller ICONT.
Give to. Other interrupt signals not shown are in port P
Interrupt controller I via ORT8 and PORT9
Given to CONT. AS * is an address strobe signal indicating the validity of the address signal output to the outside, RD
* Is a read signal for notifying externally that it is a read cycle, HWR * is an upper byte write signal for notifying externally that it is a write cycle of upper 8 bits, L
WR * is a lower byte write signal for notifying externally that it is a write cycle of lower 8 bits, and these are used as access control signals to the outside of the microcomputer MCU.

Except for the second operation mode in which the flash memory FMRY is directly rewritten by the external PROM writer, the input / output of the data BD0 to BD15 for the microcomputer MCU to access the external is not particularly limited. PORT1 and PORT2 are assigned. Address signals BA0 to BA at this time
The output of 19 is not particularly limited, but the port PO
RT3 to PORT5 are assigned.

On the other hand, the microcomputer MCU has a second
When the operation mode is set, the flash memory F
To connect to a PROM writer that controls MRY rewriting,
The ports PORT2 to POR are not particularly limited.
T5 and PORT8 are assigned. That is, the ports PORT2 are assigned to the input / output of the data ED0 to ED7 for writing and verifying, the input of the address signals EA0 to EA16 and the access control signals CE * (chip enable signal) and OE * (output enable signal). , WE * (write enable signal)
Is input to the ports PORT3 to PORT5 and P
ORT8 is assigned. The chip enable signal C
E * is the flash memory FMRY from the PROM writer
Operation select signal and output enable signal O
E * is an instruction signal for an output operation to the flash memory FMRY, and the write enable signal WE * is an instruction signal for a write operation to the flash memory FMRY. One of the address signals EA0 to EA16
The input terminal of the signal NMI is assigned to the input of the bit EA9. The external terminals of the ports allocated in this way, and other necessary external terminals such as the high voltage Vpp application terminal are the conversion socket SOCKET described in FIG.
Is connected to the general-purpose PROM writer PRW via. At this time, the external terminals are allocated by connecting the microcomputer MCU to the PROM via the conversion socket SOCKET.
It can be taken into consideration to make the terminal arrangement easy to connect to the writer PRW. PROM in the second operation mode
The external terminal group assigned to the connection with the writer PRW,
Other functions will be assigned in other operation modes of the microcomputer MCU.

FIG. 16 shows the upper surface of a flat package having external terminals in four directions obtained by sealing the microcomputer MCU of FIG. 15 with resin, for example. The signals shown in FIG. 16 are common to those in FIG. External terminals (pins) without signal names are input pins for wait signals, input pins for bus request signals, output pins for bus acknowledge signals, serial communication interface SCI and other peripheral circuits, and external signal inputs. It is used for output pins.

In the package FP shown in FIG. 16, each terminal (pin) derived from the package FP.
The interval may be 0.5 mm or less. That is,
When the user of the microcomputer MCU connects the flash memory FMRY in the microcomputer MCU to the PROM writer PRW via the conversion socket SOCKET and writes data in the flash memory FMRY, the terminal intervals (pin pitch) of the package FP.
If PP is 0.5 mm or less, the conversion socket S
When the package FP is inserted into the OCKET, pin bending due to undesired contact between the conversion socket SOCKET and the external terminal of the package FP is likely to occur. When such pin bending occurs, electrical connection between each terminal of the conversion socket SOCKET and each terminal of the package FP is not performed with respect to the terminal having the pin bending. As a result, the PROM writer PRW
Then, it becomes impossible to write data in the flash memory FMRY.

With respect to this point, in the present invention, since the central processing unit CPU is capable of writing data to the flash memory FMRY, the user is required to write data to the flash memory FMRY by the external PROM writer P.
If the central processing unit CPU writes data in the flash memory FMRY after the package of the microcomputer MCU is mounted on the mounting substrate (printed circuit board) without using the RW, the microcomputer MCU has the pin pitch PP. Even if it is sealed in a package of 0.5 mm or less, the user can prevent the lead bending of the external terminal led out from the package. Note that semiconductor manufacturers have automatic handlers, so 0.5 mm
Even if the microcomputer MCU is sealed in a package having the following pin pitch, the microcomputer MCU can be reliably tested without causing pin bending.

[11] Rewriting control circuit of flash memory FMRY

FIG. 17 shows an overall block diagram of the flash memory FMRY incorporated in the microcomputer MCU of FIG. In the same drawing, ARY is a memory array in which memory cells constituted by the insulated gate field effect transistors of the double-layer gate structure described in FIG. 11 are arranged in a matrix. This memory array AR
Similar to the configuration described with reference to FIG. 14, Y represents that the control gates of the memory cells are connected to the corresponding word lines, the drain regions of the memory cells are connected to the corresponding data lines, and the source regions of the memory cells are the memory blocks. Each of them is connected to a common source line, but the division mode of the memory block is different from that in FIG. For example, as shown in FIG. 18, seven large memory blocks (large blocks) LMB0 each having a relatively large storage capacity are provided.
To LMB6, and eight small memory blocks (small blocks) SMB0 to SMB each having a relatively small storage capacity.
It is divided into MB7. The large memory block is used as a program storage area or a large capacity data storage area. The small memory block is used as a small capacity data storage area.

In FIG. 17, ALAT is a latch circuit for the address signals PAB0 to PAB15. The address signals PAB0 to PAB1 in the first operation mode
Reference numeral 5 corresponds to the output address signal of the central processing unit CPU. In the second operation mode, address signals PAB0 through PAB0
B15 is an output address signal EA of the PROM writer PRW
0 to EA15. XADEC is a row address decoder that decodes a row address signal fetched through the address latch ALAT. WDRV is a word driver that drives a word line based on a selection signal output from the row address decoder XADEC. In the data read operation, the word driver WDRV is 5V
The word line is driven with such a voltage, and the word line is driven with a high voltage such as 12 V in the data write operation. In the data erase operation, all outputs of the word driver WDRV are set to a low voltage level such as 0V. YADE
C is a column address decoder for decoding a column address signal fetched through the address latch YALAT. YSEL is a column address decoder that selects a data line according to the output selection signal of the column address decoder YADEC. SAMP is a sense amplifier that amplifies a read signal from the data line selected by the column selection circuit YSEL in the data read operation. DOLAT
Is a data output latch that holds the output of the sense amplifier. DOBUFF is a data output buffer for outputting the data held in the data output latch DOLAT to the outside. In the figure, PDB0 to PDB7 are lower 8 bits (1 byte) data, and PDB8 to PDB15
Is upper 8 bits (1 byte) data. According to this example, the maximum output data is 2 bytes. DIBUFF
Is a data input buffer for fetching write data supplied from the outside. Data input buffer DIBU
The data input from the FF is the data input latch circuit D
Held in ILAT. Data input latch circuit DILA
When the data held in T is "0", the write circuit WR
IT supplies a high voltage for writing to the data line selected by the column selection circuit YSEL. The high voltage for writing is supplied to the drain of the memory cell to which the high voltage is applied to the control gate according to the row address signal, and thereby the memory cell is written. ERASEC is an erasing circuit for supplying a high voltage for erasing to a source line of a designated memory block to collectively erase the memory blocks.

FCONT is a flash memory FMRY.
Is a control circuit for controlling the timing of the data read operation in the above, and controlling various timings and voltages for writing and erasing. The control circuit FCONT includes a control register CREG.

FIG. 19 shows the control register CREG.
An example is shown. The control register CREG is
8-bit program / erase control register PEREG and erase block designation register MBREG1
And MBREG2. program/
In the erase control register PEREG, Vpp is a high voltage application flag that is set to "1" in response to the application of the high voltage for rewriting. The E bit is a bit instructing an erase operation, and the EV bit is an instruction bit for a verify operation in erase. The P bit is an instruction bit for a write operation (program operation), and the PV bit is an instruction bit for a verify operation in writing. Erase block designating registers MBREG1 and MBREG2 are registers for designating which memory block contained in a large block divided into 7 and a small block divided into 8 is to be erased. It is used as a designation bit for each memory block, for example, bit "
1 "means selection of corresponding memory block, bit"
0 "means non-selection of the corresponding memory block. For example, when the 7th bit of the erase block designating register MBREG2 is" 1 ", erasing of the small memory block SMB7 is designated.

The control register CREG is externally readable and writable. Control circuit FCO
The NT refers to the setting contents of the control register CREG and controls the erasing / writing according to the contents. Externally, its control register CR
By rewriting the contents of EG, the state of the erase / write operation can be controlled.

In FIG. 17, the control circuit FCONT has FLM, MS-FLN, MS-MI as control signals.
SN, M2RDN, M2WRN, MRDN, MWRN,
IOWORDN, and RST are supplied, and the top 1
Byte data PDB8 to PDB15 and predetermined bits of address signals PAB0 to PAB15 are given.

The control signal FLM is the flash memory FM.
This is a signal that specifies the RY operation mode, and "0" specifies the first operation mode and "1" specifies the second operation mode. This signal FLM is, for example, the mode signal MD.
It is formed based on 0 to MD2.

The control signal MS-FLN is a selection signal for the flash memory FMRY, and "0" indicates selection and "1" indicates non-selection. The central processing unit CPU outputs the control signal MS-FLN in the first operation mode, and the control signal MS-FLN in the second operation mode.
Corresponds to the chip enable signal CE * supplied from the PROM writer PRW.

The control signal MS-MISN is a selection signal for the control register CREG. At this time, which of the program / erase control register PEREG and the erase block designating registers MBREG1 and MBREG2 is selected is determined by referring to predetermined bits of the address signals PAB0 to PAB15. In the first operation mode, the central processing unit CPU outputs its control signal MS-MISN. In the second operation mode, although not particularly limited, PR
Most significant address bit EA output by OM writer PRW
16 is considered as its control signal MS-MISN.

M2RDN is a memory read strobe signal, M2WRN is a memory write strobe signal, MRD.
N is a read signal of the control register CREG, MW
RN is a write signal of the control register CREG. In the first operation mode, the central processing unit CPU outputs these control signals. In the second operation mode, although not particularly limited, the write enable signal WE * supplied from the PROM writer PRW is regarded as the signals M2WRN and MWRN, and the output enable signal OE * supplied from the PROM writer is regarded as the signal M2RDN, MRDN
Is regarded as The memory write strobe signal M2W
RN is regarded as a strobe signal for writing the data to be written in the memory cell into the data input latch circuit DILAT. The actual writing to the memory cell is started by setting the P bit in the control register CREG.

IOWORDN is a flash memory FMR
It is a switching signal for 8-bit read access and 16-bit read access to Y. In the second operation mode, the control signal IOWORDN is fixed to a logical value instructing 8-bit read access.

RST is a reset signal for the flash memory FMRY. When the flash memory FMRY is reset by this signal RST or the Vpp flag of the program / erase control register PEREG is set to "0", EV, PV, and PV in the program / erase control register PEREG are reset.
Each mode setting bit of E and P is cleared.

FIG. 20 shows a timing chart of an example of the memory read operation in the flash memory FMRY. In the figure, CK1M and CK2M are non-overlap two-phase clock signals and are regarded as operation reference clock signals. tCYC is the cycle time,
It is not much different from the access time to RAM. The read operation for the control register CREG is also performed at the same timing.

FIG. 21 shows a timing chart of an example of the memory write operation in the flash memory FMRY. Write strobe signal M2WRN shown in FIG.
In the memory write operation instructed by, as described above, the actual writing to the memory cell is not performed, the input address signals PAB0 to PAB15 are held in the address latch circuit ALAT, and the input data PB8 is held.
Through PB15 are held in the data input latch DILAT, and the write cycle is completed. The write operation to the control register CREG is also performed at the same timing as this, but in this case, actual data writing to the control register CREG is performed.

[12] Details of rewriting control procedure of flash memory FMRY

In this item, the central processing unit CPU or P
A detailed example of a control procedure in which the ROM writer writes and erases the flash memory via the control circuit FCONT will be described. Writing of information to the flash memory is basically performed on a memory cell in an erased state. In the first operation mode for rewriting the flash memory in the state where the microcomputer is installed in the system, the rewriting control program to be executed by the central processing unit CPU includes an erasing program and a writing program. According to the designation of the first operation mode, the rewrite control program can be configured such that the erase processing routine is executed first, and subsequently the write processing routine is automatically executed. Alternatively, the first operation mode may be specified separately for erasing and writing. The rewriting control by the PROM writer is also executed by the same operation as in the first operation mode. The write control procedure and the erase control procedure will be described below.

FIG. 22 shows a detailed example of the write control procedure. The procedure shown in the figure is, for example, a procedure for writing 1-byte data, and is common to both the control of the central processing unit CPU in the first operation mode and the control of the PROM writer in the second operation mode. To be done. For example, the control subject is described as the central processing unit CPU.

At the first step of writing data in byte units, the central processing unit CPU sets 1 in its built-in counter n (step S1). Next, the central processing unit CPU performs the memory write operation described in FIG. 21, sets the data to be written in the flash memory FMRY in the data input latch circuit DILAT in FIG. 17, and sets the address to write the data in. The address latch circuit ALAT is set (step S2). Then, the central processing unit CPU issues a write cycle to the control register CREG, and the program bit P
Is set (step 3). As a result, the control circuit FC
The ONT applies a high voltage to the control gate and drain of the memory cell designated by the address based on the data and address set in the step 2 to perform writing. As the write processing time on the flash memory side, the central processing unit CPU waits, for example, 10 μsec (step S4), and then clears the program bit P (step S5).

Thereafter, the central processing unit CPU issues a write cycle to the control register CREG to set the program verify bit PV in order to confirm the write state (step 6). As a result, the control circuit FCONT utilizes the address set in the step 2 and applies the verify voltage to the word line to be selected by the address to read the data of the written memory cell. . Here, the verify voltage is set to a voltage level such as 7V which is higher than the power supply voltage Vcc such as 5V in order to ensure a sufficient write level. The central processing unit CPU confirms that the data read thereby matches the data used for writing (step S7). Central processing unit CP
When U confirms the match by verifying, U clears the program verify bit PV (step S8),
This completes the writing of the 1-byte data.

On the other hand, the central processing unit CPU executes the step S
If the non-coincidence is confirmed by the verification of step 7, the program verify bit PV is cleared in step S9, and then the value of the counter n is set to the write retry upper limit number N.
It is determined whether or not has reached (step S10). As a result, if the write retry upper limit number N has been reached, the process ends as a write failure. When the write retry upper limit number N has not been reached, the central processing unit CPU increments the value of the counter n by 1 (step S11), and repeats the processing from step S3.

FIG. 23 shows a detailed example of the erase control procedure. The procedure shown in the figure is common to both the control of the central processing unit CPU in the first operation mode and the control of the PROM writer in the second operation mode. For example, the control subject is described as the central processing unit CPU.

The central processing unit CPU sets 1 to its built-in counter n when erasing (step S2).
1). Next, the central processing unit CPU prewrites the memory cells in the erase target area (step S22).
That is, data "0" is written in the memory cell of the erase target address. The write control procedure described with reference to FIG. 22 can be used as the prewrite control procedure. This pre-write process is performed in order to make the amount of charge in the floating gate before erasing uniform for all bits and make the erased state uniform.

Next, the central processing unit CPU issues a write cycle to the control register CREG to specify the memory block to be erased collectively (step S23). That is, the erase block designation register MBR
The memory block numbers to be erased are designated in EG1 and MBREG2. After specifying the memory block to be erased,
The central processing unit CPU has a control register CREG.
Issue a write cycle to erase bit E
Is set (step 24). As a result, the control circuit F
The CONT applies a high voltage to the source line of the memory block specified in step 23 to erase the memory block in a batch. The central processing unit CPU has a processing time of, for example, 10 m as the processing time of batch erasing on the flash memory side.
Wait sec (step S25). This time of 10 msec is shorter than the time required to complete the erase operation once. Then, the erase bit E is cleared (step S26).

Thereafter, in order to confirm the erased state, the central processing unit CPU first internally sets the head address of the batch erase target memory block as the address to be verified (step S27), and then performs a dummy write to the verify address. Perform (step S28). That is, the memory write cycle is issued to the address to be verified. As a result, the memory address to be verified is held in the address latch circuit ALAT. After that, the central processing unit CPU issues a write cycle to the control register CREG to set the erase verify bit EV (step 2).
9). As a result, the control circuit FCONT uses the address set in step S28, applies the erase verify voltage to the word line to be selected by the address, and reads the data in the erased memory cell. . Here, the erase verify voltage is, for example, a power supply voltage Vc such as 5V in order to guarantee a sufficient erase level.
The voltage level is set to 3.5V, which is lower than c. The central processing unit CPU verifies whether the data read thereby matches the data in the erase completed state (step S30). When the central processing unit CPU confirms the match by verifying, it erases the erase verify bit EV (step S31), and then determines whether or not the verify address of this time is the final address of the erased memory block (step S32). If it is an address, a series of erase operations is completed. If it is determined that the final address has not been reached, the verify address is incremented by 1 (step S33), and the processing from step S29 is repeated.

On the other hand, the central processing unit CPU executes the step S
If the discrepancy is confirmed by the verification of 30, the erase verify bit EV is cleared in step S34, and then it is determined whether the value of the counter n has reached the erasing upper limit number N gradually (step S35). As a result, if the erasure upper limit number N has been reached gradually, the process ends as an erasing failure. When the erasure upper limit number N has not been reached, the central processing unit CPU increments the value of the counter n by 1 (step S3).
6) The process is repeated from step S24. In practice, in order to prevent over-erasing in which the threshold voltage of the memory cell becomes a negative value due to over-erasing, verify is performed every time and a short time such as 10 msec is gradually applied. Erasing is repeated.

[13] Forming a plurality of memory blocks having different storage capacities in units of word lines

FIG. 25 shows a memory mat structure of a flash memory which is divided into a plurality of memory blocks in units of word lines and has different memory capacities that can be collectively erased.

In the structure shown in FIG. 14, the memory block is defined in units of data lines, but in FIG. 25, the memory block is defined in units of word lines. In the figure, in the memory mats ARY0 to ARY7, a memory block LMB having a relatively large storage capacity and a memory block SMB having a relatively small storage capacity are representatively shown.

Each of the memory mats ARY0 to ARY7 has a memory cell M formed of the insulated gate field effect transistor having the two-layer gate structure described with reference to FIG.
Cs are arranged in a matrix. In the figure, WL0
WLn is a word line common to all the memory mats ARY0 to ARY7. The control gates of the memory cells arranged in the same row are connected to the corresponding word lines. In each of the memory mats ARY0 to ARY7, the drain regions of the memory cells MC arranged in the same column are connected to the corresponding data lines DL0 to DLm. The source regions of the memory cells MC forming the small memory block SMB are commonly connected to the source line SLwi extending in the word line direction, and the source regions of the memory cells MC forming the large memory block LMB extend in the word line direction. It is commonly connected to the source line SLw1. 14
In the case of batch erasing in units of memory blocks, as in the case of, the memory block to be batch erased is designated by the erase block designating register, and the high voltage Vp for erasing is assigned to the source line of the memory block designated by this.
p is supplied. Details of the voltage condition for erasing / writing will be described later. In addition, YSEL is a Y selection circuit, CD
Is a common data line, WRIT is a write circuit, DILAT
Is a data input latch, SAMP is a sense amplifier, DOL
AT is a data output latch, DIBUFF is a data input buffer, and DOBUFF is a data output buffer.

Here, the memory mats ARY0 to ARY7.
And the output data are the same as in FIG. That is, 1 bit of input / output data corresponds to one memory mat. For example, the data D0 is the memory mat ARY0.
Is carried by. By adopting the configuration of 1 I / O in such one memory mat, the Common data line CD can be divided for each memory mat, and it is not extended with a long distance so as to penetrate all the memory mats. It will be finished. Therefore, the parasitic capacitance of the common data line CD can be reduced, which contributes to high-speed access and low-voltage operation.

As shown in FIG. 25, when memory blocks such as LMB and SMB are defined in units of word lines, the memory array A whose parallel input / output bit number is 1 byte.
The storage capacity of the minimum memory block in the entire RY is the storage capacity of one word line. This does not change regardless of the number of parallel input / output bits. On the other hand, when defining a memory block in units of data lines as shown in FIG. 14, the minimum memory block in the entire memory array corresponds to eight data lines corresponding to the number of parallel input / output bits (each memory mat). The storage capacity is one data line each). Therefore, if the memory bit number in the data line direction is ⅛ of the memory bit number in the word line direction, the unit of the memory block is the same whether the data line or the word line is used. The number of memory bits in the data line direction is normally about 1/2 of the number of memory bits in the word line direction because of the layout efficiency or the addressing efficiency of the memory cells when integrated into a circuit. Since the flash memory is connected to the internal data bus, the number of parallel input / output bits is set in byte or word units.
It is better to define the memory block in word line units.
The storage capacity of the smallest memory block can be remarkably reduced. If the minimum size of the memory block can be made smaller, the usability of using this as a data area will be further improved. Furthermore, if information that does not need to be rewritten is collectively erased and then that information is rewritten again. The so-called waste prevention effect can be further exerted.

[14] Measures for disturbing data line disturb for non-selected write block

FIG. 26 shows an example of erase / write voltage conditions when a memory block is defined in word line units. In particular, a data line disturb countermeasure is taken for a non-selected block for writing (non-selected memory block).

In (A) showing the erase voltage condition, the selected block (selected memory block) 20 is a memory block for which batch erase is selected, and the non-selected block 21 is a memory block for which batch erase is not selected. In the erase operation, the representative word lines WLh to WLk are shown.
Is given a ground potential GND such as 0V. In the selected block 20, a high voltage Vpp such as 12V is applied to the common source line SLwm, whereby the memory cells of the selected block 20 are erased at once. In the non-selected block 21, the common source line SLwn is set to the ground potential GND and erase is suppressed.

In (B) showing the write voltage condition,
The selected block 30 is a memory block including a memory cell to be programmed, and the non-selected block 31 is a memory block that does not include a memory cell to be programmed. Common source line SLwm in the selection block 30
Is supplied with the ground potential GND, for example, when the memory cell MC surrounded by a two-dot chain line is to be programmed, a high voltage Vpp is applied to the word line WLh to which the control gate is connected and the data line is applied to the word line WLh. Is given a relatively high voltage Vp such as 6V. In the selection block 30, the ground potential GND is applied to the unselected word lines WLi.

In the non-selected block 31 at the time of writing, all the word lines WLj and WLk have the ground potential GN.
When set to D, the memory cell is not selected. Due to the fact that the word lines are used as a unit to form a memory block, the data lines in the non-selected block 31 are also selected by the selected block 3.
The voltage Vp is applied in response to the writing at 0. That is, the memory cells MC in the non-selected block 31 are brought into the word line non-selected state and the data line selected state according to the writing in the selected block 30. For example, according to the state shown in FIG. 26B, when writing a circled memory cell in the selected block, the memory cell of the non-selected block 31 connected to the data line DLk (square of two-dot chain line) The voltage Vp is applied to the memory cell surrounded by. At this time, a voltage Vddi (data line disturb blocking voltage) such as 3.5V is applied to the source line SLwn common to the non-selected blocks 31 to take measures against the data line disturb. Similarly to the selection block 30, the source line SLwn
When the ground potential GND is applied to, a data line disturb occurs. Although some memory cells that are not to be written in the selected block 30 are brought into the same state as the data line disturb is generated because the ground potential GND is applied to the word line and the source line, the state is substantially the same. Can be ignored. This will be clarified from the description of the item [15] "Correlation of data line disturb time between memory blocks" described later.

FIG. 27A shows the generation mechanism of the data line disturb. That is, in the region near the drain edge, electron-hole pairs are generated due to the tunneling phenomenon between bands. At this time, when the source is set to the ground potential GND and the drain is set to the relatively high voltage Vp to generate a relatively large electric field, the holes of the electron-hole pair are generated by the electric field in the depletion layer in the region. It is accelerated and becomes a hot hole with high energy. The hot holes are injected into the floating gate 8 through a thin tunnel insulating film (under the floating gate electrode 8) having a thickness of about 10 nm. This state is the state of the data line disturb, and when the time for receiving the data line disturb becomes long, the threshold value of the memory cell transistor decreases, and the write state "0".
Memory cells in the erased state "1" and the memory cells in the erased state "1" are depleted, causing an undesired change in stored information and a malfunction (data line disturb failure).

FIG. 27B shows a mechanism for preventing data line disturbance. That is, as shown in FIG. 26, in the write non-selected block, when the voltage Vddi such as 3.5 V is applied to the source of the memory cell to raise the potential on the source side, the depletion layer of the region is The electric field is weakened, which prevents the holes of the electron-hole pair from becoming hot holes and prevents the threshold voltage of the memory cell transistor from decreasing.

FIG. 28 shows an experimental example relating to changes in the threshold value of the memory cell with respect to the data line disturb time. In this experiment, the memory cell transistor shown in the figure is used, and the control gate and the back gate thereof are supplied with the ground potential GND, and the drain thereof is applied with 6.5 V, and the floating voltage (o
Pen), and the threshold voltage when writing is repeated for each source potential Vs of 3.5V. The upper side of the figure is for the memory cell transistor in the write state "0", and the lower side is for the memory cell transistor in the erase state "1". As is clear from the figure, by setting Vs = 3.5V, a data line disturb time of about 1000 seconds causes a large reduction in the threshold value that cannot be ignored in both the erased state and the written state. There wasn't.

As a result, in order to prevent the occurrence of defects due to the data line disturb, the source potential of the non-selected memory block is biased with the data line disturb blocking voltage Vddi such as 3.5V, and the data line disturb is applied. The need to keep the time as short as possible will be appreciated.

[15] Correlation of data line disturb time between memory blocks

The correlation of the data line disturb time between the memory block MBa having a relatively small storage capacity and the memory block MBb having a relatively large storage capacity shown in FIG. 29 will be described. For convenience of description, the common source line of the write non-selected block is also set to the ground potential GND similarly to the write selected block. The data line disturb time at this time is shown in FIG. In FIG. 30, although not particularly limited, the write time per bit of the memory cell is 100 μsec, and the erase / write count is 10,000.
I am trying to do it. The one-time erasing / writing operation is an operation of erasing the target memory block in a batch and then switching the word lines to write the data in the memory cell. However, regarding the data line disturb time with respect to the memory cell in the memory block selected for writing, it is considered that the word line to which the memory cell is coupled is not selected.

According to this result, the memory block MBa
The data line disturb time received by the memory cell MCa is 1.5 msec when the memory block MBa is selected for writing (see TypeAfromA column), and when the memory block MBb is selected (TypeAfromB). Is 1000)
It is assumed to be sec. The difference is that the memory block M
This is due to the difference in the storage capacities (the number of word lines) of Ba and MBb. That is, the formula for calculating the data line disturb time shown in the column of TypeAfrommA is 100 μs ×
In the case of 15 × 1 times, the number of word line switching at the time of writing after the memory block batch erase is the memory block MBa.
15 corresponding to the number of word lines of
100 μs × 1008 × 10000, which is the formula for calculating the data line disturb time shown in the column of peAfromB.
This is because the number of word line switchings at the time of writing after the memory block batch erase is set to 1008, which corresponds to the number of word lines of the memory block MBb. Second
In the calculation of the data line disturb time received by the memory cell MCa in the memory block MBa selected for rewriting, the substantial number of times of rewriting can be regarded as one. That is, the formula for calculating the data line disturb time shown in the column of TypeAfrommA is 100 μs × 1.
The number of times of rewriting is regarded as one time in 5 × 1 times, whereas 100 μs × 1008 × 1 which is the calculation formula of the data line disturb time shown in the column of TypeAfromB.
This is because the number of rewrites at 0000 is set to 10,000, which corresponds to the actual number of rewrite operations. This is because in the case of the memory cell MCa in the memory block MBa to be rewritten and selected, the threshold voltage of all the memory cells is rewritten every time the rewriting operation is performed by the prewriting prior to the batch erasing as described with reference to FIG. The data line disturb time of the memory cell MCa is considered to be substantially defined by one rewriting time since the data is disturbed stepwise from the viewpoint of preventing overerasure. is there. In other words, it can be considered that the data line disturb state received by the memory cell MCa in the memory block MBa selected for rewriting is initialized every rewriting. On the other hand, when the rewriting selected memory block is the memory block MBb, the memory cell MC
For a, the initialization is not performed, and the data line disturb time is accumulated according to the actual number of times of rewriting.

Similarly, the data line disturb time received by the memory cell MCb of the memory block MBb is 0.1 sec when the memory block MBb is selected and is to be written (TypeBfromB column). When MBa is selected (Type
The BfromA column) is set to 16 seconds. This difference is also similar to the above-mentioned difference in the storage capacity (the number of word lines) of the memory block and the memory block MBb selected for rewriting.
This is because the substantial number of times of rewriting can be regarded as one in the calculation of the data line disturb time received by the memory cell MCb in the inside.

As a result, the data line disturb time generated on the non-selected memory block side due to the writing of the selected memory block is significantly longer than the data line disturb time received by the memory cells in the selected memory block. it is obvious. Therefore, in order to prevent the decrease in the threshold voltage of the memory cell due to the data line disturb, it is at least necessary to bias the common source line on the write non-selected memory block side with the voltage Vddi as described with reference to FIG. However, regarding the data line disturb time received by the memory cells in the selected memory block, it becomes clear that there is almost no harm even if this is ignored.

Further, TypeAfromB and Type in the correlation of the data line disturb time in FIG.
The contents of BfromA reveal the following. That is, the data line disturb time received by a small memory block due to the writing of a memory block having a large storage capacity is relatively long as compared with the opposite case.

[16] Transfer gate circuit for data line separation

FIG. 31 shows an embodiment of a memory array in which transfer gate circuits for selectively separating data lines are provided between memory blocks. The transfer gate circuit TGC is arranged between the memory block MBa and the memory block MBb, and has transfer MOS transistors T0 to Tk interposed in one-to-one correspondence with the data lines DL0 to DLk, which are switch-controlled by a control signal DT. To be done. According to this example, the Y selection circuit YSEL such as the column selection switch circuit is arranged on the memory block MBb side. The transfer M is shown in FIG.
A switch control mode of the OS transistors T0 to Tk is shown. The selected block at the time of writing is the memory block MBa
, The transfer MOS transistors T0 to T0
Tk is turned on. At this time, the source potential Vsa of the memory block MBa as the write selected block is set to the ground potential GND, and the source potential Vsb of the memory block MBb as the write unselected block is 3.5.
The data line disturb blocking voltage Vddi such as V is set. On the other hand, when the selected block at the time of writing is the memory block MBb, the transfer MOS transistors T0 to Tk are turned off. At this time, the source potential V of the memory block MBb as the write selection block
sa is set to the ground potential GND. Source potential Vsb of memory block MBa as a write non-selected block
Is a data line disturb blocking voltage Vd such as 3.5V
It may be di or the ground potential GND (or floating). With the transfer MOS transistors T0 to Tk in the cut-off state, the Y selection circuit Y
This is because the write voltage Vp of the data line supplied via SEL is not transmitted to the memory block MBa.

In particular, the transfer gate circuit TGC
Has the following significance with respect to the data line disturb time of the write non-selected block. That is, when the memory block MBa is set as the write selection block, the transfer gate circuit TGC is provided on the front side (Y selection circuit YS).
A relatively high voltage Vp for writing in the memory block MBa is applied to the memory block MBb arranged on the EL side) via the data line. In this state, the data line disturb blocking voltage Vddi is applied to the common source line of the memory block MBb which is the write unselected block, and the data line disturb is basically blocked, but this state continues for a long time. 28 (when the data line disturb time becomes considerably long), as is apparent from FIG. 28, even if the source is biased with the voltage Vddi,
The threshold value of the memory cell in the programming state in the programming non-selected memory block MBb decreases slightly. Therefore, as described with reference to FIG. 31, the data line disturb time received by the small memory block due to the writing accompanying the rewriting of the memory block having the large storage capacity becomes relatively large as compared with the opposite case. Paying attention to the point, Y with the transfer gate circuit TGC in between
The memory block MBb on the selection circuit YSEL side is a large memory block having a relatively large storage capacity, and the memory block MBa on the opposite side is a small memory block having a relatively small storage capacity. As a result, the data line disturb time received by the memory cells of the memory block MBb due to the writing of the memory block MBa is
Compared to the case where Ba is a large memory block and memory block MBb is a small memory block, it is significantly shorter when the memory block MBa is a small memory block and the memory block MBb is a large memory block. As a result, the malfunction prevention due to the data line disturb becomes more complete.

FIG. 32 shows a summary of the data line disturb countermeasures. In the figure, the voltage application state of (A) showing the data line disturb countermeasure for the non-selected memory block represents the memory cell transistor connected to the data line whose supply of the write voltage is cut off due to the off state of the transfer gate circuit TGC. ing.

[17] Dummy word line

33, 34, and 35 are circuit diagrams in which dummy word lines are arranged between the memory block and the transfer gate circuit. In each figure, DWA is a dummy word line on the memory block MBa side, and DWB is a dummy word line on the memory block MBb side. Each dummy word line DWA, DWB is coupled with a control gate of a dummy cell DC0-DC6, which is typically represented by DC1 through DC6, and is supplied with a ground potential GND. Dummy cells DC0 to DC
6 is composed of the same transistor as the memory cell. In FIG. 33, the sources of the dummy cells DC0 to DC6 are floated and the drains are coupled to the data lines. In FIG. 34, the sources and drains of the dummy cells DC0 to DC6 are both floating. In FIG. 35, the sources of the dummy cells DC0 to DC6 are connected to the common source line of the corresponding memory block, and the drains thereof are floating. When the transfer gate circuit TGC is provided between the memory blocks, the repeated pattern of the memory cell transistor and the word line is interrupted at that position, which causes a sharp unevenness on the wafer surface in terms of device structure. Such unevenness makes the film thickness of the photoresist film nonuniform when the word line and the control gate are formed by photoetching or the like. As a result, the dimensions of the word lines and control gates become partially non-uniform, causing variations in the electrical characteristics of the transistors and word lines. Under such circumstances,
Dummy word lines DWA and DWB and dummy cells DC0 to DC0
By disposing DC6 at the ends of the memory blocks MBa and MBb separated by the transfer gate circuit TGC, it is possible to reduce the dimensional variation of the word line and the control gate in the vicinity of the transfer gate circuit TGC.

[18] Various Modes of Multiple Memory Blocks in Word Line Units

As shown in FIG. 36, two memory blocks can be arranged on each side of the transfer gate circuit TGC. At this time, desirably, the memory block MBc and the memory block MBd on the side of the Y selection circuit YSEL are set as a large memory block, and the memory block MBb and the memory block MBa in the subsequent stage of the transfer gate circuit TGC are set as a small memory block. For example, the large memory block is used for storing programs, and the small memory block is used for storing data.

As shown in FIG. 37, the minimum erasable memory block has one word line and two word lines in sequence.
The number can be increased to three or four, but the number of word lines of each memory block that can be collectively erased can be appropriately determined, and the size of each memory block can be appropriately changed and configured. .

As shown in FIG. 38, each word line is set to 1
When relatively small memory block groups MBa to MBe each having two, three, four, and eight and relatively large memory block groups MBf and MBf each having 64 word lines are adopted, As can be inferred from the description of [16], the transfer gate circuit TGC is preferably arranged at the boundary between the large memory block group and the small memory block group.

As shown in FIG. 39, a main data line and a sub data line are adopted as the data line structure. Main data line D
L0 to DLk reach all the memory blocks MBa to MBc. Sub-data lines d0-dk extend only within each memory block, and the drains of the memory cells included in the corresponding memory block are coupled to each other. At this time, the connection between the main data lines DL0 to DLk and the sub data lines d0 to dk is
This is performed through the transfer gate circuit TGC assigned to each memory block. Such a structure can be easily realized by a two-layer aluminum wiring structure, for example. In this main / sub data line structure, since the transfer gate circuit TGC is arranged for each memory block,
The write data line potential Vp can be applied only to the write selected block. Therefore, the countermeasure against the data line disturbance of the write-unselected memory block becomes more complete.

FIG. 40 shows an embodiment in which batch erasable memory blocks are arranged on the left and right of the X address decoder. The decode signal of the X address decoder XADEC is output to the left and right. And X address decoder XAD
Memory blocks MBa to MBc and MBa 'to MBc' are arranged on the left and right sides of the EC in units of word lines arranged respectively.
Is configured. Any of the above memory blocks can be adopted as each memory block. The left and right memory blocks are provided with Y selection circuits YSEL and YSE.
Data io0 to io7, i in 8-bit units via L '
Input / output of o8 to io15 is performed. Transfer MOS transistors Tsw are provided in a one-to-one correspondence between the left output of the X address decoder XADEC and the word lines WL0 to WLn. Similarly, the X address decoder XADE is provided.
There is a one-to-one correspondence between the output on the right side of C and the word lines WL0 'to WLn' in a transfer MOS transistor Ts.
w'is provided. Further, discharge MOS transistors Csw and Csw ′ are arranged on each word line. The control circuit DIVCONT is a left and right transformer MOS.
Transistors Tsw, Tsw 'and discharge MO
Switch control of the S transistors Csw and Csw ′ is performed. The control circuit DIVCONT is not particularly limited,
The high voltage Vpp1 and the most significant address bit An of the address signal are received, and the transfer MOS transistors Tsw, T are transferred in accordance with the logical value of the most significant address bit An.
sw ′ and discharge MOS transistor Csw,
Csw 'is complementarily switch-controlled on the left and right. For example,
When the most significant address bit An is logic 1, the right transfer MOS transistor Tsw 'is turned on, the left transfer MOS transistor Tsw' is turned off, and the write data is supplied through the right Y selection circuit YSEL '. It At this time, the discharge M on the right side
The OS transistor Csw 'is turned off, and the left discharge MOS transistor Csw is turned on.
When the most significant address bit An is logic 0, the left transfer MOS transistor Tsw is turned on, the right transfer MOS transistor Tsw ′ is turned off, and the write data is supplied through the left Y selection circuit YSEL. . At this time, the discharge MO on the right side
The S-transistor Csw 'is turned on and the left discharge MOS transistor Csw is turned off. The selection operation of the left and right Y selection circuits YSEL, YSEL 'follows the decode output of the Y address decoder YADEC.
Is activated or another supply circuit (not shown) supplies a supply path for write data to the left or right Y selection circuit. The transfer MOS transistors Tsw, Ts
The signal voltage for turning on w'is set to a high voltage in writing, and an example of the control circuit DIVCONT for that is shown in FIG. The voltage Vpp1 in FIG. 41 can be generated using the power supply circuit in FIG. 52 described later.

As a structure to be compared with the structure shown in FIG. 40, there may be mentioned a structure in which an X address decoder is arranged on one end side of a word line. In this case, the size in the word line direction of the memory block defined with the word line as the minimum unit is twice that in FIG. When the configuration of FIG. 40 is compared with that configuration, it contributes to shortening the word line disturb time of the selected block at the time of writing. That is, referring to FIG. 26, the selection block 30 at the time of writing
In some memory cells, the high voltage Vpp is applied to the word line and the write voltage Vp is not applied to the data line. As described above, in the write selection block 30, in the memory cell in which the data line is in the non-selected state in the word line selected state, the potential difference between the control gate and the floating gate becomes large, whereby the charge is controlled from the floating gate. Emitted to the gate,
Attempts to undesirably lower the threshold of the memory cell transistor. This is word line disturb, and the longer the state, the lower the threshold. Therefore, like the data line disturb, it is desirable that the time during which the word line disturb state continues (word line disturb time) is short. In this regard, in the configuration of FIG. 40, assuming that writing is performed in 8-bit units, the number of memory cells exposed to the word line disturb state in the write-selected block is higher than that of the configuration of the comparison target. It is halved. This contributes to shortening the word line disturb time.

FIG. 42 shows an embodiment in which a memory block is provided with redundant words. In the figure, in each of the memory blocks MBa and MBb, redundant word lines WRa and WRb for repairing the defective word line, redundant data lines DR,
And redundant memory cells RC are arranged. By providing the redundant word in the memory blocks MBa and MBb in this way, when the defective word is repaired, the defective word is repaired by using the redundant word in the same block as the memory block to which the repaired defective word belongs. be able to.
For example, if a word in the memory block MBa is defective, the word can be repaired by the redundant word WRa in the memory block MBa. As a result, even if the defective word is replaced by the redundant word, the above-mentioned data line disturb countermeasure can be applied to the redundant word under exactly the same conditions. Further, as the redundant word, as shown in FIG. 43, it is possible to provide memory blocks MBrd and MBrd 'dedicated to redundancy.

FIG. 44 shows an embodiment in which some memory blocks are made into a one-time programmable area (OTP-flash). One-time programmable area conversion means that desired data is written only once. In the figure, the memory block MBc and the memory block MBd are memory blocks which are made into a one-time programmable area. The memory blocks MBc and MBd, which are made into the one-time programmable area, have no difference from the configuration of the other memory blocks. To make a specific memory block a one-time programmable area,
Rewriting of the memory block may be selectively suppressed. For example, it is possible to force a specified bit of an erase register for specifying a memory block targeted for one-time programmable area to a non-selected level by a non-volatile memory element, and write voltage to a word line of the memory block. The path for supplying the power is cut by the non-volatile memory element. As a result, the one-time programmable area memory block and the other memory blocks can share the X address decoder, the Y address decoder, and the data line. At this time, it is easiest to use a transistor similar to the memory cell transistor of the flash memory as the nonvolatile memory element. In the write operation, the data line disturb blocking voltage Vddi is applied to the source lines Vsc and Vsd of the memory block which is made into the one-time programmable area to prevent the data line disturb defect of the memory block. As described above, if the memory block can be partially configured as a one-time programmable area, it is possible to prevent the situation in which data is undesirably rewritten after being once written. For example, the one-time programmable area memory block can be used as a program holding area or as a data holding area where it is necessary to prevent falsification.

FIG. 45 shows a configuration in which some of the memory blocks are made into a mask ROM instead of the one-time programmable area of some of the memory blocks.
In the figure, the memory block MBc and the memory block MBd are areas which are mask ROM. By adopting this configuration, the memory blocks MBc, MBd
Writing to is completely disabled. At the time of writing, memory blocks MBc and MB which are masked to ROM
For d, the high voltage for writing is prohibited from being applied to the word line, and the source lines Vsc and Vsd are biased by the voltage Vddi or the like. When erasing,
Common source line Vs of the memory blocks MBc and MBd
It is prohibited to apply a high voltage for erasing to c and Vsd.

[19] Layout configuration of memory block

FIG. 46 shows an example of the layout configuration for the memory block. The layout configuration shown in the figure has a memory block MBa and a memory block MBb.
This is an example in which the transfer gate circuit TGC is not arranged between and. In the figure, the memory cell includes a control gate 11 integrated with a word line, a floating gate (fg) 8 formed separately under the control gate 11, a drain including an N-type semiconductor region 13 and a P-type semiconductor region 14, and an N-type. It is composed of a source composed of the semiconductor region 13 and the N-type semiconductor region 15. Each memory cell is separated from each other by a thick field insulating film 4. The word lines WL0 to WLi + 2 are separated from each other and formed in parallel to the horizontal direction of the drawing. Data lines DL0 to DL8
Are formed by a first wiring layer 23 such as a first aluminum layer (Al1), are separated from each other, and are arranged in parallel to the vertical direction of the drawing with an arrangement intersecting with the word line. The data line is connected to a drain common to adjacent memory cells via a contact (CONT) 22. The source of the memory cell is composed of N-type semiconductor regions 13 and 15 parallel to the word line, and is connected to the source line SL composed of the first wiring layer 23 via the contact 22 every 8 bits. The source line SL is parallel to the data lines DL0 to DL8. The source line SL in each memory block is cut at the block end, and the source line S of the adjacent memory block is cut off.
Separated from L. On the other hand, the data lines DL0 to D
L8 extends through the adjacent block. Each source line SL in one memory block is connected to a common source line SA, SB composed of a second wiring layer (Al2) such as a second aluminum layer through a through hole (TC) 25 at the block end. Connected. The common source lines SA and SB are arranged below the field oxide film 4 in parallel with the word lines. In this way, the source line is separated for each memory block. The common source lines SA and SB can be arranged on both sides of the block end or in the center of the memory block. Although not shown, each word line is shunted to the second wiring layer 26 arranged above the word line for every 16 bits to reduce the delay component of the word line.

FIG. 47 shows a layout configuration example when a transfer gate circuit is provided between memory blocks. The transfer gate circuit is composed of adjacent memory blocks M.
Between the common source lines SA and SB of Ba and MBb, transfer MOS transistors T0 to T8 as high breakdown voltage N channel type MOS transistors having the first conductor layer 8 as a gate electrode are arranged. In this case, the data line is cut at the adjacent ends of the memory block MBa and the memory block MBb. The cut ends of one of the data lines whose cut ends face each other are connected to the drains of the transfer MOS transistors T0 to T8 via the contacts 22, and the cut ends of the other data lines are connected to the transfer MOS transistors via the contacts 22. T0
Connected to the source of T7. The memory cells located at the ends of the memory blocks facing each other are used as dummy cells, and in this example, the sources are made floating. FIG. 48 shows a configuration in which the drain of the dummy cell is made floating in the configuration of FIG. 47.

FIG. 49 shows a layout configuration example in which the transfer MOS transistors T0 to T7 are substantially increased in size. In this example, the gate widths of the transfer MOS transistors T0 to T7 are increased to prevent the transfer MOS transistors T0 to T7 from lowering the data line potential. That is, in the example of FIG. 49, the transfer MOS transistors T0, T2, T4, T6 are arranged in parallel with the word line on the memory block MBa side, and the transfer MOS transistors T1, T3, T5, T7 are arranged on the memory block MBb side with the word line. Place parallel to. The data line DL0 extending from the memory block MBb side is connected to the transfer MOS transistor T
1 and the transfer MOS transistor T0
And the data line DL0 extending from the memory block MBa side is coupled to the transfer MOS transistor T0. The adjacent data line DL1 extending from the memory block MBa side passes over the transfer MOS transistor T0 and is coupled to the transfer MOS transistor T1, and the data line DL1 extending from the memory block MBb side is coupled to the transfer MOS transistor T1. To be done. Other transfer MOS transistors are similarly coupled to the data line. The number of vertically stacked transfer MOS transistors is not limited to the above-mentioned two, and the maximum number of vertically stacked transfer MOS transistors is the number of data lines between the source lines SL.

[20] Overall flash memory with data line disturb countermeasures

FIG. 50 is a block diagram showing an embodiment of the entire flash memory in which a plurality of memory blocks are formed on a word line basis and a data line disturb countermeasure is provided.
The flash memory shown in the figure is built in a microcomputer. In the figure, reference numeral 210 denotes a memory array in which memory cells each composed of an insulated gate field effect transistor having a two-layer gate structure described in FIG. In the memory array ARY, the control gates of the memory cells are connected to the corresponding word lines, the drain regions of the memory cells are connected to the corresponding data lines, and the source regions of the memory cells are similar to the structure described in FIG. Are connected to common source lines SL1 to SLn for each of the memory blocks MB1 to MBn defined by word line as a unit. The source lines SL1 to SLn of each memory block are individually connected to the erase circuits ERS1 to ERSn. Although n memory blocks MB1 to MBn are shown in the figure, these memory blocks have relatively large storage capacities as shown in FIG. 18, for example.
Large memory blocks (large blocks) LMB0 to LM
B6 and eight small memory blocks (small blocks) SMB0 to SMB7 each having a relatively small storage capacity can be divided. The large memory block is used as a program storage area or a large capacity data storage area. The small memory block is used as a small capacity data storage area.

In FIG. 50, reference numeral 200 denotes an address buffer and address latch circuit, the inputs of which are coupled to the internal address bus of the microcomputer. Reference numeral 201 denotes an X address decoder (XADE) that decodes a row address signal (X address signal) latched by the address buffer and address latch circuit 200 and drives a word line.
C). For example, in the data read operation, the X address decoder 201 drives a predetermined word line with a voltage such as 5V, and in the data write operation, drives the predetermined word line with a high voltage such as 12V. In the data erasing operation, all the outputs of the X address decoder 201 are set to a low voltage level such as 0V. A Y address decoder (YADE) 202 decodes the Y address signal latched by the address buffer and address latch circuit 201.
C). A Y selection circuit (YSEL) 203 selects a data line according to a data line selection signal output from the Y address decoder 202. As for the relationship between the data line and the Y selection circuit, one memory mat corresponds to one I / O as described in FIG. Although not particularly limited, the memory array is divided into 16 memory mats. At this time, each of the memory blocks MB1 to MBn is spread over 16 memory mats. Reference numeral 204 denotes a sense amplifier (SAMP) that amplifies a read signal from the data line selected by the Y selection circuit 203 in the data read operation. According to this embodiment, 16 amplification circuits are included corresponding to the output bits from each memory mat. Two
Reference numeral 05 is a data output latch (DOLAT) that holds the output of the sense amplifier 204. A data output buffer (DOBUFF) 206 outputs the data held by the data output latch 205 to the outside. The output of data output buffer 206 is bit-wise coupled to the 16-bit internal data bus of the microcomputer. According to this example, the maximum read data is 2 bytes. 207
Is a data input buffer (DIBUFF) for fetching write data supplied from the outside. The data input from the data input buffer 207 is held in the data input latch (DILAT) 208. When the data held in the data input latch 208 is “0”, the write circuit (WRIT) 209 supplies the write high voltage to the data line selected by the Y selection circuit 203. The high voltage for writing is supplied to the drain of the memory cell to which the high voltage is applied to the control gate according to the X address signal,
As a result, the memory cell is written.

The erasing circuits ERS1 to ERSn supply a high voltage for erasing to the source line of the designated memory block to collectively erase the memory blocks. The erase block designating register 23 determines which erase circuit performs the erase operation.
Controlled by the 1 set bit. The erase block designation register 231 is the register MBREG described in FIG.
1 and MBREG2. At the time of writing, the erasing circuits ERS1 to ERSn are as described in FIG.
While the ground line GND is applied to the source line of the write selected block, the data line disturb blocking voltage Vddi is applied to the source line of the write unselected block. This control is performed by the non-selected block designating circuit 2 for writing
30 does. Non-selected block designation circuit 230 for writing
Receives the X address signal output from the address buffer and address latch circuit 200, decodes the X address signal, determines the selected block at the time of writing, and instructs the erase circuit of the write selected block to apply the ground potential GND. , The erase circuit of the write non-selected block is instructed to apply the data line disturb blocking voltage Vddi.

In FIG. 50, reference numeral 240 is a control circuit for controlling the timing of the data read operation in the flash memory FMRY, and controlling various timings and voltages for writing and erasing.

FIG. 51 shows an example of the control circuit 240. The control circuit 240 includes a power supply circuit 241, a memory read / write control circuit 242, a register control circuit 243, and a control register 244. The control register 244 has the program / erase control register PEREG described in FIG. Control register 244
The erase signal E, the write signal W, the erase verify signal EV, and the write verify signal WV output from are the E bit of the program / erase control register PEREG,
It corresponds to P bit, EV bit, and PV bit. Figure 1
As described in Section 9, erase / write operations are
It is controlled according to the setting contents of the erase control register PEREG. The register control circuit 243 uses the read / write signal R /
The program / erase control register PEREG and the erase block designation register 231 (MBREG1, MBREG) included in the control register 244 based on W1 and the like.
Read / write control of REG2) is performed. The memory
The read / write control circuit 242, based on the read / write signal R / W2 and the like supplied via the control bus, the data input buffer 207, the data input latch circuit 208, the data output buffer 206, the data output latch circuit 205, The power supply circuit 24 controls the operation of the address buffer and address latch circuit 200 and
1 to control the operation. The power supply circuit 241 receives a power supply voltage Vcc such as 5V and a high voltage Vpp such as 12V,
The voltages Vpp1, VppS, Vcc1 are formed according to the set bits of the program / erase control register PEREG included in the control register 244 and the output control signal of the memory read / write control circuit 242.

FIG. 52 shows an example circuit diagram of the power supply circuit 241. The power supply circuit 241 includes a reference voltage generation circuit 2410, a decoder drive power supply circuit 2411, a source circuit drive power supply circuit 2412, and a sense amplifier drive power supply circuit 2413. Reference voltage generation circuit 24
A resistor 10 divides a high voltage by resistance to generate reference voltages V1 and V2. The decoder drive power supply circuit 2411 generates a voltage Vpp1 for determining the drive voltage of the word line according to the operating state of the flash memory. The operating state of the flash memory is transmitted by the control signal 2414 from the control register 244 or the memory read / write control circuit 242, which controls the internal switch circuit to optimize the value of the voltage Vpp1 according to the operating state. Be converted. An example of the output waveform of the voltage Vpp1 with respect to the internal operation state is shown in FIG. The decoder drive power supply circuit 2
Reference numeral 411 denotes a detection circuit 2415 that detects a decrease in power supply voltage Vcc with respect to a threshold value, and a booster circuit 2416 that boosts the power supply voltage when a decrease in power supply voltage Vcc is detected.
And have. This boosted voltage is used during the read operation during the low voltage operation. The source circuit driving power supply circuit 2412 is a voltage V used for driving the source line or the like.
Generate ppS according to control signal 2414. The sense amplifier drive power supply circuit 2413 generates a voltage Vcc1 used as a drive voltage of the sense amplifier in accordance with the control signal 2414. The voltage waveforms of the voltages VppS and Vcc1 with respect to the internal state of the flash memory are shown in FIG.
3 is shown.

FIG. 54A shows an example of the X address decoder 201. In the figure, a structure corresponding to one word line is shown as a representative. The X address signal includes a predecoder 2010, a decoding unit 2011 that decodes its output, and a driving unit 2012 that drives a word line based on the output of the decoding unit 2011. The predecoder 2010 and the decoding unit 2011 are operated with a power supply voltage Vcc like 5V system. The driving unit 2012 is a high voltage driving system that is driven by a voltage such as the voltage Vpp1. 2013 has a high breakdown voltage N for separating the 5V system and the high voltage system.
It is a channel type MOS transistor.

When adopting the transfer gate circuit TGC as described with reference to FIGS. 33 to 36, the large memory blocks LMB0 to LMB6 correspond to the memory blocks MB1 to MB7 of FIG.
MB0 to SMB7 are memory blocks MB8 to MB8 in FIG.
Corresponds to MBn. And the transfer gate circuit T
Although not shown in FIG. 50, the GC is arranged between the memory blocks MB7 and MB8. FIG. 54B shows an example of the selection circuit 250 that generates the switch signal DT of the transfer gate circuit TGC. The selection circuit 250 receives the voltage Vpp1, the address signal, and the write signal, and cuts off the transfer gate circuit TGC when writing to a large memory block. That is, the signal DT is not particularly limited, but is set to 0V corresponding to the ground potential when writing to the large memory block, and is set to the voltage Vpp1 otherwise.

FIG. 55 shows an example of the erase circuit.
FIG. 56 shows an operation timing chart thereof. The erasing circuits ERS1 to ERSn are supplied with the voltage VppS and the power supply voltage Vdd as operating voltages. The signal E / W * shown in the figure is a signal that is set to 0 level during writing or erasing. When the bit from the erase block designating register supplied to the erase circuit of FIG. 55 is 1 level (erase designating level), the erase signal E also becomes 1 level, and the supply voltage Vs to the source line is set to the voltage VppS. It The voltage VppS at the time of erasing is Vp as described in FIG.
p. As a result, the memory cells are collectively erased in the collective erase selection block. The control signal from the non-selected block during writing supplied to the erase circuit of FIG. 55 is 1 level (instruction level of the non-selected block during writing)
At this time, the write signal W also becomes 1 level, and the supply voltage Vs to the source line is set to the voltage VppS. The voltage VppS at the time of writing is set to the data line disturb blocking voltage Vddi such as 3.5V. As a result, the data line disturb is prevented in the non-selected block at the time of writing.

FIG. 57 shows a timing chart of a series of erase-related operations in the flash memory shown in FIG. 50, and FIG. 58 shows a timing chart of a series of write-related operations in the flash memory shown in FIG. . Before explaining the respective timing charts, the control signals shown in those figures will be described first. Since it is considered necessary for facilitating the understanding, the description here has some contents overlapping with the description of FIG. The control signal FLM is the flash memory FMRY.
Is a signal that specifies the operation mode of the
The operation mode is designated, and "1" designates the second operation mode. The signal FLM is formed based on the mode signals MD0 to MD2, for example. Control signal MS-FLN
Is a selection signal of the flash memory FMRY, and "0" indicates selection and "1" indicates non-selection.
The control signal MS-MISN is a program / erase control register PEREG and an erase block designation register MBR.
It is a selection signal for internal registers such as EG1 and MBREG2. Which one is selected is determined by the address signal PABm. M2RDN is a memory read strobe signal, M2WRN is a memory write strobe signal, MRD
N is the read signal of the flash memory built-in register, MW
RN is a write signal of a register with a built-in flash memory. The memory write strobe signal M2WRN is used for the data input latch circuit D for writing the data to be written in the memory cell.
It is regarded as a strobe signal for writing to ILAT.
The actual writing to the memory cell is started by setting the P bit of the program / erase control register PEREG.

As shown in FIG. 57, a series of operations relating to erasing are roughly classified into setup erase, erase, and erase verify. The setup erase is an operation of writing data for designating a memory block to be erased in a batch to the erase block designation register, and a logical 1 to the E bit of the program / erase control register PEREG.
This is an operation for writing the bit (flag) of. Erase is a collective erase operation of memory blocks, and 1 is set to the E bit.
It is started by setting. The specific processing procedure of the erase operation is the same as that described with reference to FIG. Erase verify is started by clearing the E bit, and in accordance with the contents described with reference to FIG. 23, verify is sequentially performed in byte units from the head address.

As shown in FIG. 58, a series of write operations is roughly classified into a setup program, a program, and a program verify. The setup program writes the data to be written in the data input latch circuit, and the operation of making the address buffer and the address latch circuit show off the memory address to be written,
The operation is to write a bit (flag) of logic 1 to the P bit of the program / erase control register PEREG. The program is an operation of writing the memory cell specified by the latched address according to the data written in the data input latch circuit, and is started by setting 1 in the P bit. The specific processing procedure of the write operation is the same as that described with reference to FIG. Program verification is started by clearing the P bit, and verification is sequentially performed in byte units from the start address according to the contents described with reference to FIG.

The operation timings shown in FIGS. 57 and 58 are basically the same in both the first operation mode and the second operation mode, and the method described in the above items [3] and [4] is adopted. can do. In addition, general-purpose PRO
When rewriting using the M writer, it is possible to use the rewriting support control program prepared in advance in a mask ROM or the like built in the microcomputer to burden the CPU or other lodges built in the microcomputer with a part of the processing. is there. The flash memory shown in FIG. 50 is the microcomputer M described with reference to FIGS.
It goes without saying that it can be applied to a CU, and can also be configured as a single flash memory chip.

[21] Method for manufacturing flash memory

59 to 65 are vertical sectional views of the device in the process of manufacturing various transistors for forming a flash memory or a microcomputer incorporating the flash memory. The transistors shown in each figure are
In order from the left side of the drawing, memory cell transistors of flash memory, high breakdown voltage NMOS and PMOS used for writing and erasing flash memory, logic system NMOS and PMOS forming peripheral logic such as CPU, and erasing or reading of flash memory There are six types of Zener diodes used to generate the reference voltage.

(A); Step shown in FIG. 59 (A) The N-type well 2 and the P-type well 3 are formed on one main surface of the P-type semiconductor substrate 1 by a known technique.

(B); Process shown in FIG. 59 (B) The P-type channel stopper layer 5 is formed in the substantially same process as the thick field insulating film 4 by a known technique. Then, the first gate insulating film 6 of the high breakdown voltage NMOS (N-channel type MOS transistor) and PMOS (P-channel type MOS transistor) is formed. The gate insulating film 6 is formed at a temperature of 850 to 950 ° C. by a thermal oxidation method.
It is formed to have a thickness of 0 to 50 nm.

(C); Step shown in FIG. 59 (C) Using the photoresist as a mask, the first gate insulating film 6 in the flash memory formation region is removed to expose the surface of the P-type semiconductor substrate 1. .

(D); 10 nm at a temperature of 800 to 850 ° C. by the process thermal oxidation method shown in FIG.
An insulating film is formed to some extent. Then, the insulating film described in 1 above is removed by wet etching. As a result, when the mask such as the photoresist in (C) is removed, P in the flash memory formation region is removed.
Contamination adhering to or penetrating the exposed surface of the mold semiconductor substrate 1 can be removed. A tunnel insulating film 7 of a flash memory is newly formed. The tunnel insulating film 7 is 800 to 85 by the thermal oxidation method.
It is formed to have a thickness of 8 to 12 nm at a temperature of 0 ° C. At this time, the first gate insulating film 6 has a film thickness of 20 to 40 nm because it passes through the steps (D) to. Next, the first gate electrode for the floating gate electrode of the flash memory and the gate electrodes of the high breakdown voltage NMOS and PMOS
The conductor layer 8 is formed. The first conductor layer 8 diffuses phosphorus by thermal diffusion into polycrystalline silicon having a film thickness of about 200 nm deposited at a temperature of about 640 ° and ρs = 60 to 100Ω / □.
To be formed. In order to reduce the erase variation of the flash memory, it is necessary to reduce the grain size of the polycrystalline silicon, and the temperature of thermal diffusion is set to 900 ° C. or less and the grain size is set to 0.1 μm or less.

(E); Process shown in FIG. 61. The interlayer insulating film 9 between the floating gate electrode and the control gate electrode of the flash memory is formed. The interlayer insulating film 9 is a laminated film of a silicon oxide film and a silicon nitride film, and from the first conductor layer 8 side, a two-layer film of a silicon oxide film / silicon nitride film and a silicon oxide film / silicon nitride film / silicon oxide film. It is a four-layer film of film / silicon nitride film.
Here, the silicon oxide film on the first conductor layer 8 is formed by thermal diffusion to a thickness of 10 to 20 nm at a temperature of 850 to 950 °. The silicon nitride film on the silicon oxide film is formed to a thickness of 20 to 30 nm by the CVD method.
In the case of the four-layer film, the silicon oxide film of the silicon nitride film is 2 to 5 n at a temperature of 900 to 950 ° by a thermal oxidation method.
It is formed to a film thickness of m. Then, the silicon nitride film on the silicon oxide film of 2 to 5 nm has a thickness of 10 to 1 by a CVD method.
It is formed with a film thickness of 5 nm. The total film thickness of the two-layer film and the four-layer film is formed to be 20 to 30 nm in terms of silicon oxide film. Logic system NMOS using photoresist as a mask
Also, the interlayer insulating film 9 in the PMOS and Zener diode forming region is removed. The masks of the complement and the register are removed. Using the uppermost silicon nitride film of the interlayer insulating film 9 as a mask, wet etching is performed to form a logic NMO.
The S and PMOS and the first gate insulating film in the Zener diode formation region are removed to expose the surface of the P-type semiconductor substrate 1.

(F): Step shown in FIG. 62 By the same method as in the above-mentioned (D), the contamination adhered to or invaded the exposed surface is removed. At this time, an insulating film having a thickness of 10 to 20 nm is formed at 800 to 850 ° C. by a thermal oxidation method. Then, the second gate insulating film 10 serving as the gate insulating film of the logic NMOS and the PMOS is formed. The second gate insulating film 10 is formed by a thermal oxidation method in a wet atmosphere at 800 to 850 ° C. to a film thickness of 10 to 20 nm. Next, the second conductor layer 11 to be the control gate electrode of the flash memory and the gate electrodes of the logic NMOS and PMOS is formed. The second conductor layer is sequentially from the bottom,
It has a laminated structure of polycrystalline silicon film / refractory metal silicide film / silicon oxide film. Here, the polycrystalline silicon film is deposited at a temperature of about 640 ° C.
A film of ρs = 60 to 100 Ω / □ in which phosphorus is diffused by thermal diffusion at 900 ° C. or less in polycrystalline silicon having a film thickness of 200 nm is used. The refractory metal silicide film is a WSix film (x = 2.5 to 3.
0), a film thickness of 100 to 150 nm, and ρs = 2 to 15 Ω / □ after heat treatment. The silicon oxide film is formed by CVD to have a film thickness of 100 to 150 nm. This silicon oxide film is a protective film of a polycrystalline silicon film / refractory metal silicide film which actually becomes a control gate electrode or a gate electrode, and protects the refractory metal from damage such as ion implantation or dry etching. Control gate electrode 11 / of flash memory by dry etching using photoresist etc. as a mask
The interlayer insulating film 9 / floating gate electrode 8 is formed in a self-aligned manner. The tunnel insulating film 7 damaged by the dry etching is removed by wet etching using the first conductor layer 8 and the second conductor layer 11 as masks, and the P-type semiconductor substrate 1 in the source and drain formation regions of the flash memory is removed. Expose the surface. Then, the insulating film 12 is formed on the entire surface. The insulating film 12 is a protective film, and is formed of a silicon oxide film by a CVD method.
It is formed with a film thickness of ˜20 nm. Using the second conductor layer 11 as a mask, the N-type semiconductor region 13 and the P-type semiconductor layer 14 are formed in the source and drain regions of the flash memory. Here, the N-type semiconductor region 1
3 is formed by implanting arsenic at an acceleration energy of 50 to 80 kev at about 1 × 10 ¹⁵ cm ⁻² by an ion implantation method. The P-type semiconductor layer 14 is made of boron by ion implantation at an acceleration energy of 20 to 60 keV and a concentration of 1 × 10 ¹³ to.
It is formed by implanting 1 × 10 ¹⁴ cm ^-2 .

(G); Process shown in FIG. 63 Using the photoresist or the like as a mask, the gate electrodes of the logic NMOS and PMOS are formed by dry etching. At this time, the flash memory area is not etched because it is covered with the mask. In addition, high breakdown voltage NM
The OS, the PMOS, and the second conductor layer 11 in the Zener diode formation region are removed. After removing the mask such as photoresist, 900 ~ 95
The heat treatment at about 0 ° C. reduces the resistance of the refractory metal silicide of the second conductor layer 11 (ρs = 2 to 15Ω / □). Next, using the photoresist or the like as a mask, the N-type semiconductor region 15 is formed in the source region of the flash memory. N
The type semiconductor region 15 is formed by implanting phosphorus at an acceleration energy of 50 to 80 kev at about 5 × 10 ¹⁵ cm ⁻² by an ion implantation method. Then, the N-type semiconductor region 15 is thermally diffused by a heat treatment at about 950 ° C. for about 30 minutes to 2 hours to cover the P-type semiconductor layer 14 in the source region. As a result, the drain region has a double structure of the N-type semiconductor region 13 and the P-type semiconductor layer 14 for controlling the threshold value and improving the writing efficiency. The source region is an N-type semiconductor region 13 made of arsenic and an N-type semiconductor region 15 made of phosphorus for improving the source breakdown voltage at the time of erasing.
It has a double structure. As an erasing method, the P-type semiconductor substrate 1 is formed on the control gate electrode 11 of the flash memory.
In the case of sector erasing in which a negative bias is applied to the entire channel region below the floating gate electrode 8, it is not necessary to form the N-type semiconductor region 15 on the source side. Using a photoresist as a mask, phosphorus is ion-implanted at an acceleration energy of 50 kev of 2 to 4 × 10 ¹³ cm 2.
^-2 implantation is performed to form an N-type semiconductor region 16. Boron is implanted into the entire surface by an ion implantation method at an acceleration energy of 15 kev in an amount of 1 to 2 × 10 ¹³ cm ⁻² to form a P type semiconductor region 17. Boron is also implanted in the NMOS region, but since it has a high phosphorus concentration, it substantially functions as an N-type semiconductor.

(H): After a silicon oxide film is formed on the entire surface by the process CVD method shown in FIG. 64,
The sidewall 18 is formed by dry etching. Ion implantation using a photoresist as a mask
Arsenic with acceleration energy of 60 kev 1-5 × 10 ¹⁵ cm
^{-2 is} implanted to form the N-type semiconductor region 19, and boron is accelerated at an energy of ¹⁵ kev in an amount of 1 to 2 × 10 ¹⁵ cm ^-2.
Implantation is performed to form a P-type semiconductor region 20. The Zener diode is formed of the N-type semiconductor region 19 and the P-type semiconductor region 20, and has a Zener voltage of 3 to 4V.

(I); The process insulating film 21 shown in FIG. 65 is formed. The insulating film 21 is composed of a silicon oxide film having a thickness of about 150 nm formed by the CVD method and 400 to 50
It is formed of a BPSG film having a film thickness of 0 nm. After forming the contact hole 22, the second wiring layer 23 is formed. The first wiring layer 23 is formed of a laminated film of refractory metal silicide and aluminum. The first wiring layer 23 is also used as a data line and a source line of the flash memory. An insulating film 24 is formed on the first wiring layer 23. The insulating film 24 is a laminated film of a silicon oxide film formed by the plasma CVD method / spin-on-glass film / a silicon oxide film formed by the plasma CVD method. After forming the through hole 25, the second wiring layer 26 is formed. The second wiring layer 26 has the same film structure as the first wiring layer 23. The second wiring layer 26 is used as a shunt of the second conductor layer 11 which becomes a word line of the flash memory. The final passivation film 27 is formed and completed. The final passivation film 27 is a laminated film of a silicon oxide film formed by a CVD method or a plasma CVD method and a silicon nitride film formed by a plasma CVD method.

[22] Structure of semiconductor substrate / well corresponding to sector erase

FIG. 6 shows a method for erasing the flash memory.
The voltage conditions shown in 6 are conceivable. At this time, when sector erase (a negative bias is applied to the control gate electrode with respect to the semiconductor substrate) is adopted and the generation of the negative bias is complicated in terms of the circuit, the control gate electrode = GN
D, substrate part = positive bias, and negative bias can be effectively erased. At this time, it is necessary to separate the substrate portion in the flash memory cell formation region. A semiconductor substrate and a well structure therefor will be described with reference to FIGS. 67 to 69.

(A); The N-type well 2 and the P-type well 3 are formed on one main surface of the structure N-type semiconductor substrate 101 shown in FIG. 67 for separation. For that purpose, as shown in FIG. 67, an N-type semiconductor substrate 101 is used instead of the P-type semiconductor substrate 1. (B); Separation is performed by the double well structure (P-type well 3 / N-type well 2 / P-type semiconductor substrate 1) shown in FIG. In this case, the N-type well 2 is formed on one main surface of the P-type semiconductor substrate 1. At this time, the N-type well 2 is also formed in the flash memory formation region, and the P-type well 3 is formed so as to be shallower than the N-type well 2. (C); structure double well structure shown in FIG. 69 (P-type well 3 / N-type well 102 / P
The semiconductor substrate 1) is separated. In this case, a deep N-type well 102 is formed in the flash memory formation region of one main surface of the P-type semiconductor substrate 1, and the subsequent manufacturing method is the same as in the case of FIG.

According to the above embodiment, there are the following effects.

(1) The flash memory F built in the microcomputer MCU first in a stage before mounting the microcomputer MCU in a required system.
When writing information to MRY, by designating the second operation mode, information can be written efficiently under the control of an external writing device such as the PROM writer PRW. In addition, microcomputer MCU
By designating the first operation mode in, the information stored in the flash memory FMRY can be rewritten with the microcomputer MCU mounted in the system. At this time, the batch erasing function can shorten the rewriting time.

(2) By providing a plurality of memory blocks (LMB, SMB) having mutually different storage capacities as batch erasable units in the flash memory FMRY, each memory block has its storage capacity. Depending on the requirement, for example, a program, a data table, control data, etc. can be held. That is, data having a relatively large amount of information can be written in a memory block having a relatively large storage capacity, and data having a relatively small amount of information can be written in a memory block having a relatively small storage capacity. In other words, it is possible to use a memory block having a storage capacity commensurate with the amount of information to be stored. Therefore, it is possible to prevent the situation where the erase unit is suitable for the program area but too large for the data area, which makes it difficult to use. In addition, even if a required memory block is erased all at once for rewriting a part of the information held in the flash memory, there is no waste of rewriting again after erasing the information group that does not substantially require rewriting. It can be prevented as much as possible.

(3) By providing a memory block whose storage capacity is equal to or less than the storage capacity of the built-in RAM among the plurality of memory blocks, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory block. Like

(4) In the above (3), when the flash memory is rewritten in the mounted state of the microcomputer, the information of the memory block to be rewritten is transferred to the internal RAM, and only a part of the information to be rewritten is received from the outside. By performing rewriting on the RAM and then rewriting the flash memory, it is not necessary to overlap the information that does not need to be rewritten internally and is not transferred from the outside before rewriting. It is possible to eliminate waste of information transfer for rewriting a copy.

(5) Since the batch erase time of the flash memory does not become so short even for a small memory block,
Although the flash memory itself cannot be rewritten in real time in synchronization with the control operation by the microcomputer MCU, it is rewritten in real time by using the built-in RAM as a work area or a data buffer area for rewriting a memory block. The same data can be obtained in the memory block as a result.

(6) Register MBRE for rewritably holding designation information of memory blocks to be collectively erased
By incorporating G in the flash memory FMRY, the memory block to be collectively erased can be easily specified from inside or outside the microcomputer MCU (internal central processing unit, external PROM writer) by the same procedure.

(7) With each of the above effects, the usability of the flash memory FMRY incorporated in the microcomputer MCU can be improved.

(8) As shown in FIG. 25, one bit of input / output data corresponds to one memory mat. By adopting such a configuration that one memory mat has 1 I / O, the common data line CD can be divided for each memory mat, and a long distance is provided so as to penetrate all the memory mats. Since it does not need to be extended, the parasitic capacitance of the common data line CD can be reduced, which contributes to high-speed access and low-voltage operation.

(9) When the memory block is defined in units of word lines, the storage capacity of the minimum memory block in the entire memory array ARY is the storage capacity of one word line. This does not change regardless of the number of parallel input / output bits of the flash memory. Therefore, it is easier to reduce the storage capacity of the minimum memory block by defining the memory block in units of word lines, and in particular, the input / output of data in units of bytes or words such as that built in a microcomputer is possible. In the case of such memory, the minimum size of the memory block is reduced significantly. This contributes to further improvement in usability of a flash memory incorporated in a microcomputer and further to improvement in efficiency of rewriting small-scale data in memory block units.

(10) As shown in FIG. 26, when a voltage Vddi such as 3.5 V is applied to the source of the memory cell in the unselected block for writing to raise the potential on the source side, the memory cell It is possible to prevent the data line disturbance in which the threshold value of the transistor is reduced.

(11) In order to prevent a data line disturb defect, it is effective to shorten the data line disturb time as much as possible. At this time, the data line disturb time received by the small memory block due to the writing accompanying the rewriting of the memory block having the large storage capacity becomes relatively long as compared with the opposite case. Focusing on this, the Y selection circuit YSE is placed across the transfer gate circuit TGC.
The memory block MBb on the L side is a large memory block having a relatively large storage capacity, and the memory block MB on the opposite side is
Let a be a small memory block with a relatively small storage capacity. As a result, the data line disturb time received by the memory cells of the memory block MBb due to the writing of the memory block MBa is smaller than that in the case where the memory block MBa is a large memory block and the memory block MBb is a small memory block. It is much shorter when the memory block MBb is a small memory block and the memory block MBb is a large memory block. As a result, the malfunction prevention due to the data line disturb becomes more complete.

(12) By arranging the dummy word lines DWA and DWB and the dummy cells DC0 to DC6 at the end of the memory block separated by the transfer gate circuit TGC, the dimensional variation of the word line and the control gate in the vicinity of the transfer gate circuit TGC. Can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the peripheral circuit incorporated in the microcomputer is not limited to the above-mentioned embodiment, but can be changed as appropriate. The memory cell transistor of the flash memory is not limited to the stacked gate structure MOS transistor of the above embodiment, and it is also possible to use a FLOTOX type memory cell transistor using the tunnel phenomenon for the write operation. In the above-described embodiment, control of both erasing and writing to the flash memory is performed with reference to FIGS.
However, the present invention is not limited to this. For example, batch erasing that takes a relatively long time may be controlled by built-in dedicated hardware of the flash memory. You may For example, the dedicated hardware is E bit or E
A control logic for controlling the setting and clearing of the V bit and verifying the erased state is provided. The configuration in which the control logic for batch erasing is built in the flash memory improves the usability for the user in that the software load for batch erasing is reduced, but the control logic increases the area. Regarding the contents of items [1] to [7], the unit of collective erasure may be a memory block having a common source line or a memory block having a common word line for erasing. Is selected depending on the polarity of the erase voltage or the number of memory cells connected to a single word line and the single data line when the storage capacity of the batch erase unit is to be minimized. It can be determined in consideration of the situation such as which one is smaller than the number of connected memory cells. The size of the memory block is not limited to the fixed size as in the above embodiment. For example, the size can be made variable according to the setting of the control register or the instruction of the mode signal.
For example, when a batch erase voltage is applied with the word line as the minimum unit, the operation of the driver for driving the word line with the erase voltage may be selected according to the setting of the control register or the instruction of the mode signal. Further, as a division mode of the memory block, as shown in FIG. 24, the whole is divided into a plurality of large blocks LMB0 to 7, and each of the large blocks is divided into a plurality of small blocks SMB0 to SMB.
It is also possible to divide into MB7 so that large blocks or small blocks can be collectively erased. In addition, in a memory cell transistor of a flash memory, its source and drain may be understood as a relative one determined by an applied voltage.

The present invention is a flash memory which can be programmed by performing batch erasing at least in memory block units,
Further, the present invention can be widely applied to a microcomputer provided with a central processing unit and an electrically rewritable flash memory on a single semiconductor chip.

[0183]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the microcomputer according to the present invention has the first operation mode and the second operation mode, a relatively large amount of information such as initial data or an initial program before mounting the microcomputer in the system, It can be written efficiently with a general-purpose PROM writer. Furthermore, when tuning the data while operating the system in which the microcomputer is mounted,
In addition, when it is necessary to change the data or program while the microcomputer is installed in the system, such as program bug countermeasures or program changes due to system version upgrade, flash without removing the microcomputer from the installed system. The memory can be rewritten.

By providing a plurality of memory blocks having mutually different storage capacities as batch erasable units in the flash memory, data having a relatively large amount of information can be stored in a memory block having a relatively large memory capacity. In addition, data with a relatively small amount of information can be written in a memory block with a relatively small storage capacity,
A memory block having a storage capacity commensurate with the amount of information to be stored can be used. Therefore, it is possible to prevent the situation where the erase unit is suitable for the program area but too large for the data area, which makes it difficult to use. In addition, even if a required memory block is erased all at once for rewriting a part of the information held in the flash memory, there is no waste of rewriting again after erasing the information group that does not substantially require rewriting. It can be prevented as much as possible.

Built-in RAM of a plurality of memory blocks
By providing a memory block whose storage capacity is less than or equal to, the built-in RAM can be used as a work area or a data buffer area for rewriting the memory block. Under such conditions, when the flash memory is rewritten in the mounted state of the microcomputer, the information of the memory block to be rewritten is transferred to the built-in RAM, and only a part of the information to be rewritten is received from the outside and the data is rewritten on the RAM. By rewriting the flash memory after rewriting, it is not necessary to overlap the information that does not need to be rewritten stored internally before rewriting and to receive it from the outside. The waste of information transfer can be eliminated. In addition, when tuning the data held in the flash memory, the built-in R
The AM address is overlapped with the address of the memory block of the flash memory, tuning is performed on the RAM, and the tuning result is transferred to the corresponding memory block of the flash memory to synchronize with the control operation by the microcomputer in real time. Even if the flash memory itself cannot be rewritten, the same data as that rewritten in real time can be obtained in the memory block as a result.

By incorporating a register for rewritably holding the designation information of the memory block to be collectively erased in the flash memory, the memory block to be collectively erased can be easily designated from inside or outside the microcomputer by the same procedure. become able to.

By the respective effects described above, the usability of the flash memory built in the microcomputer can be improved.

When a memory block is defined in units of word lines, the storage capacity of the minimum memory block is the storage capacity of one word line, regardless of the number of parallel input / output bits. Therefore, it is easier to reduce the storage capacity of the minimum memory block by defining the memory block in units of word lines than in the case of defining the memory block in units of data lines. In the case of a memory in which data is input and output in units of bytes or words, the minimum size of the memory block is significantly reduced. This contributes to further improvement of usability of a flash memory incorporated in a microcomputer and further improvement of rewriting efficiency of small-scale data in memory block units.

In the write non-selected block, when the source potential of the memory cell is increased by applying the second potential such as the data line disturb blocking voltage to the source line of the memory cell,
The electric field between the sources is weakened, which prevents the holes of the electron-hole pair generated near the drain from becoming hot holes, which contributes to the reduction of the threshold value of the nonvolatile memory element and the prevention of data line disturb failure. .

In order to prevent a data line disturb defect, it is effective to shorten the data line disturb time as much as possible. At this time, however, a small memory block is affected by the writing accompanying the rewriting of the memory block having a large storage capacity. The data line disturb time becomes relatively large as compared with the opposite case. Focusing on this, using the arrangement in which the memory block on the side of the Y selection circuit is a large memory block and the memory block on the opposite side is a small memory block across the transfer gate circuit is relatively effective from the Y selection circuit. Compared to the case where the arrangement of the large memory block and the small memory block is reversed, the data line disturb time received by the memory cells of the memory block relatively close to the Y selection circuit due to the writing of the distant memory block is
Make it much shorter. Due to such a layout relationship between the large memory block and the small memory block, malfunction prevention due to the data line disturbance can be further perfected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a microcomputer that employs a full-face flash memory.

FIG. 2 is a block diagram of an embodiment of a microcomputer that uses a mask ROM together with a flash memory.

FIG. 3 is a block diagram focusing on rewriting of a flash memory by a general-purpose PROM writer.

FIG. 4 is a block diagram focusing on rewriting of a flash memory under CPU control.

FIG. 5 is a memory map of an example of a microcomputer that is an all-flash memory.

FIG. 6 is an example memory map of a microcomputer having a mask ROM together with a flash memory.

FIG. 7 is a diagram illustrating a schematic example control procedure of erasing.

FIG. 8 is an explanatory diagram of a schematic example control procedure of writing.

FIG. 9 is an explanatory diagram of an example of a method for dealing with real-time rewriting of the flash memory.

FIG. 10 is an explanatory diagram illustrating an example of a method for efficiently rewriting a part of a memory block of a flash memory.

FIG. 11 is a diagram illustrating the principle of a flash memory.

12 is an explanatory diagram of a configuration principle of a memory cell array using the storage transistor of FIG.

FIG. 13 is an explanatory diagram showing an example of voltage conditions for an erase operation and a write operation for a memory cell.

FIG. 14 is a circuit block diagram of an example of a flash memory in which a plurality of memory blocks are formed in units of data lines and the storage capacities of the memory blocks are different.

15 is a block diagram of a detailed embodiment of a microcomputer corresponding to the microcomputer of FIG.

16 is a plan view showing a state in which the microcomputer shown in FIG. 15 is packaged.

17 is an overall block diagram of a flash memory incorporated in the microcomputer of FIG.

FIG. 18 is an explanatory diagram illustrating an example of a division mode of a memory block.

FIG. 19 is a diagram illustrating an example of a control register.

FIG. 20 is a timing chart of an example of a memory read operation in a flash memory.

FIG. 21 is a timing chart of an example of a memory write operation in a flash memory.

FIG. 22 is a detailed example flowchart of a write control procedure.

FIG. 23 is a detailed example flowchart of an erase control procedure.

FIG. 24 is an explanatory diagram showing another example of a memory block division mode.

FIG. 25 is a memory mat configuration diagram of an example of a flash memory in which a plurality of memory blocks are formed in units of word lines and the storage capacities of the memory blocks are different.

FIG. 26 is an explanatory diagram showing an example of voltage conditions for a data line disturb countermeasure for a non-selected block for writing.

FIG. 27 is a diagram illustrating the principle of occurrence of data line disturbance and its countermeasure.

FIG. 28 is an explanatory diagram regarding changes in the threshold value of the memory cell with respect to the data line disturb time.

FIG. 29 is a circuit diagram for explaining a correlation of a data line disturb time between a memory block having a small storage capacity and a memory block having a large storage capacity.

FIG. 30 is an explanatory diagram of correlation of data line disturb time between a memory block having a small storage capacity and a memory block having a large storage capacity.

FIG. 31 is a circuit diagram of an embodiment of a memory array in which transfer gate circuits for selectively separating data lines are provided between memory blocks.

FIG. 32 is an explanatory diagram collectively showing an example of voltage conditions for measures against data line disturbance.

FIG. 33 is an example circuit diagram in which dummy word lines are arranged between a memory block and a transfer gate circuit.

FIG. 34 is another circuit diagram in which dummy word lines are arranged between the memory block and the transfer gate circuit.

FIG. 35 is still another circuit diagram in which dummy word lines are arranged between the memory block and the transfer gate circuit.

FIG. 36 is an explanatory diagram of a memory array in which two memory blocks are arranged on each side of the transfer gate circuit.

FIG. 37 is a circuit diagram showing an example of a memory array configured by sequentially increasing the number of word lines in a memory block that can be collectively erased.

FIG. 38 is an explanatory diagram of an example of a memory array in which transfer gate circuits are arranged between a large memory block group and a small memory block group.

FIG. 39 is a circuit diagram showing an example of a memory array that employs a main data line and a sub data line as a data line structure.

FIG. 40 is an explanatory diagram of an embodiment in which batch erasable memory blocks are arranged on the left and right of an X address decoder.

41 is an explanatory diagram of an example of the control circuit of FIG. 40.

FIG. 42 is an explanatory diagram of an embodiment in which a memory block is provided with a redundant word.

FIG. 43 is an explanatory diagram of an embodiment in which a memory block dedicated to redundancy is provided.

FIG. 44 is an explanatory diagram of an embodiment in which some memory blocks are made into a one-time programmable area.

FIG. 45 is an explanatory diagram of an embodiment in which some memory blocks are mask ROM.

FIG. 46 is an explanatory diagram of an example layout pattern of a memory block.

FIG. 47 shows a transfer gate MO between memory blocks.
It is a layout pattern explanatory view when an S transistor is provided.

48 is a pattern explanatory diagram when the drain of the dummy cell is set to a floating state in the configuration of FIG. 47. FIG.

FIG. 49 is an explanatory diagram of a layout pattern in which the size of a transfer MOS transistor is substantially increased.

FIG. 50 is a block diagram of an embodiment of the entire flash memory provided with a data line disturb countermeasure when a plurality of memory blocks are formed in word line units.

51 is a detailed block diagram of a control circuit included in the flash memory of FIG. 50.

52 is a detailed explanatory diagram of a power supply circuit included in the flash memory of FIG. 50. FIG.

53 is an output voltage waveform diagram formed by the power supply circuit of FIG. 52.

54 is a detailed explanatory diagram of an X address decoder included in the flash memory of FIG. 50. FIG.

55 is a detailed explanatory diagram illustrating an example of an erase circuit included in the flash memory in FIG. 50.

56 is an operation timing chart of the erase circuit of FIG. 55.

57 is a timing chart of a series of erase-related operations in the flash memory shown in FIG.

58 is a timing chart of a series of write-related operations in the flash memory shown in FIG.

FIG. 59 is a first vertical section of a device in a process of manufacturing various transistors for configuring a flash memory or a microcomputer including the flash memory.

FIG. 60 is likewise a second longitudinal section of the device.

FIG. 61 is likewise a third vertical cross-sectional view of the device.

FIG. 62 is likewise a fourth vertical cross-sectional view of the device.

FIG. 63 is likewise a fifth vertical cross-sectional view of the device.

FIG. 64 is likewise a sixth vertical cross-sectional view of the device.

FIG. 65 is likewise a seventh longitudinal section view of the device.

FIG. 66 is an explanatory diagram of an erase method of the flash memory.

FIG. 67 is a vertical cross-sectional view for explaining the structure of a semiconductor substrate / well corresponding to sector erase.

FIG. 68 is a vertical cross-sectional view for explaining another structure of the semiconductor substrate / well corresponding to the sector erase.

FIG. 69 is a vertical sectional view for explaining still another structure of the semiconductor substrate / well corresponding to the sector erase.

[Explanation of symbols]

MCU Microcomputer CHP Semiconductor chip FMRY Flash memory LMB Large memory block SMB Small memory block CPU Central processing unit RAM Random access memory CONT Control circuit MASKROM Mask read only memory MODE mode signal Pmode mode signal input terminals MD0 to MD2 modes Signals PORTdata port PORTaddr port PORTcont port socket socket PRW general-purpose PROM writer ABUS address bus DBUS data bus ARY1 to ARY7 memory mat MC memory cells WL0 to WLn word lines DL0 to DL7 data lines SL1, SL2 source lines B1, B2 erase block designation registers Bits PORT1 to PORT12 Ports ED0 to ED7 Input / output data EA0 to EA16 with the ROM writer Input address signal CE * chip enable signal OE * output enable signal WE * write enable signal FCONT control circuit CREG control register NBREG erase block designation register PEREG program / erase control register E Erase bit EV Erase verify bit P Program bit PE Program verify bit ERASEC Erase circuit LMB0 to LMB6 Large memory block SMB0 to SMB7 Small memory block 20 Erase selected block 21 Erase unselected block Vddi Data line disturb blocking voltage SLwn, SLwm Source line MBa , MBb Memory block TGC Transfer gate circuit DT Control signal YSE Y selection circuit MB1~MBn memory block ERS1~ERSn erase circuit 230 writes the time of non-selection block designating circuit 231 erase block designation register 250 select circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kiyoshi Matsubara 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Masaaki Terasawa 5-chome, Mizumizumoto-cho, Kodaira-shi, Tokyo No. 20 No. 1 within Hitachi Ultra LSI Engineering Co., Ltd. (56) Reference JP-A-3-230397 (JP, A) JP-A-3-173999 (JP, A) JP-A-60- 38800 (JP, A) JP-A-2-289997 (JP, A) JP-A-3-105795 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/02

Claims (10)

(57) [Claims] 1. A memory array including a plurality of memory cells including a non-volatile memory element having a source, a drain, and a control gate, a plurality of word lines, a plurality of data lines, a plurality of source lines, and a plurality of source lines. Source voltage control means, the plurality of word lines extend in a row direction in parallel with each other, and the control gates of the memory cells arranged in one row are commonly connected to each word line. The data lines extend in the column direction in parallel with each other, the drains of the memory cells arranged in one column are commonly connected to the data lines, and the plurality of source lines extend in the row direction. A source of the memory cells in an array of at least one row is connected in common to the memory cells, and the memory cells in the array of at least one row form a memory block, Memory blocks, the first memory block group, disposed between the different second time including a memory block group, data lines of the first memory block group of data lines and a second memory block group from that The transfer gate circuit, and a selection circuit provided so as to sandwich the first memory block group between the transfer gate circuit and the transfer gate circuit, the selection circuit selecting a data line during a write operation / read operation. A control circuit for turning off the transfer gate circuit when writing to the memory block, and turning on the transfer gate circuit when writing to the second memory block. When writing to the first memory block, the source line of the second memory block is connected to the first memory block. A voltage level higher than the source lines of the at the time of writing to the second memory block, the first of the source lines of the memory block second
Flash memory comprising means for setting the voltage level or ground level higher than the source line of the memory block. 2. The plurality of source voltage control means further comprises:
2. The flash memory according to claim 1, wherein, during an erase operation, an erase potential having a level different from that at the time of the write is applied to a source line of a memory block to be collectively erased. 3. A first and a second semiconductor region formed in a first surface portion of a semiconductor substrate, and a first of the semiconductor substrate.
And a non-volatile memory element having a floating gate formed on the second surface portion between the second semiconductor regions and being insulated therefrom, and a control gate formed on the floating gate and insulated from the floating gate. A memory cell array in which a plurality of memory cells are arranged in a matrix, and a plurality of memory cells extending in parallel in the row direction on the semiconductor substrate and controlling each row of memory cells. A first conductor to which a gate is commonly connected and a plurality of first memory cells extending in parallel in the column direction above the semiconductor substrate are provided. A second conductor to which semiconductor regions are commonly connected; and a plurality of second memory cells, each of which extends in the row direction above the semiconductor substrate and each of which extends at least one row. Conductor region are commonly connected, they at least
A common conductor in which the memory cells of the row form a memory block, and a common voltage formed in the semiconductor substrate and provided for each memory block to generate a common voltage having at least first and second voltage values. A plurality of common voltage control circuits, and a control signal indicating which one of the memory blocks is to be the target of the erase / write operation, which is supplied to the plurality of common voltage control circuits. The voltage control circuit applies a common voltage depending on the control signal to the associated common conductor, and the second voltage is applied to the common conductor of the memory block that does not include the memory cell selected for writing.
Write operation is performed by applying a common voltage having a voltage value of 1 to generate a control signal for performing a batch erase operation by applying the common voltage having the first voltage value to the common conductor of the memory block selected in the batch erase operation. An electrically rewritable flash memory having a control circuit according to claim 1, wherein the memory block includes a first memory block group and a second memory block group different from the first memory block group, The transfer gate circuit disposed between the second conductor of the memory block group and the second conductor of the second memory block group , and the first memory block group between the transfer gate circuit and the transfer gate circuit. A selection circuit for selecting the second conductor at the time of writing / reading operation, and the transfer gate at the time of writing to the first memory block. A control circuit for turning off the circuit and turning on the transfer gate circuit at the time of writing to the second memory block, wherein the control circuit at the time of writing to the first memory block The common conductor of the second memory block is set to a higher voltage level than the common conductor of the first memory block, and the common conductor of the first memory block is set to the second memory when writing to the second memory block. A flash memory comprising means for setting a voltage level or a ground level higher than the common conductor of the block. 4. The flash memory according to claim 3, wherein the second voltage value is equal to or lower than the voltage on the second conductor selected in the write operation. 5. Both are formed in the semiconductor substrate,
The memory block further includes a gate circuit and a second conductor selection circuit that selects one of the second conductors, and the plurality of memory blocks have a simple storage capacity when viewed in the length direction of the second conductor. The gate circuit and the second selection circuit are arranged such that at least one of the memory blocks is sandwiched between them and the sandwiched memory block is other than the memory block having the smallest capacity. The sandwiched memory blocks form a first memory block group, and the other memory blocks form a second memory block group, and the second conductor and the second memory block in the first memory block group are formed. The second conductors of the memory block group are interconnected by the gate circuit so that the second memory block group is inactive when the gate circuit is in the non-conductive state. Flash memory according to claim 3, characterized in that made. 6. A first dummy cell row and a second dummy cell row formed in the substrate between the first memory block group and the gate circuit and between the gate circuit and the second memory block group, respectively. Furthermore, it is provided to suppress abrupt changes in the substantially periodic pattern of the memory cells and the first conductor due to the gate circuit provided between the first and second memory block groups. 6. The flash memory according to claim 5, wherein: 7. The flash memory according to claim 1, wherein the first memory block and the second memory block have different storage capacities. 8. The first memory block is the second memory block.
8. The flash memory according to claim 7, which has a capacity larger than that of the memory block. 9. The flash memory according to claim 8, wherein the first memory block is for storing a program, and the second memory block is for storing data. 10. A single semiconductor chip comprising the flash memory according to claim 1 and a central processing unit capable of accessing the flash memory. And a microcomputer.