JP3826458B2

JP3826458B2 - Method of bonding die bonding material

Info

Publication number: JP3826458B2
Application number: JP34346096A
Authority: JP
Inventors: 英博中村; 正己湯佐; 良明坪松; 順雄岩崎; 文男井上; 茂樹市村; 康彦阿波野
Original assignee: Hitachi Chemical Co Ltd; Showa Denko Materials Co Ltd; Resonac Corp
Current assignee: Resonac Corp
Priority date: 1996-12-24
Filing date: 1996-12-24
Publication date: 2006-09-27
Anticipated expiration: 2016-12-24
Also published as: JPH10189798A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パッケ−ジ用チップ支持基板の製造法、半導体パッケ−ジ、半導体パッケ−ジの製造法、半導体パッケ−ジ用チップ支持基板の製造用絶縁材転写用シ−トに関する。
【０００２】
【従来の技術】
半導体の集積度が向上するに従い、入出力端子数が増加している。従って、多くの入出力端子数を有する半導体パッケージが必要になった。一般に、入出力端子はパッケージの周辺に一列配置するタイプと、周辺だけでなく内部まで多列に配置するタイプがある。前者は、ＱＦＰ（ＱｕａｄＦｌａｔＰａｃｋａｇｅ）が代表的である。これを多端子化する場合は、端子ピッチを縮小することが必要であるが、０．５ｍｍピッチ以下の領域では、配線板との接続に高度な技術が必要になる。後者のアレイタイプは比較的大きなピッチで端子配列が可能なため、多ピン化に適している。従来、アレイタイプは接続ピンを有するＰＧＡ（ＰｉｎＧｒｉｄＡｒｒａｙ）が一般的であるが、配線板との接続は挿入型となり、表面実装には適していない。このため、表面実装可能なＢＧＡ（ＢａｌｌＧｒｉｄＡｒｒａｙ）と称するパッケージが開発されている。
【０００３】
一方、電子機器の小型化に伴って、パッケージサイズの更なる小型化の要求が強くなってきた。この小型化に対応するものとして、半導体チップとほぼ同等サイズの、いわゆるチップサイズパッケージ（ＣＳＰ；ＣｈｉｐＳｉｚｅＰａｃｋａｇｅ）が提案されている。これは、半導体チップの周辺部でなく、実装領域内に外部配線基板との接続部を有するパッケージである。具体例としては、バンプ付きポリイミドフィルムを半導体チップの表面に接着し、チップと金リード線により電気的接続を図った後、エポキシ樹脂などをポッティングして封止したもの（ＮＩＫＫＥＩＭＡＴＥＲＩＡＬＳ＆ＴＥＣＨＮＯＬＯＧＹ９４．４，Ｎｏ．１４０，ｐ１８−１９）や、仮基板上に半導体チップ及び外部配線基板との接続部に相当する位置に金属バンプを形成し、半導体チップをフェースダウンボンディング後、仮基板上でトランスファーモールドしたもの（ＳｍａｌｌｅｓｔＦｌｉｐ−Ｃｈｉｐ−ＬｉｋｅＰａｃｋａｇｅＣＳＰ；ＴｈｅＳｅｃｏｎｄＶＬＳＩＰａｃｋａｇｉｎｇＷｏｒｋｓｈｏｐｏｆＪａｐａｎ，ｐ４６−５０，１９９４）などがある。
従来提案されている半導体パッケージの多くは、小型で高集積度化に対応できかつパッケージクラックを防止し信頼性に優れしかも生産性に優れるものではない。
また、バンプ付きポリイミドフィルム等のチップ搭載用基板に半導体チップを接着し実装するダイボンデイング材を、チップ搭載用基板に接着する必要がある。従来は、液状体ダイボンデイング材をデイスペンサで塗布するか、膜状体（フィルム状）ダイボンデイング材を熱圧着している。
【０００４】
【発明が解決しようとする課題】
このような方法は、複雑なシーケンス制御や画像位置合わせなど装置の精密化が要求され、さらには、個片貼り付けが多くタクトタイムの削減に制限がある。膜状体（フィルム状）ダイボンデイング材は仮置きや貼り付けを個片で行うため、特に圧着時間を大きくするばあいにタクト時間増大となるため、圧着条件は容易に変更できない。
本発明は、パッケージクラックを防止し信頼性に優れる小型の半導体パッケ−ジの製造を可能とする半導体パッケ−ジ用チップ支持基板を提供するものであり、ダイボンデイング材のチップ搭載用基板への接着において安価にタクトタイムを短縮する方法を与えるものである。
【０００５】
【課題を解決するための手段】
本発明の半導体パッケ−ジ用チップ支持基板の製造法は、
Ａ．半導体チップ実装用端子、引き回し配線及び外部接続用端子を備えた導電体が形成された絶縁性支持基板を準備する工程、
Ｂ．離型性シ−トの所定箇所に接着性と絶縁性を確保した所定形状の絶縁材層が形成された絶縁材転写用シ−トを準備する工程、
Ｃ．前記絶縁性支持基板の半導体チップ搭載領域部に、前記絶縁材転写用シ−トの前記所定形状の絶縁材層を対向させ、前記絶縁性支持基板と前記絶縁材転写用シ−トとを加圧し、前記所定形状の絶縁材層を前記離型性シ−トから前記絶縁性支持基板の半導体チップ搭載領域部に転写する工程、
Ｄ．前記離型性シ−トを剥離する工程
を備えることを特徴とするものである。
【０００６】
本発明の半導体パッケ−ジ用チップ支持基板の製造法では、導電体は半導体チップ搭載領域を備えたものであり、絶縁性支持基板の半導体チップ搭載領域部には前記導電体の半導体チップ搭載領域が含まれるようにすることができる。
【０００７】
また本発明の半導体パッケ−ジ用チップ支持基板の製造法では、絶縁性支持基板の半導体チップ搭載領域部にベントホ−ルが設けられており、絶縁材転写用シ−トの前記ベントホ−ルに対向した箇所にベントホールより大きい切り欠きが設けられているようにするこたができる。
【０００８】
本発明の半導体パッケ−ジは、本発明の方法で製造された半導体パッケ−ジ用チップ支持基板の絶縁材層を介して半導体チップを搭載させた半導体パッケ−ジである。
【０００９】
本発明の半導体パッケ−ジの製造法は、
ａ．半導体チップ実装用端子、引き回し配線及び外部接続用端子を備えた導電体が形成された絶縁性支持基板を準備する工程、
ｂ．離型性シ−トの所定箇所に接着性と絶縁性を確保した所定形状の絶縁材層が形成された絶縁材転写用シ−トを準備する工程、
ｃ．前記絶縁性支持基板の半導体チップ搭載領域部に、前記絶縁材転写用シ−トの前記所定形状の絶縁材層を対向させ、前記絶縁性支持基板と前記絶縁材転写用シ−トとを加圧し、前記所定形状の絶縁材層を前記離型性シ−トから前記絶縁性支持基板の半導体チップ搭載領域部に転写する工程、
ｄ．前記離型性シ−トを剥離する工程
ｅ．前記絶縁性支持基板の半導体チップ搭載領域部に転写された前記所定形状の絶縁材層を介して半導体チップを搭載させる工程、
を備えるとともに、
前記離型性シ−トを剥離する工程（ｄ）を
前記絶縁性支持基板の半導体チップ搭載領域部に転写された前記所定形状の絶縁材層を介して半導体チップを搭載させる工程（ｅ）の直前に行うことを特徴とする半導体パッケ−ジの製造法。
【００１０】
本発明の半導体パッケ−ジ用チップ支持基板の製造用絶縁材転写用シ−トは、離型性シ−トの所定箇所に接着性と絶縁性を確保した所定形状の液状絶縁材層を形成し、後に絶縁性支持基板に転写するため接着性を著しく損なわないまでに乾燥した絶縁材転写用シ−トである。
【００１１】
【発明の実施の形態】
本発明が適用できる半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の具体例の断面図を図１、２に示す。これらは、少なくともインナー接続部（半導体チップ実装用端子）とアウター接続部（外部接続用端子）への引き回し配線を備えた導電体１とこれと導通したアウター接続部（外部接続用端子）が設けられる絶縁性支持基板２からなる。３は半導体チップ搭載領域部であり、図１、２は半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の構成１単位４となる。
図１は、導電体１が半導体チップ搭載領域部３の周辺に配置され、一般に知られるＰＧＡ（ＰｉｎＧｒｉｄＡｒｒａｙ）、ＢＧＡ（ＢａｌｌＧｒｉｄＡｒｒａｙ）がこれに対応する。一方、図２は半導体チップ搭載領域部３に導電体１のアウター接続部への引き回し配線を配置した構造であり、図１と比べてパッケージ寸法を縮小できる。すなわちこの導電体は、半導体チップ実装用端子、引き回し配線及び外部接続用端子、半導体チップ搭載領域を備えたものである。この構造はＣＳＰ（ＣｈｉｐＳｉｚｅＰａｃｋａｇｅ）をもくろむ構造である。
【００１２】
本発明は、図３に示す様にチップ搭載用基板が多面で作製された基板を前提とする。すなわち、本発明は図１、２に示す半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の構成１単位４が多数作製された基板に好適に適用される。このチップ搭載用基板が多面で作製された基板の所定位置にガイド穴５を設ける。図３に示すガイド穴５を設けかつチップ搭載用基板の構成１単位が多面付けされた基板を以下配線基板６と呼ぶ。
次に、図４に示す望ましくは透明の離型性シ−ト７に膜状体ダイボンデイング材８を例えば印刷法によりパターニング及び熱処理して形成し、配線基板６のガイド穴５に対向したのガイド穴９を設ける。この図４に示すガイド穴９を設けた膜状体ダイボンデイング材８付き離型シ−トを以下Ｄ／Ｂ材転写フィルム１０と呼ぶ。Ｄ／Ｂ材転写フィルム１０のガイド穴９を配線基板６のガイド穴５と対向させ、かつ配線基板６の半導体チップ搭載領域部３とＤ／Ｂ材転写フィルム１０のダイボンデイング材８側が接着する様に配置して熱圧着する。この工程を以下Ｄ／Ｂ材フィルム仮貼り転写と呼ぶ。
【００１３】
【実施例】
図５、６により本発明の１実施例を説明する。まず図５によりＤ／Ｂ材転写フィルム作製方法を説明する。
離型性シ−ト１０としてＰＥＴフィルム、ＯＰＰフィルム（延伸ポリプロピレンフィルム）、ＴＰＸ（メチルペンテンコポリマ）フィルムなど、表面エネルギーが２０〜５０ｅｒｇ／ｃｍ²で、望ましくは透明性のあるフィルムを所定の大きさ（縦２５０ｍｍ、横３００ｍｍ、厚さ５０μｍ）に切り出す（図５（ａ））。離型性シ−ト１０の片面にＤ／Ｂ材ワニス（粘度１００〜１０００ポイズ：Ｅ型粘度計１回転／分）をスクリーンメッシュ或いは望ましくはメタルマスクを用いて所定のパターン１１を印刷する。このとき、ガイド穴９と場合により追加して後述するベントホール対向穴を穴明けするための基準となるＫおよびＫ’とよぶマークパターン１２も印刷する（図５（ｂ））。これをガラスエポキシ基板にのせ、４隅をマイラテープで固定し、乾燥する。この後、Ｋ、Ｋ’をパンチング穴明けする。１３はパンチング穴（直径３．１５ｍｍ）である（図５（ｃ））。このパンチング穴１３を基準にしてＮＣ穴明け装置でガイド穴９、場合によりベントホール対向穴を穴明けする。これにより、Ｄ／Ｂ材転写フィルムができる（図５（ｄ））。
【００１４】
Ｄ／Ｂ材ワニスとしては、例えば
【化１】

（ただし、ｎ＝２〜２０の整数を示す。）
で表されるテトラカルボン酸二無水物（１）の含量が全テトラカルボン酸二無水物の７０モル％以上であるテトラカルボン酸二無水物と、ジアミンを反応させて得られるポリアミド酸、ポリイミド樹脂、更にエポキシ樹脂等の熱硬化性樹脂を必要に応じて有機溶媒に溶解させたワニスがある。更にこれにシリカ、アルミナ、等の無機物質フィラーを含有させることもできる。またソルダ用絶縁材として市販されているもの、例えば太陽インク製商品名ＰＳＲ−４００ＡＵＳ５等の使用できる。
【００１５】
図６により、Ｄ／Ｂ材フィルム仮貼り転写工程を説明する。
Ｄ／Ｂ材仮貼り転写では、まずＤ／Ｂ材転写フィルムの切り出しを行う（図６（ａ））。配線基板とＤ／Ｂ材転写フィルムの大きさが対応していればこの切り出しは必要ない。次に（図６（ｂ））に示す転写フィルム治具固定ではガイドピン付き治具１４に厚さ２．５ｍｍのシリコンゴム１５、厚さ１．０ｍｍのシリコン板１６の順に設置しておく。この上にガイド穴を通す様に、Ｄ／Ｂ材転写フィルム９をＤ／Ｂ材を上にして設置する。この後、（図６（ｃ））に示すように配線基板６の半導体チップ搭載領域部を下にして、ガイド穴を通す様に配線基板６を設置する。そして上下を０．１厚のテフロンシート１７で挟み込む。この後、この構成品を熱圧着する。この時に構成品の下側は常温の平坦な金属板に設置し、上側は熱源を有する表面が平坦な金属により加圧する。圧着後、構成品を解体し、配線基板６に転写されたＤ／Ｂ材転写フィルムの離型性シ−ト１０を剥離する（図６（ｄ））。最後に、Ｄ／Ｂ材の残溶剤量を調整するため乾燥する（図６（ｅ））。構成品の熱圧着はロ−ルでも良い。
【００１６】
このようにして作製された、チップ搭載用基板の断面を図７、８に示す。１８は配線基板に転写されたＤ／Ｂ材である。特に図８に示す様に、半導体チップ搭載領域を備えた２以上の導電体が形成されておりこの２以上の導電体の半導体チップ搭載領域にわたって半導体チップが搭載される場合、すなわち半導体チップ搭載領域を備えた２以上の導電体にわたって半導体チップ搭載領域部が構成されるチップ搭載用基板の場合には、圧着条件により所定配線間（導電体間）に間隙を持たせたままテント状にＤ／Ｂ材を形成できる他、埋め込み率を容易に制御できる。
すなわち、所定配線の端面（導電体の端面）と絶縁性支持基板表面と転写形成されたＤ／Ｂ材下面とで空隙が形成されるように、テント状にＤ／Ｂ材を形成すろようにすることができる。また前記空隙にＤ／Ｂ材が所定量埋め込まれるように埋め込み率を容易に制御することができる。
【００１７】
図９にベントホール１９を有する場合のチップ搭載用基板の断面図を示す。２０は外部接続のためのはんだボールを接続するための接続穴、２１はＤ／Ｂ材を支持するためのダミ−パタ−ンを示す。この図からも推察できるが、はんだボールを接続するリフローやマザーボードに実装する際のリフロー信頼性は、前記空隙の間隙率が高いほど膨張蒸気の逃げ道となる有効体積が大となり大きくなる。図１０は、図９のチップ搭載用基板の平面図である。
所定配線間の絶縁性が充分に確保されない場合においては、前記空隙の間隙の埋め込み率を圧着条件により変えることができる。埋め込み率を高くすると、図１１に示す様に、チップ（図示せず）とＤ／Ｂ材１８界面に間隙が残りベントホール１９による蒸気の逃げ道がなくなる。そこで図１２に示すようにベントホール１９と対向した箇所のＤ／Ｂ材転写フィルム９を、図５（ｄ）のガイド穴明け工程で穴明けしておく。この時の転写位置関係を図１２に示す。Ｄ／Ｂ材フィルム仮貼り転写により図１３の断面を持つチップ搭載用基板が得られる。この場合は、所定配線間の絶縁性が充分に確保されるように空隙間隙の埋め込み率を高くしかつベントホール１９による蒸気の逃げ道も確保することができる。
【００１８】
【発明の効果】
以上の発明により個々の膜状体ダイボンデイング材の接着において大幅なタクトタイム短縮が可能となる。
【図面の簡単な説明】
【図１】本発明が適用できる半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の具体例を示す断面図。
【図２】本発明が適用できる半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の具体例を示す断面図。
【図３】半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の構成１単位４が多数作製された基板の平面図。
【図４】Ｄ／Ｂ材転写フィルムの断面図。
【図５】Ｄ／Ｂ材転写フィルム作製工程を説明する断面図。
【図６】Ｄ／Ｂ材フィルム仮貼り転写工程を説明する断面図。
【図７】本発明の半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の断面図。
【図８】本発明の半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の断面図。
【図９】本発明の半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の断面図。
【図１０】図９の半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の平面図。
【図１１】ベントホール部を拡大した半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の断面図。
【図１２】ベントホールと対向したＤ／Ｂ材転写フィルムの位置関係を示すの断面図。
【図１３】本発明の半導体パッケ−ジ用チップ支持基板（チップ搭載用基板）の断面図。
【符号の説明】
１．導電体
２．絶縁性支持基板
３．半導体チップ搭載領域部
４．半導体パッケ−ジ用チップ支持基板の構成１単位
５．ガイド穴
６．配線基板
７．離型性シ−ト
８．膜状体ダイボンデイング材
９．ガイド穴
１０．Ｄ／Ｂ材転写フィルム
１１．所定のパターン
１２．マークパターン
１３．パンチング穴
１４．ガイドピン付き治具
１５．シリコンゴム
１６．シリコン板
１７．テフロンシート
１８．転写されたＤ／Ｂ材
１９．ベントホール
２０．ボール用接続穴
２１．ダミ−パタ−ン[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package chip support substrate, a semiconductor package, a method for manufacturing a semiconductor package, and an insulating material transfer sheet for manufacturing a chip support substrate for a semiconductor package.
[0002]
[Prior art]
As the degree of integration of semiconductors has improved, the number of input / output terminals has increased. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, there are a type in which input / output terminals are arranged in a row around the package and a type in which the input / output terminals are arranged in multiple rows not only in the periphery but also in the interior. The former is typically QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in a region having a pitch of 0.5 mm or less, advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged with a relatively large pitch. Conventionally, an array type is generally a PGA (Pin Grid Array) having connection pins, but connection with a wiring board is an insertion type and is not suitable for surface mounting. Therefore, a package called BGA (Ball Grid Array) that can be mounted on the surface has been developed.
[0003]
On the other hand, with the downsizing of electronic devices, the demand for further downsizing of the package size has increased. In order to cope with this miniaturization, a so-called chip size package (CSP) having a size substantially equal to that of a semiconductor chip has been proposed. This is a package having a connection portion with an external wiring board in the mounting region, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is bonded to the surface of a semiconductor chip, and after electrical connection is made between the chip and a gold lead wire, epoxy resin or the like is potted and sealed (NIKKEI MATERIALS & TECHNOLOGY 94. 4, No. 140, p18-19) or metal bumps are formed on the temporary substrate at positions corresponding to the connection portions between the semiconductor chip and the external wiring substrate, and the semiconductor chip is transferred on the temporary substrate after face-down bonding. Molded (Smallest Flip-Chip-Like Package CSP; TheSecond VLSI Packaging Workshop of Japan, p46-50, 1994).
Many of the conventionally proposed semiconductor packages are small in size, can cope with high integration, prevent package cracks, have excellent reliability, and are not excellent in productivity.
Moreover, it is necessary to adhere | attach the die bonding material which adhere | attaches and mounts a semiconductor chip on chip | tip mounting substrates, such as a polyimide film with a bump, on a chip | tip mounting substrate. Conventionally, a liquid die-bonding material is applied with a dispenser, or a film-like (film-like) die-bonding material is thermocompression bonded.
[0004]
[Problems to be solved by the invention]
Such a method requires precision of the apparatus such as complicated sequence control and image alignment, and moreover, there are many sticking of individual pieces and there is a limit to reduction of tact time. Since the film-like (film-like) die-bonding material is temporarily placed and pasted in pieces, the tact time is increased especially when the pressure-bonding time is increased, so that the pressure-bonding conditions cannot be easily changed.
The present invention provides a chip support substrate for a semiconductor package that enables the manufacture of a small semiconductor package that prevents package cracks and is excellent in reliability, and provides a die-bonding material to a chip mounting substrate. It provides a method for shortening the tact time at low cost in bonding.
[0005]
[Means for Solving the Problems]
The manufacturing method of the chip support substrate for a semiconductor package of the present invention is as follows:
A. Preparing an insulating support substrate on which a conductor having a semiconductor chip mounting terminal, a lead wiring, and an external connection terminal is formed;
B. A step of preparing an insulating material transfer sheet in which an insulating material layer having a predetermined shape that secures adhesiveness and insulating properties is formed at a predetermined position of the releasable sheet;
C. The insulating support layer and the insulating material transfer sheet are added to the insulating support substrate and the semiconductor chip mounting region of the insulating support substrate facing the insulating material layer having the predetermined shape. Pressing and transferring the predetermined-shaped insulating material layer from the releasable sheet to the semiconductor chip mounting region of the insulating support substrate;
D. The method includes a step of peeling the releasable sheet.
[0006]
In the method for manufacturing a chip support substrate for a semiconductor package according to the present invention, the conductor includes a semiconductor chip mounting region, and the semiconductor chip mounting region of the conductor is provided in the semiconductor chip mounting region portion of the insulating support substrate. Can be included.
[0007]
In the method for manufacturing a semiconductor package chip support substrate of the present invention, a vent hole is provided in the semiconductor chip mounting area of the insulating support substrate, and the vent hole of the insulating material transfer sheet is provided on the vent hole. A notch larger than the vent hole can be provided at the opposite location.
[0008]
The semiconductor package of the present invention is a semiconductor package in which a semiconductor chip is mounted via an insulating material layer of a chip support substrate for a semiconductor package manufactured by the method of the present invention.
[0009]
The manufacturing method of the semiconductor package of the present invention is as follows:
a. Preparing an insulating support substrate on which a conductor having a semiconductor chip mounting terminal, a lead wiring, and an external connection terminal is formed;
b. A step of preparing an insulating material transfer sheet in which an insulating material layer having a predetermined shape that secures adhesiveness and insulating properties is formed at a predetermined position of the releasable sheet;
c. The insulating support layer and the insulating material transfer sheet are added to the insulating support substrate and the semiconductor chip mounting region of the insulating support substrate facing the insulating material layer having the predetermined shape. Pressing and transferring the predetermined-shaped insulating material layer from the releasable sheet to the semiconductor chip mounting region of the insulating support substrate;
d. Peeling the releasable sheet e. Mounting a semiconductor chip through the insulating material layer having the predetermined shape transferred to the semiconductor chip mounting region of the insulating support substrate;
With
The step (d) of peeling the releasable sheet is a step (e) of mounting a semiconductor chip via the insulating material layer having the predetermined shape transferred to the semiconductor chip mounting region portion of the insulating support substrate. A method for producing a semiconductor package, which is performed immediately before.
[0010]
The sheet for insulating material transfer for manufacturing a chip support substrate for a semiconductor package according to the present invention forms a liquid insulating material layer having a predetermined shape that secures adhesiveness and insulation at a predetermined location of a releasable sheet. In addition, since the sheet is transferred to an insulating support substrate later, it is an insulating material transfer sheet that has been dried until the adhesiveness is not significantly impaired.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
1 and 2 show cross-sectional views of specific examples of a semiconductor package chip support substrate (chip mounting substrate) to which the present invention can be applied. They are provided with at least an inner connection portion (semiconductor chip mounting terminal) and an outer connection portion (external connection terminal) electrically connected to the conductor 1 provided with a lead wiring to the outer connection portion (external connection terminal). The insulating support substrate 2 is formed. Reference numeral 3 denotes a semiconductor chip mounting area, and FIGS. 1 and 2 show a configuration 1 unit 4 of a semiconductor package chip support substrate (chip mounting substrate).
In FIG. 1, the conductor 1 is arranged around the semiconductor chip mounting region 3, and generally known PGA (Pin Grid Array) and BGA (Ball Grid Array) correspond to this. On the other hand, FIG. 2 shows a structure in which the lead wiring to the outer connection portion of the conductor 1 is arranged in the semiconductor chip mounting region portion 3, and the package size can be reduced as compared with FIG. That is, the conductor includes a semiconductor chip mounting terminal, a lead wiring and an external connection terminal, and a semiconductor chip mounting region. This structure is a structure including CSP (Chip Size Package).
[0012]
The present invention is premised on a substrate on which a chip mounting substrate is manufactured from multiple sides as shown in FIG. That is, the present invention is preferably applied to a substrate on which a large number of units 1 of the structure 4 of the semiconductor package chip support substrate (chip mounting substrate) shown in FIGS. A guide hole 5 is provided at a predetermined position of the substrate on which the chip mounting substrate is manufactured with multiple surfaces. A substrate in which the guide holes 5 shown in FIG. 3 are provided and one unit of the chip mounting substrate is multifaceted is hereinafter referred to as a wiring substrate 6.
Next, a film-like die bonding material 8 is formed on the desirably transparent release sheet 7 shown in FIG. 4 by patterning and heat treatment by, for example, a printing method, and is opposed to the guide hole 5 of the wiring board 6. Guide holes 9 are provided. The release sheet with the film-shaped die bonding material 8 provided with the guide holes 9 shown in FIG. 4 is hereinafter referred to as a D / B material transfer film 10. The guide hole 9 of the D / B material transfer film 10 is opposed to the guide hole 5 of the wiring substrate 6, and the semiconductor chip mounting region 3 of the wiring substrate 6 and the die bonding material 8 side of the D / B material transfer film 10 are bonded. Place them in the same manner and thermocompression bond. This process is hereinafter referred to as D / B material film temporary transfer.
[0013]
【Example】
An embodiment of the present invention will be described with reference to FIGS. First, a method for producing a D / B material transfer film will be described with reference to FIG.
As the releasable sheet 10, a film having a surface energy of 20 to 50 erg / cm ² , such as a PET film, an OPP film (stretched polypropylene film), or a TPX (methyl pentene copolymer) film, is preferably a predetermined large film. Cut out to a width (250 mm long, 300 mm wide, 50 μm thick) (FIG. 5A). A predetermined pattern 11 is printed on one side of the releasable sheet 10 by using a D / B material varnish (viscosity 100 to 1000 poise: E type viscometer 1 rotation / minute) using a screen mesh or preferably a metal mask. At this time, a mark pattern 12 called K and K ′, which serves as a reference for drilling a guide hole 9 and a vent hole facing hole which will be described later in some cases, is also printed (FIG. 5B). This is placed on a glass epoxy substrate, and the four corners are fixed with mylar tape and dried. Thereafter, punching holes K and K ′ are formed. Reference numeral 13 denotes a punching hole (diameter: 3.15 mm) (FIG. 5C). Using this punching hole 13 as a reference, an NC drilling device is used to drill the guide hole 9, and possibly the vent hole facing hole. Thereby, a D / B material transfer film is formed (FIG. 5D).
[0014]
Examples of D / B material varnishes include:

(However, n represents an integer of 2 to 20.)
A polycarboxylic acid obtained by reacting a diamine with a tetracarboxylic dianhydride whose content of tetracarboxylic dianhydride (1) is 70 mol% or more of the total tetracarboxylic dianhydride, and a polyimide resin Furthermore, there is a varnish in which a thermosetting resin such as an epoxy resin is dissolved in an organic solvent as necessary. Furthermore, an inorganic substance filler such as silica, alumina or the like can be contained therein. Moreover, what is marketed as an insulating material for solders, for example, the product name PSR-400AUS5 manufactured by Taiyo Ink can be used.
[0015]
The D / B material film temporary sticking transfer step will be described with reference to FIG.
In the D / B material temporary transfer, the D / B material transfer film is first cut out (FIG. 6A). If the size of the wiring board corresponds to the size of the D / B material transfer film, this cutting is not necessary. Next, in fixing the transfer film jig shown in FIG. 6 (b), a silicon rubber 15 having a thickness of 2.5 mm and a silicon plate 16 having a thickness of 1.0 mm are placed on a jig 14 with a guide pin in this order. The D / B material transfer film 9 is placed with the D / B material facing upward so that the guide hole is passed over it. Thereafter, as shown in FIG. 6C, the wiring board 6 is installed so that the semiconductor chip mounting area of the wiring board 6 faces down and the guide holes are passed. Then, the top and bottom are sandwiched between 0.1-thick Teflon sheets 17. Thereafter, this component is thermocompression bonded. At this time, the lower side of the component is placed on a flat metal plate at room temperature, and the upper side is pressurized with a metal having a flat surface having a heat source. After the pressure bonding, the components are disassembled, and the release sheet 10 of the D / B material transfer film transferred to the wiring board 6 is peeled off (FIG. 6D). Finally, it is dried to adjust the residual solvent amount of the D / B material (FIG. 6 (e)). A roll may be sufficient as the thermocompression bonding of a component.
[0016]
7 and 8 show cross sections of the chip mounting substrate thus manufactured. Reference numeral 18 denotes a D / B material transferred to the wiring board. In particular, as shown in FIG. 8, when two or more conductors having a semiconductor chip mounting region are formed and the semiconductor chip is mounted over the semiconductor chip mounting region of the two or more conductors, that is, the semiconductor chip mounting region. In the case of a chip mounting substrate in which a semiconductor chip mounting region is formed over two or more conductors having a D / D shape in a tent shape with a gap between predetermined wirings (between conductors) depending on the crimping conditions. In addition to forming the B material, the embedding rate can be easily controlled.
That is, the D / B material is formed in a tent shape so that a gap is formed between the end surface of the predetermined wiring (the end surface of the conductor), the surface of the insulating support substrate, and the lower surface of the transferred D / B material. can do. Further, the embedding rate can be easily controlled so that a predetermined amount of D / B material is embedded in the gap.
[0017]
FIG. 9 shows a cross-sectional view of the chip mounting substrate when the vent hole 19 is provided. Reference numeral 20 denotes a connection hole for connecting a solder ball for external connection, and 21 denotes a dummy pattern for supporting the D / B material. As can be inferred from this figure, the reflow reliability when solder balls are connected or mounted on a mother board increases as the void ratio increases and the effective volume serving as an escape path for the expanded steam increases. FIG. 10 is a plan view of the chip mounting substrate of FIG.
When the insulation between the predetermined wirings is not sufficiently ensured, the filling ratio of the gaps can be changed depending on the pressure bonding conditions. When the filling rate is increased, a gap remains at the interface between the chip (not shown) and the D / B material 18 as shown in FIG. Therefore, as shown in FIG. 12, the D / B material transfer film 9 at a location facing the vent hole 19 is drilled in the guide drilling step of FIG. FIG. 12 shows the transfer position relationship at this time. The chip mounting substrate having the cross section of FIG. 13 is obtained by temporary transfer of the D / B material film. In this case, it is possible to increase the filling rate of the gaps and ensure a vapor escape path by the vent hole 19 so that sufficient insulation between the predetermined wirings is ensured.
[0018]
【The invention's effect】
According to the above invention, the tact time can be greatly shortened in the bonding of the individual film-shaped body die bonding materials.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a specific example of a semiconductor package chip support substrate (chip mounting substrate) to which the present invention can be applied.
FIG. 2 is a cross-sectional view showing a specific example of a semiconductor package chip support substrate (chip mounting substrate) to which the present invention can be applied.
FIG. 3 is a plan view of a substrate on which a number of constitutional units 4 of a semiconductor package chip support substrate (chip mounting substrate) are produced.
FIG. 4 is a cross-sectional view of a D / B material transfer film.
FIG. 5 is a cross-sectional view illustrating a process for producing a D / B material transfer film.
FIG. 6 is a cross-sectional view illustrating a D / B material film temporary attachment transfer step.
7 is a cross-sectional view of a semiconductor package chip support substrate (chip mounting substrate) according to the present invention; FIG.
FIG. 8 is a cross-sectional view of a semiconductor package chip support substrate (chip mounting substrate) of the present invention.
FIG. 9 is a cross-sectional view of a semiconductor package chip support substrate (chip mounting substrate) according to the present invention;
10 is a plan view of the semiconductor package chip support substrate (chip mounting substrate) of FIG. 9; FIG.
FIG. 11 is a sectional view of a semiconductor package chip support substrate (chip mounting substrate) with an enlarged vent hole portion;
FIG. 12 is a cross-sectional view showing a positional relationship of a D / B material transfer film facing a vent hole.
13 is a cross-sectional view of a semiconductor package chip support substrate (chip mounting substrate) according to the present invention; FIG.
[Explanation of symbols]
1. Conductor 2. 2. Insulating support substrate 3. Semiconductor chip mounting area 4. Configuration of chip support substrate for semiconductor package 1 unit Guide hole 6. Wiring board 7. Release sheet 8. 8. Membrane die bonding material Guide hole 10. 10. D / B material transfer film Predetermined pattern 12. Mark pattern 13. Punching hole 14. 14. Jig with guide pin Silicone rubber 16. Silicon plate 17. Teflon sheet 18. Transferred D / B material 19. Bent hole 20. Ball connection hole 21. Dummy pattern

Claims

A method of adhering a die bonding material to a semiconductor chip mounting region of a plurality of semiconductor chip mounting substrates fabricated on an insulating support substrate,
A film for transferring a die bonding material in which a plurality of film-shaped body die bonding materials having a predetermined shape are formed on one side of a releasable sheet, and the insulating support substrate, and a plurality of the film-shaped body die bonding materials An insulating support substrate comprising: a step of aligning and overlapping each of the semiconductor chip mounting region portions of the semiconductor chip mounting region portion, and thermocompression bonding; and a step of peeling off the release sheet. A method of bonding a die bonding material to a semiconductor chip mounting region of a plurality of semiconductor chip mounting substrates fabricated above.

The surface energy of the surface of the releasable sheet on which the film die bonding material is formed is 20 to 50 erg / cm. ²² The method of claim 1, wherein

3. The method according to claim 1, wherein the film-like die bonding material is formed by patterning a die bonding material varnish having a viscosity of 100 to 1000 poise on one side of the releasable sheet.

The alignment is performed by providing a guide hole at a predetermined position of the die bonding material transfer film and the insulating support substrate, and passing the guide hole through a guide pin of a jig with a guide pin. Item 4. The method according to any one of Items 1 to 3.