JP3143081B2 - Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device - Google Patents

Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device

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Publication number
JP3143081B2
JP3143081B2 JP20454697A JP20454697A JP3143081B2 JP 3143081 B2 JP3143081 B2 JP 3143081B2 JP 20454697 A JP20454697 A JP 20454697A JP 20454697 A JP20454697 A JP 20454697A JP 3143081 B2 JP3143081 B2 JP 3143081B2
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JP
Japan
Prior art keywords
support substrate
semiconductor
chip
semiconductor chip
adhesive
Prior art date
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Expired - Fee Related
Application number
JP20454697A
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Japanese (ja)
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JPH10135247A (en
Inventor
義樹 曽田
浩司 宮田
聡夫 山崎
文男 井上
良明 坪松
英博 中村
康彦 阿波野
茂樹 市村
正己 湯佐
順雄 岩崎
Original Assignee
シャープ株式会社
日立化成工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体パッケ−ジ
用チップ支持基板、半導体装置及び半導体装置の製造法
に関する。The present invention relates to a chip support substrate for a semiconductor package, a semiconductor device, and a method for manufacturing a semiconductor device.

【０００２】[0002]

【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ）が代表的である。これを多端子化する場合は、端子
ピッチを縮小することが必要であるが、０．５ｍｍピッ
チ以下の領域では、配線板との接続に高度な技術が必要
になる。後者のアレイタイプは比較的大きなピッチで端
子配列が可能なため、多ピン化に適している。従来、ア
レイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ Ｇｒｉ
ｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は
挿入型となり、表面実装には適していない。このため、
表面実装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）と称するパッケージが開発されている。2. Description of the Related Art As the degree of integration of semiconductors increases, the number of input / output terminals increases. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, I / O terminals are arranged in a line around the package,
There is a type that is arranged in multiple rows not only around but also inside.
The former is a QFP (Quad Flat Package).
e) is representative. In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in the region of 0.5 mm pitch or less, advanced technology is required for connection with a wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch. Conventionally, the array type is a PGA (Pin Gri) having connection pins.
d Array) is common, but the connection with the wiring board is of an insertion type and is not suitable for surface mounting. For this reason,
Surface mountable BGA (Ball Grid Array)
A package called y) has been developed.

【０００３】一方、電子機器の小型化に伴って、パッケ
ージサイズの更なる小型化の要求が強くなってきた。こ
の小型化に対応するものとして、半導体チップとほぼ同
等サイズの、いわゆるチップサイズパッケージ（ＣＳ
Ｐ； Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案さ
れている。これは、半導体チップの周辺部でなく、実装
領域内に外部配線基板との接続部を有するパッケージで
ある。具体例としては、バンプ付きポリイミドフィルム
を半導体チップの表面に接着し、チップと金リード線に
より電気的接続を図った後、エポキシ樹脂などをポッテ
ィングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩ
ＡＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．
１４０，ｐ１８−１９）や、仮基板上に半導体チップ及
び外部配線基板との接続部に相当する位置に金属バンプ
を形成し、半導体チップをフェースダウンボンディング
後、仮基板上でトランスファーモールドしたもの（Ｓｍ
ａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃ
ｋａｇｅ ＣＳＰ； ＴｈｅＳｅｃｏｎｄ ＶＬＳＩ
Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐ
ａｎ，ｐ４６−５０，１９９４）などがある。[0003] On the other hand, with the miniaturization of electronic equipment, the demand for further miniaturization of the package size has increased. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) has been proposed. This is a package having a connection portion with an external wiring board in a mounting region, not in a peripheral portion of a semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, and after electrically connecting the chip to a gold lead wire, epoxy resin or the like is potted and sealed (NIKKEI MATERI).
ALS & TECHNOLOGY 94.4, No.
140, pp. 18-19) or a method in which a metal bump is formed on a temporary substrate at a position corresponding to a connection portion between a semiconductor chip and an external wiring substrate, and the semiconductor chip is face-down bonded and then transfer-molded on the temporary substrate ( Sm
allest Flip-Chip-Like Pac
kage CSP; The Second VLSI
Packaging Works of Jap
an, p. 46-50, 1994).

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、従来提
案されている半導体パッケージの多くは、小型で高集積
度化に対応できかつパッケージクラックを防止し信頼性
に優れしかも生産性に優れるものではない。本発明は、
パッケージクラックを防止し信頼性に優れる小型の半導
体パッケ−ジの製造を可能とする半導体パッケ−ジ用チ
ップ支持基板、半導体装置及び半導体装置の製造法を提
供するものである。However, many of the semiconductor packages proposed in the prior art are small in size, can cope with high integration, prevent package cracks, have excellent reliability, and are not excellent in productivity. The present invention
It is an object of the present invention to provide a semiconductor package chip supporting substrate, a semiconductor device, and a method of manufacturing a semiconductor device, which can manufacture a small semiconductor package having excellent reliability by preventing package cracks.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体パッケ−
ジ用チップ支持基板は、 Ａ．絶縁性支持基板の一表面には複数の配線が形成され
ており、前記配線は少なくとも半導体チップ電極と接続
するインナ−接続部及び半導体チップ搭載領域部を有す
ものであり、 Ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前
記配線が形成されている箇所であって前記インナ−接続
部と導通するアウタ−接続部が設けらる箇所に、開口が
設けられており、 Ｃ．前記配線の半導体チップ搭載領域部を含めて半導体
チップが搭載される箇所に、絶縁性のフィルム状接着材
が載置形成されており、 Ｄ．前記絶縁性支持基板の前記絶縁性フィルム状接着材
が形成される箇所には、前記絶縁性フィルム状接着材の
平板性を維持するための少なくとも１つ以上の金属パタ
−ンが形成されている ことを特徴とするものである。絶縁性支持基板の絶縁性
フィルム状接着材が載置形成される箇所には、少なくと
も１個の第一の貫通穴を設けることができる。又絶縁性
支持基板には半導体チップ封止用の封止樹脂が被覆され
る封止領域が設けられ、前記封止領域には少なくとも１
個の第二の貫通穴を設けることができる。金属パタ−ン
は複数個形成され、相互間の間隔は１ミリメートル以下
となるように形成するのが好ましい。すなわち任意の点
から半径１ミリメートルの範囲に少なくとも１つ以上の
金属パタ−ンが形成されているようにするのが好まし
い。このような複数個の金属パタ−ンは、均等配置する
のが好ましい。本発明の半導体装置は、上記本発明の半
導体パッケージ用チップ支持基板と、前記支持基板のフ
ィルム状接着材の面に搭載された半導体チップと、前記
半導体チップを封止する樹脂封止を備えるものである。
本発明の半導体装置の製造法は、上記本発明の半導体パ
ッケージ用チップ支持基板のフィルム状接着材の面に半
導体チップを接着する工程、半導体チップ電極を配線の
インナ−接続部とワイヤーボンディングにより接続する
工程、半導体チップを樹脂封止する工程、前記支持基板
の開口にインナ−接続部と導通するアウタ−接続部を設
ける工程を備えるものである。SUMMARY OF THE INVENTION A semiconductor package according to the present invention is provided.
The chip support substrate for A B. A plurality of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part connected to the semiconductor chip electrode and a semiconductor chip mounting area part; In the insulating support substrate, an opening is provided at a position where the wiring of the insulating support substrate is formed and at a position where an outer connection portion that is electrically connected to the inner connection portion is provided. C. B. an insulating film-like adhesive is placed and formed on a portion where the semiconductor chip is mounted including the semiconductor chip mounting region of the wiring; At least one or more metal patterns for maintaining the flatness of the insulating film-like adhesive are formed on the insulating support substrate where the insulating film-like adhesive is formed. It is characterized by the following. At least one first through-hole can be provided in a portion of the insulating support substrate where the insulating film-like adhesive is placed and formed. The insulating support substrate is provided with a sealing region covered with a sealing resin for sealing a semiconductor chip.
Individual second through holes can be provided. It is preferable that a plurality of metal patterns are formed, and the interval between them is 1 mm or less. That is, it is preferable that at least one or more metal patterns are formed within a range of a radius of 1 mm from an arbitrary point. It is preferable that such a plurality of metal patterns are evenly arranged. A semiconductor device of the present invention includes the above-described chip supporting substrate for a semiconductor package of the present invention, a semiconductor chip mounted on a surface of a film-like adhesive of the supporting substrate, and a resin seal for sealing the semiconductor chip. It is.
The method of manufacturing a semiconductor device according to the present invention includes a step of bonding a semiconductor chip to the surface of the film-like adhesive of the chip supporting substrate for a semiconductor package according to the present invention, and connecting the semiconductor chip electrode to an inner connection portion of the wiring by wire bonding. And a step of encapsulating the semiconductor chip with a resin, and a step of providing an outer connection portion in conduction with the inner connection portion in the opening of the support substrate.

【０００６】[0006]

【発明の実施の形態】絶縁性支持基板としては、ポリイ
ミド、エポキシ樹脂、ポリイミド等のプラスチックフィ
ルム、ポリイミド、エポキシ樹脂、ポリイミド等のプラ
スチックをガラス不織布等基材に含浸・硬化したもの等
が使用できる。絶縁性支持基板の一表面に複数の配線を
含む金属パタ−ン形成すには、銅箔をエッチングする方
法、所定の箇所に銅めっきをする方法、それらを併用す
る方法等が使用できる。絶縁性支持基板に外部接続部、
第一の貫通穴（貫通穴（ａ））及び第二の貫通穴（貫通
穴（ｂ））などの開口を設けるには、ドリル加工やパン
チングなどの機械加工、エキシマレーザや炭酸ガスレー
ザなどのレーザ加工等により行うことができる。接着性
のある絶縁基材等に開口部をあらかじめ設けておいてそ
れを銅箔等の配線形成用金属箔と張り合わせる方法、銅
箔付きまたはあらかじめ配線が形成された絶縁基材に開
口部を設ける方法、それらを併用する等が可能である。
インナ−接続部と導通するアウタ−接続部の絶縁性支持
基板開口部にハンダボール、めっき等によりバンプ等を
形成することにより作成することが出来る。これは、外
部の基板等に接続される。金属パタ−ンとは、アウタ−
接続部、インナ−接続部とアウタ−接続部とを結ぶ展開
配線、展開配線間を結ぶ配線、それらとは独立のダミ−
パタ−ン、位置合わせ用マ−ク、文字・符号等を含む何
らかの所定のパタ−ンである。金属パターンは任意であ
るが、特に接着フィルム搭載領域はできるだけ均一に配
置されていることが好ましい。具体的には、絶縁性フィ
ルム状接着材が形成される領域の絶縁性支持基板には任
意の点からその任意の点を含む半径１ミリメートルの範
囲に少なくとも１つ以上の配線が形成されているように
配線が配置されていることが好ましい。ここで配線と
は、アウター接続部、インナー接続部とアウター接続部
とを結ぶ展開配線、展開配線間を結ぶ配線、それらとは
独立のダミーパターン、位置合わせ用マーク、文字・符
号等などをを含んでいる。BEST MODE FOR CARRYING OUT THE INVENTION As an insulating support substrate, a plastic film such as polyimide, epoxy resin or polyimide, or a substrate obtained by impregnating and curing a plastic such as polyimide, epoxy resin or polyimide in a substrate such as glass nonwoven fabric can be used. . In order to form a metal pattern including a plurality of wirings on one surface of the insulating support substrate, a method of etching a copper foil, a method of plating a predetermined portion with copper, a method of using them in combination, or the like can be used. External connection part on insulating support substrate,
To provide openings such as the first through hole (through hole (a)) and the second through hole (through hole (b)), machining such as drilling and punching, and laser such as excimer laser and carbon dioxide gas laser It can be performed by processing or the like. A method in which an opening is provided in advance on an adhesive insulating substrate or the like, and the opening is bonded to a metal foil for forming a wiring such as a copper foil. It is possible to provide them, use them together, or the like.
It can be formed by forming bumps or the like by soldering balls, plating, or the like in the openings of the insulating support substrate of the outer connection portion that conducts to the inner connection portion. This is connected to an external substrate or the like. The metal pattern is the outer
Connection part, an expansion wiring connecting the inner connection part and the outer connection part, a wiring connecting the expansion wirings, and a dummy independent of them.
This is a predetermined pattern including a pattern, a mark for positioning, a character / code, and the like. The metal pattern is arbitrary, but it is particularly preferable that the adhesive film mounting area is arranged as uniformly as possible. Specifically, at least one or more wirings are formed on the insulating support substrate in a region where the insulating film-like adhesive is formed in a range of 1 mm from a given point to a radius of 1 mm including the given point. It is preferable that the wiring is arranged as described above. Here, the wiring means an outer connection portion, a development wiring connecting the inner connection portion and the outer connection portion, a wiring connecting between the development wirings, a dummy pattern independent of them, a positioning mark, a character / code, and the like. Contains.

【０００７】絶縁性のフィルム状接着材は、半導体チッ
プ接続のためのダイボンド材であり、化１The insulating film adhesive is a die bonding material for connecting a semiconductor chip.

【化１】 （ただし、ｎ＝２〜２０の整数を示す。）で表されるテ
トラカルボン酸二無水物（１）の含量が全テトラカルボ
ン酸二無水物の７０モル％以上であるテトラカルボン酸
二無水物と、ジアミンを反応させて得られるポリイミド
樹脂、更にエポキシ樹脂等の熱硬化性樹脂からなるフィ
ルム接着材がよい。更にこれにシリカ、アルミナ、等の
無機物質フィラーを含有してなるフィルム状接着材がよ
り好ましい。厚みについては、絶縁性を確保できる限り
薄くしたほうがパッケージ基板の半田ボール搭載、基板
へのパッケージ搭載等におけるリフロー工程での不良が
低減する。接着前の接着フィルムの厚みとしては、０．
００５ｍｍ以上かつ０．０３０ｍｍ以下が好ましく、あ
らゆる基材、配線パターン等に対して安定した耐リフロ
ー性及び絶縁性を示す厚みとして０．０１ｍｍ以上かつ
０．０２０ｍｍ以下の範囲がより好ましい。貫通穴
（ａ）は、接着フィルム搭載領域に少なくとも１個以上
形成される。穴径は特に問わないが、例えば、０．００
１ｍｍ以上かつ１．０ｍｍなどが選択される。配置も特
に問わないが、なるべく均等に複数個配置されているこ
とが好ましく、これらの穴径、配置は必要な配線パター
ンに応じて選択される。貫通穴（ｂ）は、後工程で用い
られる封止樹脂と接する部分（ただし、パッケージとし
て有効な部分であり、樹脂を注入するためのライナー部
などは含まない）に少なくとも１個以上形成される。穴
径は特に問わないが、例えば０．００１ｍｍ以上かつ
１．０ｍｍ以下の径が選択される。配置も特に問わない
が、特に、コーナー部、周辺部等に形成しておくことが
効果的である。形状は、矩形、一体Ｌ字型、円形などが
ある。複数の穴を封止材コーナ部にＬ字型等に配置し
て、全体として効果をもたせる方法もある。Embedded image (Wherein, n is an integer of 2 to 20) Tetracarboxylic dianhydride having a content of tetracarboxylic dianhydride (1) of 70 mol% or more of all tetracarboxylic dianhydrides And a film adhesive made of a thermosetting resin such as a polyimide resin obtained by reacting a diamine with a diamine, and an epoxy resin. Further, a film-like adhesive containing an inorganic filler such as silica, alumina and the like is more preferable. As for the thickness, it is preferable to make the thickness as thin as possible so as to ensure the insulating property, so that defects in the reflow process in mounting the solder balls on the package substrate, mounting the package on the substrate, and the like are reduced. The thickness of the adhesive film before bonding is 0.
The thickness is preferably 005 mm or more and 0.030 mm or less, and more preferably 0.01 mm or more and 0.020 mm or less as a thickness exhibiting stable reflow resistance and insulation properties for all base materials and wiring patterns. At least one through hole (a) is formed in the adhesive film mounting area. The hole diameter is not particularly limited.
1 mm or more and 1.0 mm or the like are selected. The arrangement is not particularly limited, but it is preferable that a plurality of holes are arranged as evenly as possible. The diameter and arrangement of these holes are selected according to a required wiring pattern. At least one through-hole (b) is formed in a portion that is in contact with a sealing resin used in a later step (however, it is a portion effective as a package and does not include a liner portion for injecting a resin). . Although the hole diameter is not particularly limited, for example, a diameter of 0.001 mm or more and 1.0 mm or less is selected. The arrangement is not particularly limited, but it is particularly effective to form them at corners, peripheral portions, and the like. The shape includes a rectangle, an integral L-shape, and a circle. There is also a method of arranging a plurality of holes in an L-shape or the like at the corner of the sealing material to give an effect as a whole.

【０００８】本発明の半導体パッケ−ジ用チップ支持基
板を使用して半導体パッケ−ジを製造するには、本発明
の半導体パッケ−ジ用チップ支持基板のフィルム状接着
材の面に半導体チップを接着し、半導体チップ電極を支
持基板のインナ−接続部とワイヤーボンディング等によ
り接続し、半導体チップの少なくとも半導体チップ電極
面を樹脂封止し、支持基板に設けられた開口にインナ−
接続部と導通するアウタ−接続部（例えばハンダバンプ
等）を設けることにより半導体パッケ−ジを製造するこ
とが出来る。In order to manufacture a semiconductor package using the chip supporting substrate for a semiconductor package of the present invention, a semiconductor chip is mounted on the surface of the film-like adhesive of the chip supporting substrate for a semiconductor package of the present invention. The semiconductor chip electrode is connected to the inner connection portion of the support substrate by wire bonding or the like, at least the semiconductor chip electrode surface of the semiconductor chip is resin-sealed, and the inner electrode is inserted into the opening provided in the support substrate.
A semiconductor package can be manufactured by providing an outer connection portion (for example, a solder bump or the like) which is electrically connected to the connection portion.

【０００９】[0009]

【実施例】図１により、本発明の一実施例について説明
する。ポリイミド接着剤をポリイミドフィルムの両面に
塗布した、厚さ０．０７ｍｍのポリイミドボンディング
シート１に、アウター接続部２及び貫通穴（ａ）３、貫
通穴（ｂ）４を形成する。貫通穴（ａ）３及び貫通穴
（ｂ）４はそれぞれ、後の工程で絶縁性接着材が形成さ
れる箇所及び封止材と接する箇所に形成されている。次
に厚さ０．０１８ｍｍの銅箔（日本電解製、商品名：Ｓ
ＬＰー１８）を接着後、インナー接続部５とアウター接
続部２までの展開配線６及びダミーパターン７（これら
２、５、６をまとめて金属パタ−ンと称す）を通常のエ
ッチング法で形成する。さらに、露出している配線に無
電解ニッケルめっき（膜厚：５μｍ）、無電解金めっき
（膜厚：０．８μｍ）を順次施す（不図示）。ここで
は、無電解めっきを使用したが、電解めっきを用いても
よい。次に打ち抜き金型を用いてフレーム状に打ち抜
き、複数組のインナー接続部、展開配線、アウター接続
部を形成した支持基板を準備する（図１ａ）。支持基板
の作製方法として市販の２層（銅／ポリイミド）フレキ
シブル基板のポリイミドを、レーザ加工によりアウター
接続部穴等を形成する方法でもよい。次に支持基板の半
導体チップ搭載領域に、ダイボンドフィルム８（日立化
成工業株式会社製、商品名：ＤＦ−３３５、厚み０．０
１５ｍｍ）を仮接着する（図１ｂ）。仮接着の条件は接
着材の組成にもよるが、例えば温度１６０℃、時間５
秒、圧力３ｋｇｆ／ｃｍ2などが用いられる。図２にこ
こまでの工程で作製した半導体パッケージ用チップ支持
基板の平面配置図の一例を示す。本例のようにインナー
端子がチップの両端に配置されている場合のみならず、
４辺側に配置されていている等でもかまわない。次に、
先ほど仮接着したダイボンドフィルムを用いて、半導体
チップ９を支持基板の所定の位置に接着する。接着条件
は、例えば温度２２０℃、時間５秒、圧力３００ｇｆ／
ｃｍ2である。さらに、半導体チップ電極とインナー接
続部５を、金ワイヤ１０をボンディングして電気的に接
続する（図１ｃ）。このようにして形成したものをトラ
ンスファモールド金型に装填し、半導体封止用エポキシ
樹脂１１（日立化成工業（株）製、商品名：ＣＬ−７７
００）を用いて各々封止する（図１ｄ）。その後、アウ
ター接続部にはんだボール１２を配置し溶融させ（図１
ｅ）、最後にパンチにより個々のパッケージに分離させ
る（図１ｆ）。本実施例では０．０１５ｍｍ厚のダイボ
ンドフィルムを用いたが、比較のためダイボンド厚を変
えたサンプルを作製し、吸湿リフロー試験（試験条件、
温度：３０℃、湿度：７５％、９６時間放置後、温度：
２３０℃、ＩＲリフローを２サイクル）を実施した。そ
の結果、厚み０．０３０ｍｍ以下であれば、良好な耐リ
フロー性（リフローによる剥離、膨れ、内部クラックが
ない）を示すことがわかった。また、同様に厚みを変え
たサンプルを恒温恒湿槽（条件、温度：８５℃、湿度：
８５％）に放置し配線間（ライン／スペース：０．０４
０／０．０４０ｍｍ）の絶縁抵抗を調べた結果、ダイボ
ンドフィルムの厚みが０．００５ｍｍ未満になると１０
００時間後の絶縁抵抗が急激に低下し、初期１０12オー
ムに対して試験後１０2オーム以下になり、ダイボンド
フィルムの厚み０．００５ｍｍ以上では初期１０12オー
ム以上、試験後１０12オーム以上で絶縁抵抗の低下が見
られなかった。したがって、ダイボンドフィルムの厚み
としては０．００５ｍｍ以上かつ０．０３０ｍｍ以下で
あることが望ましい。また、比較のためダミーパターン
７を設けてないサンプルを作製し、本実施例で作製した
サンプルとともに前述の吸湿リフロー試験を実施した。
その結果、ダミーパターンを設けてないサンプルでは、
耐リフロー性を満足できなかった。また、比較のため貫
通穴（ａ）３、貫通穴（ｂ）４のないサンプルを作製
し、本実施例で作製したサンプルとともに前述の吸湿リ
フロー試験を実施した。その結果、いずれの貫通穴を設
けてないサンプルでも耐リフロー性を完全に満足しなか
った。FIG. 1 shows an embodiment of the present invention. An outer connection portion 2 and through holes (a) 3 and through holes (b) 4 are formed on a 0.07 mm thick polyimide bonding sheet 1 in which a polyimide adhesive is applied to both surfaces of a polyimide film. The through-holes (a) 3 and the through-holes (b) 4 are formed at a place where an insulating adhesive is formed and a place where the through-hole (b) 4 is in contact with the sealing material in a later step. Next, a 0.018-mm-thick copper foil (manufactured by Nihon Denshi, trade name: S
After bonding LP-18), the developed wiring 6 and the dummy pattern 7 (these 2, 5, and 6 are collectively referred to as a metal pattern) up to the inner connection portion 5 and the outer connection portion 2 are formed by a normal etching method. I do. Further, electroless nickel plating (film thickness: 5 μm) and electroless gold plating (film thickness: 0.8 μm) are sequentially applied to the exposed wiring (not shown). Here, electroless plating is used, but electrolytic plating may be used. Next, a support substrate having a plurality of sets of inner connection portions, developed wiring, and outer connection portions is prepared by punching out a frame using a punching die (FIG. 1A). As a method for manufacturing the supporting substrate, a method may be used in which polyimide of a commercially available two-layer (copper / polyimide) flexible substrate is formed by laser processing to form outer connection hole portions and the like. Next, die bonding film 8 (trade name: DF-335, manufactured by Hitachi Chemical Co., Ltd., thickness 0.0
15 mm) (FIG. 1b). The conditions of the temporary bonding depend on the composition of the adhesive, but are, for example, 160 ° C. for 5 hours.
For example, a pressure of 3 kgf / cm 2 or the like is used. FIG. 2 shows an example of a plan layout view of the semiconductor package chip supporting substrate manufactured in the steps up to here. Not only when the inner terminals are arranged at both ends of the chip as in this example,
It may be arranged on the four sides. next,
The semiconductor chip 9 is bonded to a predetermined position on the support substrate using the die bond film temporarily bonded earlier. The bonding conditions include, for example, a temperature of 220 ° C., a time of 5 seconds, and a pressure of 300 gf /
cm 2 . Further, the semiconductor chip electrode and the inner connection portion 5 are electrically connected by bonding a gold wire 10 (FIG. 1C). The thus formed product is loaded in a transfer mold, and an epoxy resin 11 for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-77)
00) (FIG. 1d). After that, the solder balls 12 are arranged at the outer connection portions and melted (FIG. 1).
e) Finally, the individual packages are separated by a punch (FIG. 1f). Although a die bond film having a thickness of 0.015 mm was used in this example, a sample having a different die bond thickness was prepared for comparison, and a moisture absorption reflow test (test conditions,
Temperature: 30 ° C, Humidity: 75%, After standing for 96 hours, Temperature:
230 ° C., 2 cycles of IR reflow). As a result, it was found that when the thickness was 0.030 mm or less, good reflow resistance (no peeling, swelling, or internal cracks due to reflow) was exhibited. Similarly, a sample having a changed thickness is placed in a thermo-hygrostat (condition, temperature: 85 ° C., humidity:
85%) and leave between wires (line / space: 0.04)
0 / 0.040 mm), it was found that when the thickness of the die bond film was less than 0.005 mm, 10
And 00 hours insulation resistance suddenly drops after the initial 10 becomes 12 10 2 ohms or less after the test relative ohms, at least a thickness 0.005mm die-bonding film initial 10 12 ohms or higher, at 10 12 ohms or more after test No decrease in insulation resistance was observed. Therefore, the thickness of the die bond film is desirably 0.005 mm or more and 0.030 mm or less. For comparison, a sample without the dummy pattern 7 was prepared, and the above-described moisture absorption reflow test was performed together with the sample prepared in this example.
As a result, in the sample without the dummy pattern,
Reflow resistance could not be satisfied. For comparison, a sample having no through hole (a) 3 and no through hole (b) 4 was prepared, and the above-described moisture absorption reflow test was performed together with the sample prepared in this example. As a result, none of the samples provided with the through holes did not completely satisfy the reflow resistance.

【０００７】[0007]

【発明の効果】半導体パッケージを、 ａ．絶縁性支持基板の一表面に複数組の配線（少なくと
も半導体チップ電極と接続するインナ−接続部及び半導
体チップ搭載領域部を有す）を形成し、 ｂ．絶縁性支持基板の、絶縁性支持基板の配線が形成さ
れている箇所であってインナ−接続部と導通するアウタ
−接続部が設けらる箇所に開口を設け、 ｃ．配線の半導体チップ搭載領域部を含めて半導体チッ
プが搭載される箇所に接着材を形成し、 ｄ．半導体チップを、支持基板のインナ−接続部が設け
られている面に接着材を用いて接着し、 ｅ．半導体チップ電極を基板のインナ−接続部とワイヤ
ーボンディングにより接続し、 ｆ．半導体チップの少なくとも半導体チップ電極面を樹
脂封止して 製造する場合、支持基板の半導体チップ搭載領域に露出
した配線があるので、通常のペースト状接着材（銀ペー
スト、無銀ペースト）を使用すると、半導体チップと配
線がショートしてしまう恐れがある。このため半導体チ
ップ搭載領域にレジスト等の絶縁材料を塗布した構造
や、絶縁フィルムを貼った構造となるが、構造では多く
の材料界面ができ、また接着材のペーストが半導体チッ
プ接着時にボイドを混入しやすいため、吸湿リフロー試
験で剥離やパッケージクラックが発生しやすく、信頼性
を落とす原因になる。また、配線パターンを均等にする
ために必要に応じてダミーパターンを配置するとよい。
これにより、配線が疎な部分の絶縁性接着フィルムの陥
没を防止でき、絶縁性接着フィルムの平板性を維持し
て、チップと絶縁性接着フィルムとの間に空隙部が生じ
ることを防止し、したがって、接着フィルムとチップと
の接着性を向上させることができる。これにより、耐リ
フロー性や長期信頼性を向上させることができる。さら
に、接着フィルム厚みを０．０３０ｍｍ以下と薄くする
ことでパッケージ内部の吸湿の原因となる物質の体積を
極力少なし、耐リフロー性を上げることができる。ただ
し、絶縁抵抗の確保の観点から、厚みとして０．００５
ｍｍ以上は必要であった。そして、このように絶縁フィ
ルム厚０．００５ｍｍ以上０．０３０ｍｍ以下とするこ
とによって信頼性の高いパッケージが得られる。このよ
うな膜厚の正確な制御はフィルム状接着材を用いること
によって達成が容易になる。さらに、絶縁性支持基板の
フィルム状接着材が形成されている箇所に貫通穴（ａ）
は、絶縁基板にフィルム状接着剤を接着する際に、フィ
ルム状接着材と絶縁基板の間に空気をだきこむのを防止
する。空気を抱込んだままチップを搭載して封止する
と、前述のリフロー工程において剥離やクラック等が生
じて信頼性を落とす原因となる。またこの貫通穴は、リ
フロー工程においてその工程以前に接着フィルム等が吸
湿した水分をこの貫通穴から適正に放出させ、パッケー
ジ内部で発生する剥離やクラックなどを防止できる。さ
らに、絶縁性支持基板の封止樹脂と接する箇所に少なく
とも一つ以上の貫通穴（ｂ）を設けることにより、封止
工程で封止樹脂の一部がながれ支持基板と封止材との接
着性を上げる効果がある。これにより、耐リフロー性や
長期信頼性、封止後のハンドリング性を向上させること
ができる。したがって、本発明によりパッケージクラッ
クを防止し信頼性の高い小型半導体パッケ−ジの製造が
可能となる。According to the present invention, a semiconductor package includes: a. Forming a plurality of sets of wirings (having at least an inner connection portion connected to a semiconductor chip electrode and a semiconductor chip mounting region) on one surface of an insulating support substrate; b. Providing an opening in a portion of the insulating support substrate where the wiring of the insulating support substrate is formed and where an outer connection portion that is electrically connected to the inner connection portion is provided; c. Forming an adhesive at a portion where the semiconductor chip is mounted including the semiconductor chip mounting region of the wiring; d. Bonding the semiconductor chip to the surface of the support substrate on which the inner connection portion is provided, using an adhesive; e. Connecting the semiconductor chip electrode to the inner connection portion of the substrate by wire bonding; f. When manufacturing the semiconductor chip by sealing at least the semiconductor chip electrode surface with resin, there is a wiring exposed in the semiconductor chip mounting area of the support substrate. Therefore, when a normal paste adhesive (silver paste, silver-free paste) is used. Therefore, there is a possibility that the semiconductor chip and the wiring are short-circuited. For this reason, a structure in which an insulating material such as a resist is applied to the semiconductor chip mounting area or a structure in which an insulating film is stuck is used.However, the structure has many material interfaces, and the adhesive paste contains voids when the semiconductor chip is bonded. As a result, peeling and package cracking are likely to occur in a moisture absorption reflow test, which causes a decrease in reliability. In addition, dummy patterns may be arranged as necessary in order to equalize the wiring patterns.
Thereby, it is possible to prevent the insulating adhesive film from sinking in the sparse wiring portion, maintain the flatness of the insulating adhesive film, and prevent a gap from being generated between the chip and the insulating adhesive film, Therefore, the adhesiveness between the adhesive film and the chip can be improved. Thereby, reflow resistance and long-term reliability can be improved. Further, by reducing the thickness of the adhesive film to 0.030 mm or less, the volume of a substance causing moisture absorption inside the package can be minimized and the reflow resistance can be increased. However, from the viewpoint of securing insulation resistance, the thickness is 0.005.
mm or more was necessary. By setting the thickness of the insulating film to 0.005 mm or more and 0.030 mm or less, a highly reliable package can be obtained. Such accurate control of the film thickness can be easily achieved by using a film adhesive. Further, a through-hole (a) is formed in a portion of the insulating support substrate where the film adhesive is formed.
Prevents adhesion of air between the film adhesive and the insulating substrate when the film adhesive is bonded to the insulating substrate. If the chip is mounted and sealed while holding air, peeling, cracks, and the like occur in the above-described reflow step, which causes a reduction in reliability. In addition, the through hole allows the moisture absorbed by the adhesive film or the like before the reflow step to be appropriately released from the through hole, thereby preventing peeling or cracking occurring inside the package. Furthermore, by providing at least one or more through-holes (b) at locations where the insulating support substrate is in contact with the sealing resin, a part of the sealing resin flows in the sealing step, and the bonding between the support substrate and the sealing material is performed. It has the effect of raising the quality. Thereby, reflow resistance, long-term reliability, and handling after sealing can be improved. Therefore, according to the present invention, it is possible to prevent a package crack and to manufacture a highly reliable small semiconductor package.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例を説明するための、半導体パ
ッケージ製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor package manufacturing process for explaining one embodiment of the present invention.

【図２】本発明の一実施例の半導体パッケージ用チップ
支持基板の平面図である。FIG. 2 is a plan view of a chip supporting substrate for a semiconductor package according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ ポリイミドボンディングシート ２ アウター接続部 ３ 貫通穴（ａ） ４ 貫通穴（ｂ） ５ インナー接続部 ６ 展開配線 ７ ダミーパターン ８ ダイボンドフィルム ９ 半導体チップ １０ 金ワイヤ １１ 半導体封止用エポキシ樹脂 １２ はんだボール １３ 接着フィルム搭載領域 １４ 封止領域 DESCRIPTION OF SYMBOLS 1 Polyimide bonding sheet 2 Outer connection part 3 Through hole (a) 4 Through hole (b) 5 Inner connection part 6 Development wiring 7 Dummy pattern 8 Die bond film 9 Semiconductor chip 10 Gold wire 11 Semiconductor epoxy resin 12 Solder ball 13 Adhesive film mounting area 14 Sealing area

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山崎 聡夫 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 井上 文男 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 坪松 良明 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 中村 英博 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 阿波野 康彦 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 市村 茂樹 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 湯佐 正己 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 岩崎 順雄 茨城県下館市大字小川1500番地 日立化 成工業株式会社 下館研究所内 (56)参考文献 特開 平10−214928（ＪＰ，Ａ) 特開 平10−12676（ＪＰ，Ａ) 特開 平９−153564（ＪＰ，Ａ) 特開 平10−32300（ＪＰ，Ａ) 特開 平９−74149（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/52 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Toshio Yamazaki 48 Wadai, Tsukuba, Ibaraki Prefecture Within Hitachi Chemical Co., Ltd. Inside the Tsukuba Research Laboratory (72) Inventor Yoshiaki Tsubomatsu 48 Wadai, Tsukuba, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Inside the Tsukuba Development Laboratory (72) Hidehiro Nakamura 48 Wadai, Tsukuba, Ibaraki Hitachi Chemical Co., Ltd. Inside Tsukuba Development Laboratory (72) Inventor Yasuhiko Avano 48 Wadai, Tsukuba, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Within Tsukuba Development Laboratory (72) Shigeki Ichimura 48 Wadai, Tsukuba Ibaraki Prefecture Hitachi Chemical Co., Ltd. Inside Tsukuba Development Laboratory (72) Inventor Masaki Yusa 48 Wadai, Tsukuba City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. 72) Inventor Norio Iwasaki 1500 Ogawa, Shimodate-shi, Ibaraki Pref. Hitachi Chemical Co., Ltd. Shimodate Research Laboratory (56) References JP-A-10-214928 (JP, A) JP-A 10-12676 (JP, A JP-A-9-153564 (JP, A) JP-A-10-32300 (JP, A) JP-A-9-74149 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/12 H01L 21/52

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】Ａ．絶縁性支持基板の一表面には複数の配
線が形成されており、前記配線は少なくとも半導体チッ
プ電極と接続するインナ−接続部及び半導体チップ搭載
領域部を有すものであり、 Ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前
記配線が形成されている箇所であって前記インナ−接続
部と導通するアウタ−接続部が設けらる箇所に、開口が
設けられており、 Ｃ．前記配線の半導体チップ搭載領域部を含めて半導体
チップが搭載される箇所に、絶縁性のフィルム状接着材
が載置形成されており、 Ｄ．前記絶縁性支持基板の前記絶縁性フィルム状接着材
が形成される箇所には、前記絶縁性のフィルム状接着材
の平板性を維持するための少なくとも１つ以上の金属パ
タ−ンが形成されている ことを特徴とする半導体パッケ−ジ用チップ支持基板。1. A. B. A plurality of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part connected to the semiconductor chip electrode and a semiconductor chip mounting area part; In the insulating support substrate, an opening is provided at a position where the wiring of the insulating support substrate is formed and at a position where an outer connection portion that is electrically connected to the inner connection portion is provided. C. B. an insulating film-like adhesive is placed and formed on a portion where the semiconductor chip is mounted including the semiconductor chip mounting region of the wiring; At least one or more metal patterns for maintaining the flatness of the insulating film-like adhesive are formed on the insulating support substrate where the insulating film-like adhesive is formed. A chip supporting substrate for a semiconductor package. 【請求項２】 絶縁性支持基板の絶縁性フィルム状接着
材が載置形成される箇所に、少なくとも１個の第一の貫
通穴が設けられている請求項１記載の半導体パッケージ
用チップ支持基板。2. The semiconductor package chip supporting substrate according to claim 1, wherein at least one first through-hole is provided in the insulating supporting substrate at a position where the insulating film-like adhesive is placed and formed. . 【請求項３】 絶縁性支持基板には半導体チップ封止用
の封止樹脂が被覆される封止領域が設けられ、前記封止
領域には少なくとも１個の第二の貫通穴が設けられてい
る請求項１又は２記載の半導体パッケージ用チップ支持
基板。3. An insulating support substrate is provided with a sealing region covered with a sealing resin for sealing a semiconductor chip, and said sealing region is provided with at least one second through hole. The chip supporting substrate for a semiconductor package according to claim 1. 【請求項４】 金属パタ−ンが複数個形成され、相互間
の間隔が１ミリメートル以下である請求項１〜３各項記
載の半導体パッケージ用チップ支持基板。4. The semiconductor package chip supporting substrate according to claim 1, wherein a plurality of metal patterns are formed, and an interval between the metal patterns is 1 mm or less. 【請求項５】 複数個の金属パタ−ンが、均等配置され
てなる請求項４記載の半導体パッケージ用チップ支持基
板。5. The chip supporting substrate for a semiconductor package according to claim 4, wherein a plurality of metal patterns are evenly arranged. 【請求項６】 請求項１〜５各項記載の半導体パッケー
ジ用チップ支持基板と、前記支持基板のフィルム状接着
材の面に搭載された半導体チップと、前記半導体チップ
を封止する樹脂封止を備える半導体装置。6. The semiconductor package chip support substrate according to claim 1, a semiconductor chip mounted on a surface of a film-like adhesive of said support substrate, and a resin encapsulation for encapsulating said semiconductor chip. A semiconductor device comprising: 【請求項７】 請求項１〜５各項記載の半導体パッケー
ジ用チップ支持基板のフィルム状接着材の面に半導体チ
ップを接着する工程、半導体チップ電極を配線のインナ
−接続部とワイヤーボンディングにより接続する工程、
半導体チップを樹脂封止する工程、前記支持基板の開口
にインナ−接続部と導通するアウタ−接続部を設ける工
程を備える半導体装置の製造法。7. A step of bonding a semiconductor chip to a surface of a film-like adhesive of a chip supporting substrate for a semiconductor package according to claim 1, wherein a semiconductor chip electrode is connected to an inner connection portion of a wiring by wire bonding. Process,
A method of manufacturing a semiconductor device, comprising: a step of sealing a semiconductor chip with a resin; and a step of providing an outer connection portion that is electrically connected to an inner connection portion in an opening of the support substrate.
JP20454697A 1996-07-31 1997-07-30 Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device Expired - Fee Related JP3143081B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20454697A JP3143081B2 (en) 1996-07-31 1997-07-30 Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8-201906 1996-07-31
JP20190696 1996-07-31
JP20454697A JP3143081B2 (en) 1996-07-31 1997-07-30 Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2000115857A Division JP3616742B2 (en) 1996-07-31 2000-04-12 Chip support substrate for semiconductor package

Publications (2)

Publication Number Publication Date
JPH10135247A JPH10135247A (en) 1998-05-22
JP3143081B2 true JP3143081B2 (en) 2001-03-07

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3128548B2 (en) * 1999-03-11 2001-01-29 沖電気工業株式会社 Semiconductor device and method of manufacturing semiconductor device
WO2002027787A1 (en) * 2000-09-27 2002-04-04 Hitachi Chemical Co., Ltd. Semiconductor mounting board, its manufacturing method, semiconductor package comprising this board, and its manufacturing method
KR100386209B1 (en) * 2001-06-28 2003-06-09 동부전자 주식회사 Semiconductor substrate for a ball grid array package
US9601451B2 (en) 2015-08-11 2017-03-21 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Apparatus and methods for creating environmentally protective coating for integrated circuit assemblies

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