JP2626473B2 - Electronic musical instrument input control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a maximum peak point and a minimum peak point for extracting pitch information used for tone generation control of a musical tone from a digital waveform signal obtained by digitizing an input waveform signal generated according to a performance operation. Extract each timing of
The present invention relates to an input waveform control device .

[0002]

2. Description of the Related Art A pitch cycle of a signal is extracted in real time from an input waveform signal such as a string vibration waveform generated by a plucking operation of a string of a guitar or the like, and is configured by a digital circuit or the like based on the pitch cycle. An electronic musical instrument has been developed which controls a generated tone generating circuit to synthesize a musical tone and sound it.

In such an electronic musical instrument, for example,
In the case of a child guitar, one of the six strings (not shown) is
The corresponding hexapick-up
The string vibration waveform signal is detected from the electromagnetic pickup
You. And this signal is filtered by low pass filter
And a pitch period T as shown in FIG. 12, for example.₀~ T
_FiveIs obtained. Continued
From this signal, each peak value and each zero clock
Time data set (a₀, T₁), (B)₁, T _Two),
(A₁, T_Three), ... etc. are detected and these data
By performing a logical correction process on the set of
The interval between the maximum peak points or the interval between the minimum peak points or
Each pitch period T is defined as an interval between zero crossing time points.₀~
T_FiveEtc. are extracted in real time. And each pitch
Each time a period is extracted, corresponding pitch information is generated,
The musical tone of the pitch is generated by the musical tone generating circuit.

Therefore, if the player changes the tension of the picked string by performing a choking operation on the guitar or operating a tremolo arm for changing the tension of the string after the start of sounding, according because each pitch period T ₀ through T ₅ of the digital waveform signal D1 of FIG. 12 is changed, it is possible to vary in real time accordingly also the sound of a musical tone to be sounded higher, adding expressive the tone.

[0005] The above conventional example, the negative peak value b ₀ of the digital maximum peak point of the waveform signal D1 (the time of such positive peak value a ₀ ~a ₃ in FIG. 2) and the minimum peak point (Fig. 2 in FIG. 12 ~b
It is important how to accurately extract the timing ( _3rd time point) in order to perform accurate pitch extraction.

For this reason, a circuit is generally provided for storing the digital waveform signal D1 while subtracting (attenuating) the past peak value for each of the positive amplitude side and the negative amplitude side of the digital waveform signal D1, after the previous peak value is detected. From the subtraction circuit shown in FIG.
2, a threshold signal p whose absolute value of the amplitude gradually decreases
Or q is generated. Then, the point in time when the amplitude value of the digital waveform signal D1 exceeds the value of the threshold signal p or q in the positive or negative direction is detected, whereby the control signal for peak detection as shown in FIG. A certain maximum peak value detection signal MAX or a minimum peak value detection signal MIN rises to a high level. Further, immediately after the detection time point, when the digital waveform signal D1 changes from the increasing direction to the decreasing direction (positive amplitude side) or from the decreasing direction to the increasing direction (negative amplitude side), the maximum peak value detection signal MAX or the minimum peak value detection is performed. The signal MIN falls to a low level, and the timing of each peak value is detected as the timing. Here, even if pseudo peaks based on harmonic components and the like exist between the true peak points corresponding to the pitch period, the absolute values of those peaks are usually smaller than the absolute values of adjacent true peaks. , Do not exceed the threshold signal p or q. This allows
Only the timing of the true peak value can be accurately extracted.

In the timing of the zero-cross times t _{0 to} t ₇ , the polarity of the amplitude of the digital waveform signal D 1 changes immediately after the timing at which the maximum peak value detection signal MAX or the minimum peak value detection signal MIN falls. Detected as timing.

[0008]

Here, in the case of a general electronic guitar or the like, since there are six strings, for example, there are six types of signals detected as a string vibration waveform signal. Therefore, in the case of the above-described conventional example, the digital waveform signal D1 in FIG. 12 is a signal obtained by multiplexing a string vibration waveform signal for six strings in a time division manner, and the signal is subjected to time division processing. As a result, a pitch period corresponding to each of the six strings is extracted, and six kinds of musical tones are auditorily simultaneously generated.

In this case, two types of threshold signals p and q corresponding to the positive amplitude side and the negative amplitude side are required for a signal corresponding to one string, as shown in FIG. Therefore, 6
In order to detect the timing of each peak value from the digital waveform signal D1 obtained by time-division multiplexing a string, twelve types of threshold signals are required, and the time division for peak value timing detection using the threshold signals is required. The processing also requires 12 time division processing. Then, a 12-stage shift register is required to independently store the above 12 types of threshold signals.

As described above, the conventional processing circuit for extracting the peak value or the zero crossing time needs to perform the time division processing at twice the speed of the number of simultaneously input waveform signals.
The load in terms of processing speed increases, and the number of stages of a shift register for storing a threshold signal, which is twice as many as the number of waveform signals, is required. However, there is a problem that the electronic musical instrument has a high performance.

An object of the present invention is to reduce the processing speed and hardware load when extracting a peak value or the like.

[0012]

SUMMARY OF THE INVENTION The present invention relates to an input waveform signal.
And a polarity detecting means for detecting the polarity of.

[0013] The means is capable of, for example, changing the voltage value of the input waveform signal.
Compared to ground potential, if higher than ground potential, high level
Output a low-level signal if it is small.
It is a comparator.

Next, based on the result of the polarity detection by the polarity detection means, a portion having a negative polarity in the input waveform signal is inverted to a positive polarity, and converted so that the input waveform signal contains only a signal component of a positive polarity. And a polarity converting means. The means is, for example, a circuit that outputs the voltage value of the input waveform signal as it is when the output of the comparator is at a high level, and inverts and outputs the voltage value of the input waveform signal with an inverting amplifier when the output is at a low level.

Further, there is provided storage control means for storing the positive polarity waveform signal from the polarity conversion means while reducing the past peak value of the signal. The means, for example, after digitizing the positive polarity waveform signal, a register for temporarily storing the positive polarity waveform signal digitized at the previous output timing of the maximum or minimum peak value detection signal described later, and then, , A subtraction circuit that subtracts the output of the register at each processing timing until a maximum or minimum peak value detection signal is output.

Then, after the previous peak value of the positive polarity waveform signal is detected, the output signal of the storage control means is used as a threshold signal, and the time when the positive polarity waveform signal next exceeds the threshold signal is detected. If the means detects the positive polarity from the input waveform signal, the maximum peak value detection signal is output immediately after the detection time, and if the means detects the negative polarity, the minimum peak value detection signal is output immediately after the detection time. It has a detecting means. The means includes, for example, a comparator that outputs a high-level signal when the amplitude value of the positive waveform signal exceeds the amplitude value of a threshold signal that is an output signal of the storage control means, and the output of the comparator becomes high. When the output of the comparator is at a high level (a positive input signal), the maximum peak value detection signal is raised to a high level, and when the output of the comparator is a low level (a negative input waveform signal), The minimum peak value detection signal rises to a high level, and immediately after that, when the change of the positive polarity waveform signal changes from increase to decrease, the maximum or minimum peak value detection signal that rises to a high level falls to a low level. Circuit.

In the above arrangement, when there are a plurality of input waveform signals, for example, each string vibration waveform signal corresponding to each of the six strings of the electronic guitar, each of the above means operates in a time division manner, and , The respective input timings of the maximum peak value and the minimum peak value are detected, whereby the pitch information corresponding to each input waveform signal is detected, and the tone control of a plurality of musical tones corresponding to each pitch information is simultaneously performed. In this case, as many threshold signals as the number corresponding to the plurality of input waveform signals are prepared, and therefore, the storage control means stores and outputs each threshold signal in synchronization with each time division process, for example, It is composed of a shift register or a RAM.

[0018]

The operation of the present invention is as follows. The timing of the maximum peak value or the minimum peak value for extracting the pitch information is detected based on a threshold signal gradually decreasing from the past peak value. Therefore, even if there are pseudo peaks based on harmonic components and the like between the true peak points corresponding to the pitch period, the absolute values of those peaks are usually smaller than the absolute values of adjacent true peaks and do not exceed the threshold signal. Therefore, only the timing of the true peak value can be accurately extracted.

Here, when there are a plurality of input waveform signals, such as each string vibration waveform signal corresponding to each of the six strings of the electronic guitar,
As described above, each means of the present invention operates in a time-division manner, and the input timings of the maximum peak value and the minimum peak value are detected from each of the input waveform signals. In this case, only one type of threshold signal is generated and used corresponding to one input waveform signal (positive waveform signal). This is に 対 し て of the two types of the conventional example.

Therefore, for example, to detect the timing of each peak value from the input waveform signal for six strings of the electronic guitar,
It is sufficient to prepare six types of threshold signals, and the time-division processing using those threshold signals may be the six-time-division processing.
Then, a six-stage shift register may be prepared to store the threshold signal.

That is, both the speed of the time-division processing and the hardware scale of the memory, for example, the shift register and the RAM, can be halved as compared with the conventional example.

[0022]

Embodiments of the present invention will be described below in detail. In the following description, the symbols ｛｝, (
), <<> and <>, and the items are sequentially sorted in the order of the underlined headings. << Overall Block Diagram of Embodiment of the Present Invention >> In this embodiment, six metal strings are stretched on the body, and while holding down a fret (fingerboard) on a finger board provided under the metal strings with a finger. It is realized as an electronic guitar that performs by picking a desired string. The appearance is omitted.

FIG. 1 is an overall block diagram of the present embodiment. First, the pitch extraction analog unit 102 converts various waveform signals corresponding to each string output from a hexapickup provided for each of the six strings (not shown) for converting the vibration of each string into an electric signal. (To be described later).

The pitch extraction digital section 103 generates various parameters (to be described later) such as a peak value for pitch extraction and a zero crossing time based on each signal from the pitch extraction analog section 102, and outputs the parameters to a central control unit (MCP). By applying an interrupt to the MCP 101 via the bus BUS, the above-mentioned various parameters are output to the MCP 101.

Next, based on various information from the pitch extraction digital section 103, the MCP 101 detects which of the strings is picked, and detects a pitch period (frequency) from the picked string. Then, information on the start of sound generation based on the pitch corresponding to the pitch cycle is output to the tone generation circuit 104.

Further, after the MCP 101 starts sounding, the player performs a choking operation on the above-mentioned string (not shown) on the fingerboard, or operates a tremolo arm (not shown) to pick the string. In the case where the tension of the string is changed, the change of the pitch period of the picked string vibration is extracted based on the information from the pitch extraction digital unit 103, and the information supporting the change of the pitch based on this is extracted. To the tone generation circuit 104.

The above control operation is performed based on a control program stored in a ROM (Read Only Memory) (not shown) in the MCP 101. continue,
The tone generator 104 of FIG. 1 reads out and outputs a digital tone waveform stored in a waveform ROM (not shown) based on various tone control information from the MCP 3.
In this case, the waveform reading means (not shown)
By reading digital musical tone waveforms from the waveform ROM at address intervals corresponding to the pitch specified by P101, the pitch of musical tones is controlled.

The D / A converter 105 is connected to the tone generation circuit 10.
4 is converted into an analog musical sound waveform, and this waveform is amplified by an amplifier 106 and then emitted from a speaker 107.

When the tone generation circuit 104, the D / A converter 105, the amplifier 106, the speaker 107, and the like are provided as a separate sound source outside the main body of the string extending portion, which is a performance portion, the MCP 101 and the MCP 101 The tone generating circuit 104 includes a dedicated bus MI for transferring tone control information as shown in parentheses in FIG.
DI-BUS (MIDI: Musical Instrument Digital
Interface). << Schematic Operation of the Present Embodiment >> The schematic operation of the block configuration shown in FIG. 1 will be described below.

First, D1 in FIG. 2 (waveform indicated by a solid line)
Is the pitch extraction from the pitch extraction analog section 102 in FIG.
Of the digital waveform signal D1 output to the digital section 103
This is an analog representation of one string. This wave
Pick one of the six strings (not shown)
The corresponding hexa pickup
After filtering the detected electrical signal with a low-pass filter
(To be described later), which is output as a digital signal.
The string is attached to each of the above-mentioned frets, not particularly shown.
Picking while pressing on the covered fingerboard
2T ₀~ T_FivePitch circumference as shown
A periodical vibration waveform is generated. Note that the actual one string
The digital waveform signal D1 has the waveform portion on the negative amplitude side
This is a waveform folded back to the positive amplitude side like a line. to this
This will be described later.

Next, in this embodiment, the pitch extraction digital section 103 of FIG. 1 converts the digital waveform signal D1 of FIG.
Extracting the peak value a ₀ ~a ₃ or b ₀ ~b _3, etc., to extract zero-crossing time t ₀ ~t ₇ like just after the same time the peak value. These data are sequentially transferred to the MCP 101 via the bus BUS by outputting an interrupt signal INT to the MCP 101 in FIG.

By the above operation, when the first data set (b ₀ , t ₀ ) is input, the MCP 101 determines that the corresponding string has been picked, and starts a pitch period detecting operation.

Thereafter, when an interrupt signal INT is input from the pitch extraction digital section 103 and the interrupt is applied, a set of data (a ₀ , t ₁ ), (b ₁ , t ₂ ), (a)
_1, t _3), ... From such, via a logical correction, it extracts each pitch period T ₀ through T _5, etc. in FIG. 2 in real time. As a result, the MCP 101 generates pitch information based on the most recently obtained pitch cycle, and causes the tone generation circuit 104 to generate a tone at that pitch.

Therefore, if the player changes the tension of the picked string by performing the above-mentioned choking operation or particularly by operating the tremolo arm (not shown) after the start of sound generation, Since the pitch periods T _{0 to} T _{5 and the} like of the digital waveform signal D1 change, the pitch information also changes accordingly in real time,
Rich expressions can be added to musical sounds.

Since the above operation is time-division-processed for each output of the hexa pickup of the six strings of the guitar (the digital signal waveform D1 becomes a time-division signal of six strings as will be described later). From the circuit 104, musical tones of six strings can be simultaneously generated acoustically. These musical tones can be set to any volume and tone freely, and various effects can be electronically added, so that an extremely large performance effect can be obtained.

Of the above operations, the digital waveform signal shown in FIG.
Peak value a from D1₀~ A_ThreeOr b ₀~ B_ThreeAnd it
Zero-crossing time t immediately after₀~ T₇For detecting
The configuration and operation of the pitch extraction digital section 103 are the same as those of the present invention.
Particularly relevant to. The configuration and operation are described below in order.
I will tell. ｛Explanation of analog section for pitch extraction｝ First, the pitch extraction shown in FIG.
The output analog section 102 will be described. (Brief descriptionHere, from the above-mentioned hexa pickup
Of the six types (corresponding to each string) through a low-pass filter
By removing the harmonic components, 6 types of each waveform
Get the signal. Further, the sign of the amplitude of each waveform signal is positive or negative.
Each time it changes to a high or low level
It generates six kinds of zero-cross signals in the shape of a circle. And this
These six types of waveform signals and zero cross signals are gated
Time-division digital waveform signal by a channel or A / D converter
Signal D1 and time-division serial zero-cross signal ZCR.
In addition, pitch extraction digital
Output to the unit 103. (ConstitutionFIG. 3 shows the pitch extraction analog section 10 of FIG.
2 is a circuit diagram showing the details of the above-mentioned hexapick-up.
The input waveform signal corresponding to each string from the
Input terminals 334- of the filters (LPF) 301-306
339, where it is amplified and the high frequency component
Is removed, and the basic waveforms W1 to W6 are extracted. This b
-Pass filters 301 to 306
Considering that the frequency is within two octaves, each string
Each set to a different cutoff frequency
Is used.

The outputs of the low-pass filters 301 to 306, ie, the waveform signals (peak values) W1 to W6 are output as they are, and the waveform signals (peak values) W1 to W6 are input to zero-cross comparators 307 to 312, respectively. The zero-cross signal Z is compared with the signal ground potential.
1 to Z6 are generated.

The zero-cross signals Z1 to Z6 are applied to the inputs of a zero-cross parallel-serial conversion unit composed of AND gates 313 to 318 and OR gate 325, that is, to AND gates 313 to 318.
1 to Φ6, and are converted into a serial zero-cross signal ZCR. Here, when the zero cross signals Z1 to Z6 are positive, the logic "1" is output as the serial zero cross signal ZCR, and when the zero cross signals Z1 to Z6 are negative, the logic "0" is output as the serial zero cross signal ZCR.

On the other hand, waveform signals W1 to W6 from low-pass filters 301 to 306 are supplied to analog gates 319 to 3 respectively.
24, which is applied to an analog-parallel-serial conversion unit, that is, analog gates 319 to 324.
The pulses are input in correspondence with sequential pulses Φ1 to Φ6 described later, and are converted into analog serial signals. Here, when the pulses Φ1 to Φ6 are sequentially at a high level, the corresponding analog gates 319 to 324 are in an open state, and when the pulses Φ1 to Φ6 are at a low level, the analog gates 319 to 324 are in a closed state. These outputs are input to the inverting amplifier 329 to which the resistors 330 and 331 are connected, where the positive and negative waveforms are all inverted to the positive side. That is, the OR gate 325
Is input directly to the gate terminal of the analog gate 327 and to the gate terminal of the analog gate 328 via the inverter 326. Then, the output of the inverting amplifier 329 is input to the input terminal of the analog gate 328, and the analog gate 32
The output of 8 is always a positive value. On the other hand, the analog gate 327 is turned on when the serial zero-cross signal ZCR is at logic “1”, so that the analog gate 31
As a result of outputting the output terminals 9 to 324 to the output terminal of the analog gate 327, the output always has a positive value.

The analog gates 327 and 32
8 is converted to a log (log) conversion circuit 332 as V _IN.
, Where the data is log-compressed by log conversion to reduce the required memory bits. The output V _OUT of the log conversion circuit 332 is converted by an analog-to-digital converter A / D (hereinafter, referred to as an A / D converter) 333 into a time-division digital waveform signal D1 according to the state of the AD conversion clock signal ADCK. Is done. ( Detailed Operation ) FIG. 4 is an operation timing chart for explaining the operation of the pitch extraction analog section 102 of FIG. 1 or FIG. First, the sequential pulses Φ1 to Φ6 are sampling clocks corresponding to each string (sixth string) output from a timing generator 705 (see FIG. 7) described later, and A / D conversion generated from the timing generator 705, respectively. Has a period six times that of the AD conversion clock signal ADCK for operating the detector 333,
.PHI.6 are generated with a phase shift by one period of the AD conversion clock signal ADCK.

Therefore, the above-mentioned sequential pulses Φ1 to Φ6 sequentially control the AND gates 313 to 318,
The OR gate 325 after each of the zero-cross signals Z1 to Z6 corresponding to the waveform signals W1 to W6 for the six strings is sampled.
And is output as a serial zero-cross signal ZCR shown in FIG.

FIG. 5 shows, in the configuration of FIG. 3, a sequential pulse Φ1, a waveform signal W1, an input voltage V _IN of the log conversion circuit 332, and an output voltage V _OUT when the first string is played.
It is a timing chart of a serial zero cross signal ZCR. As is clear from this figure, the log conversion circuit 332
, The data is logarithmically compressed, whereby the number of bits when performing quantization in the A / D converter 333 can be reduced (this will be described later).

The waveform signals W2 to W corresponding to the other strings
6 is also processed in a time-division manner in accordance with the respective clocks Φ2 to Φ6. In this case, the V _IN , V _OUT , and ZCR signals are time-division multiplexed in the shaded areas in FIG.

The time-division multiplexed signal V
_OUT is quantized to 8 bits (256 levels) based on the AD conversion clock signal ADCK in the A / D converter 333 (FIG. 3), and an 8-bit digital waveform signal in which six strings are time-division multiplexed. Output as D1.

FIGS. 6A and 6B respectively show the input V _IN to the log conversion circuit 332 and the output V _IN of the log conversion circuit 332 in FIG.
_It shows the envelope (envelope) of the amplitude value of each signal of _OUT (both refer to FIG. 5). Where V _IN , V
_OUT is a signal based on any one of the above-described waveform signals W1 to W6. Therefore, the envelope finally indicates the envelope of the string vibration of each string.

The point to be noted here is the note-on time. In the present embodiment, it is detected that the amplitude value at the time of the rise of the string vibration is equal to or greater than a predetermined threshold value, and the musical tone is note-on (start of sound generation). Detects that it is below the threshold, and turns off the note. Then, during the note-on time from note-on to note-off, pitch control and the like based on pitch extraction are performed. Here, in order to reflect the fine nuance of string vibration due to the picking of a string into the tone generation, the above-mentioned threshold value (hereinafter referred to as a note-off threshold value) is used.
Is desirably set as low as possible.

On the other hand, the above note-on and note-off processes are performed for the digital-value note-off threshold with respect to the output digital waveform signal D1 of the A / D converter 333 in FIG. This is done by setting a value.

Therefore, when the A / D converter 333 quantizes the amplitude value of the input V _OUT , it is better to quantize the low range of the amplitude value as finely as possible. It becomes easy to set the threshold to a low amplitude level.

In order to realize the above operation, the number of quantization bits is large (for example, 10 bits (= 1024 levels or more)).
An A / D converter 333 may be used.
Since the / D converter is expensive, only an 8-bit (= 256 level) A / D converter can be used to reduce the cost in practice.

Therefore, in this embodiment, the A / D converter 333
A low-cost log conversion circuit 332 is provided before the
_The above operation is realized by converting _IN into an output _VOUT whose low amplitude value range is amplified in a logarithmic function in advance and inputting it to the A / D converter 333. This allows
As shown in FIG. 6 (b), even with the same note-off threshold value (digital value) as in FIG. 6 (a), the threshold value can be set with a much lower amplitude value for the original string vibration waveform. That means
The substantial note-on time can be made longer than in the case of FIG. 6 (a), and finer tone control can be performed.

As described above, the pitch extraction analog section 102 shown in FIG. 1 or FIG.
An 8-bit digital waveform signal D1 (a signal obtained by quantizing each amplitude value of V _OUT in FIG. 5) obtained by time-division multiplexing the output of a string, and a 1-bit serial zero-cross signal ZCR similarly time-division multiplexed (see FIG. 5) and zero-cross signals Z1 to Z6 for six strings are generated and supplied to the pitch extraction digital unit 103 in FIG. << Description of Pitch Extraction Digital Unit >> FIG. 7 is a block diagram showing the overall configuration of the pitch extraction digital unit 103 of FIG.
Detection circuit 701 for outputting a signal for detecting a peak point corresponding to each of the strings MIN 1 to MIN 6 or MIN 1 to 6, and a time constant conversion control circuit 7 for converting the time constant of the peak detection circuit 701
04, a zero-cross time acquisition circuit 702, a peak value acquisition circuit 703, and various timing signals, that is, pulses Φ1 to Φ6, a timing signal ADCK,
And Q5

[0052]

[Outside 1]

It comprises a timing generator 705 to be generated, and these will be sequentially described below. ( Description of Peak Detection Circuit ) First, the peak detection circuit 701 in FIG. 7 will be described. << Schematic Description >> This circuit is a part which is most relevant to the present invention, and as shown in FIG. 2, a digital waveform signal obtained by time-division multiplexing of six strings output from the pitch extraction analog unit 102 of FIG. 1 or FIG. D1 and based on the serial zero-crossing signal ZCR, each string maximum peak point of the corresponding time division signal (the time of such positive peak value a ₀ ~a ₃ in FIG. 2) and the minimum peak point of the digital waveform signal D1 (in Fig. 2 The timing of the negative peak values b _{0 to} b _3, etc.) is detected by time-division processing, and maximum peak value detection signals MAX1 to MAX6 and minimum peak value detection signals MIN1 to MIN6 corresponding to six strings are output.

For this purpose, a circuit is provided in the peak detection circuit 701 for subtracting (attenuating) the past peak value of each string and storing the subtracted value as described later. Then, after detecting the previous peak value for each string, the peak detection circuit 701 uses the output signal of each string output from the subtraction circuit as a threshold signal and performs time-sharing of the digital waveform signal D1 for each string. Next, the point in time when the signal exceeds the value of the threshold signal is detected, and the timing of the peak value for each string is detected as the input timing of the peak value immediately after that point.

At this time, as already described with reference to FIG. 5, the negative waveform side of the original waveform signals W1 to W6 (see FIG. 3) is inverted in polarity to the positive amplitude side, and the digital waveform signal D1 is inverted.
As input. That is, regarding the digital waveform signal D1 for one string in FIG. 2, the signal on the positive amplitude side is input as it is, and the signal on the negative amplitude side is input after being turned back to the positive side as shown by the broken line in FIG. In response to this signal, the peak detection circuit 701 uses the dashed line r in FIG.
Is generated, and each timing at which the digital waveform signal D1 having only the positive amplitude value exceeds the threshold signal is extracted. At each of these timings, if the serial zero cross signal ZCR is at a high level, the maximum peak value detection signals MAX1 to MAX6 rise to a high level, and if the ZCR is at a low level, the minimum peak value detection signals MIN1 to MIN6 are at a high level. Stand up to the level. Further, immediately after this timing, at the timing when the amplitude change of the digital waveform signal D1 having only the positive amplitude value shown in FIG. 2 changes from increase to decrease, each of the peak value detection signals falls to the low level. The timings of the maximum peak value and the minimum peak value of the digital waveform signal D1 are extracted as the falling timing.

Here, in the case of the conventional example shown in FIG. 12, threshold signals p and q are generated for each of the positive and negative amplitude sides of the digital waveform signal D1 as described above, and these signals correspond to six strings. is necessary. Therefore, in order to detect the timing of each peak value from the digital waveform signal D1 for six strings, twelve types of threshold signals are required, and time-division processing for peak timing detection using the threshold signals is also required.
Time division processing is required. A 12-stage shift register is required to store the above 12 types of threshold signals.

On the other hand, in the present embodiment described below, only one type of threshold signal r is generated for the digital waveform signal D1 for one string having only a positive amplitude value as shown in FIG. ·used. Therefore, in order to detect the timing of each peak value from the digital waveform signal D1 for six strings, it is sufficient to prepare six types of threshold signals, and the time division processing using those threshold signals is also performed in six time divisions. Processing is fine. In order to store the threshold signal, a six-stage shift register may be prepared, and the size of the shift register can be reduced to half.

Hereinafter, the configuration and the detailed operation for realizing the above operation will be sequentially described. << Configuration >> FIG. 8 is a detailed circuit diagram of the peak detection circuit 701 in FIG. This circuit performs the 6-time division processing on the 6-string time-division signal of the digital waveform signal D1 as described above, and outputs the maximum peak value detection signals MAX1 to MAX6 and the minimum peak value detection signals MIN1 to MIN6.

As shown in FIG.
Has a 12-bit configuration and is a 6-time division process, that is, a 12-bit × 6-stage shift register. In each of the 12 bits, the upper 8 bits are an integer part and the lower 4 bits are a decimal part. The decimal part is provided to ensure the accuracy of a subtraction process described later. The clock terminal CK of the shift register 801 has a signal obtained by inverting the A / D conversion clock signal ADCK from the timing generator 705 of FIG.
Outside 2 is input, and it turns right at this rising edge.

[0060]

[Outside 2]

Turn over. The upper 8 bits of the stored value 827 stored in the shift register 801 are input to a gate 813, which is controlled to open and close by a control signal PR from a gate control circuit 814.

The gate control circuit 814 includes a 2-bit counter 815, OR gates 816 to 818 and 821, and AND gates 817 and 820. First, the sequential pulses Φ1 and Φ2 input to the OR gate 816 are output as the control signal PR via the OR gate 821 as they are. On the other hand, the sequential pulse Φ input to the OR gate 817
3, .phi.4 is to be outputted through the AND gate 819, the lower bit output terminal Q _A of the counter 815 is output only period is a logic "1". Also, OR gate 8
Sequentially pulses Φ5 is input to 18, .phi.6 is to be outputted through the AND gate 820, the upper bit output Q _B and the lower bit output Q _A of the counter 815 is output only period is a logic "1" together . Here, the counter 8
The 15 outputs Q _B and Q _A are sequentially synchronized with the pulse Φ1 at (0, 0) (0, 1) (1, 0) (1, 1) (0, 0).
... and changes cyclically. The gate 813 is turned on at the timing when the control signal PR output as described above becomes high level.

The output of the gate 813, that is, the shift register 8
01 is input to the shifter 803. Here, by dividing the input signal by 8 bits or 4 bits, 1/256 or 1/16 division is executed. The switching between the two types of shifts is performed by a time constant change signal GX input to a terminal SEL from a time constant conversion control circuit 704 in FIG. 7 described later.

The 4-bit output of the shifter 803 is input to the second input terminal B of the subtracter 802. Subtractor 802
Of the shift register 801 from the first input terminal A of the
The stored value 827 of the bit is input. Here, as described later, the A input-B input is calculated, and the 12-bit output terminal S is calculated.
, But at this time, the carry-in input terminal CIN
Is input with logic "1". This will also be described later.

Next, when a logic “1” is output from the inverter 810, when the logic “1” is output from the output terminal S of the subtractor 802,
Of the 12-bit output, the upper 8 bits (integer part) are input to the shift register 801 via the data switch 805, and the lower 4 bits (decimal part) are input to the AND gate 80.
6 to 809 are input to the shift register 801. When the output of the inverter 810 is logic "0", a new 8-bit digital waveform signal D1 from the A / D converter 333 (see FIG. 3) in the pitch extraction analog section 102 in FIG. The data is input to the shift register 801 via the switch 805. At this time, since the AND gates 806 to 809 are turned off, the lower 4 bits, that is, the decimal part, becomes zero input.

On the other hand, an 8-bit digital waveform signal D 1 is input to the first input terminal A of the comparator 804, and the stored value 82 of the shift register 801 is input to the second input terminal B.
The upper 8 bits (integer part) of 7 are input. This comparator 8
04 is inverted by an inverter 810, and then the data changeover switch 805 and AND gates 806 to 809 are output.
Control.

Next, the serial zero-cross signal ZCR from the pitch extraction analog section 102 shown in FIG. 1 or 3 is output from the comparator 804 and the timing generator 705 shown in FIG.
Together with the timing signal Q5 from the serial / parallel conversion circuit 822. The outputs of the AND gates 823 to 826 are output together with the sequential pulses Φ1 to Φ6 from the timing generator 705 and AND gates ANDia to AND
id (i = 1 to 6) and outputs of the respective AND gates are flip-flops FFia and FFib (i = 1
To 6). Thereby, the parallel maximum peak value detection signals MAXi (i = 1 to 6) and the minimum peak value detection signals MINi (i = 1 to 6) for the six strings are output.

In the configuration of the peak detection circuit shown in FIG. 8, reference numerals 811 and 812 are not used in this embodiment. The description below per operation of the peak detection circuit 701 of FIG. 7 or FIG. 8 (Operation) The configuration.

First, the pitch extraction analog section 102 shown in FIG.
In the digital waveform signal D1 output from the A / D converter 333 (FIG. 3), six sequential pulses Φ1 to Φ6 synchronized with the AD conversion clock signal ADCK become logic “1” as shown in FIG. In synchronization with the waveform signals W1 to W6
A digital version of W6 (see FIG. 3) is time division multiplexed. However, similarly to FIG.
There is a delay from 1 to Φ6 by the conversion time Δt of the AD converter 333 (FIG. 3), which will be described later.

On the other hand, the shift register 80 shown in FIG.
Timing at which stored value 827 of 1 is output and subtractor 8
02, the shifter 803, the comparator 805, and other gates, etc.
It operates at the rising edge of.

[0071]

[Outside 3]

< Process for First String > Now, the pulse Φ
Attention is paid only to the processing for the first string synchronized with 1. First
The waveform signal W1 corresponding to the string is sequentially pulsed in the pitch extraction analog section 102 of FIG. 1 or FIG. 3 as shown in FIG. 5 in the "detailed operation" section of the above "description of the pitch extraction analog section". The waveform signal W1 is digitized in synchronization with Φ1, but the polarity of the negative amplitude side of the waveform signal W1 is inverted to the positive amplitude side and output. Then, a serial zero-cross signal ZCR which becomes logic "1" when the waveform signal W1 is on the positive amplitude side and becomes logic "0" when on the negative amplitude side is simultaneously output. This signal is also time-division multiplexed for 6 strings, and the
The part synchronized with 1 corresponds to the first string.

Therefore, the peak detection circuit 7 shown in FIG.
In step 01, the following processing is performed on the digital waveform signal D1 that is input with both the positive amplitude side and the negative amplitude side mixed as the positive amplitude side as described above.

First, as shown in FIG. 10, an integer value n = 1 in which the value synchronized with the rising of the pulse Φ1 sequentially increases by one.
Consider discrete times represented by n ₁ , n ₂ , n ₃ ,. Note that the actual time is a value obtained by sequentially multiplying the integer value by the period of the pulse Φ1.

Then, of the digital waveform signal D1,
A time-division signal corresponding to the first string input every discrete time n
x (n). It should be noted that in FIG.
(N_Two) (Positive amplitude side), x (n₈) (Negative amplitude side) only
However, the same applies to the other bar graphs.
You. In addition, a sequence corresponding to the first string that is sequentially synchronized with the pulse Φ1
Let the real zero cross signal be z (n). In the figure, the representative
Z (n_Two), Z (n ₇) Only, but other
The same applies to the portion shown in a bar graph.

Further, the stored value 827 corresponding to the first string output from the shift register 801 at each discrete time n is represented by r (n). Although only r (n ₇ ) (positive amplitude side) and r (n ₁₁ ) (negative amplitude side) are typically shown in the figure, the same applies to other plots indicated by “•”.

Each time n ₁ , n ₂ , n in FIG.
_3, processing for every ··· x (n) are sequentially pulsed Φ1 As already indicated in FIG. 9 is performed at the timing when a logic "1". Hereinafter, all processes are performed at this timing unless otherwise specified.

[0078] Now, stored value 827 of the shift register 801 in FIG. 8, and including are all 0, positive at discrete time n ₁ as shown in FIG. 10 of the digital waveform signal x
It is assumed that (n ₁ ) has been input. As a result, in the comparator 804 of FIG. 8, since A input> B input, the output of the comparator 804 outputs a logical “1”, and the output of the inverter 810 becomes a logical “0”.

As a result, the data changeover switch 805
Connected to terminal B and AND gates 806-809
It becomes. Therefore, through the same switch 805, FIG.
N ₁Digital waveform signal x (n₁), Shift cash register
This is stored in the upper 8 bits (integer part) of the star 801.

This storage operation is performed in the middle of the timing at which the sequential pulse Φ1 becomes logic “1” in FIG.
The inverted AD conversion clock signal 4 rises (AD
conversion

[0081]

[Outside 4]

Since the clock signal ADCK falls), the digital waveform signal D is generated as shown in FIG.
There is no problem if 1 = x (n ₁ ) is input after being delayed by the conversion time Δt of the AD converter 333 (FIG. 3).

At the same time, both the output of the comparator 804 and the serial zero-cross signal z (n ₁ ) (ZCR) become logic “1”, whereby the timing signal Q shown in FIG.
AND gate 824 at the timing when 5 becomes logic "1"
Is turned on, and the pulse Φ1 is sequentially at logic “1”, and as shown in FIG.
1b becomes logic "1" and the flip-flop F
F1a is set. Thus, in the middle of the timing of sequential pulses Φ1 at discrete time n ₁ is at logical "1", the maximum peak value detection signal MAX1 corresponding to the first string is the output of the flip-flop FF1a is shown in FIG. 9 or 10 Rise to logic "1".

Subsequently, the shift register 801 is shifted by 6 clocks of the AD conversion clock signal ADCK.
At a discrete time n ₂ of 0, a digital waveform signal x having a larger value than the previous time (discrete time n ₂ ) as shown in FIG.
It is assumed that (n ₂ ) is input. At the same time, the stored value r (n ₂ ) output from the shift register 801 is equal to the previous digital waveform signal x (n ₁ ), and r
(N ₂ ) = x (n ₁ ). Therefore, FIG.
Outputs the logic “1”, and the
The output of 0 outputs the logic "0" as before. Thus, the digital waveform signal x (n ₂ ) is stored in the shift register 801 via the data changeover switch 805 as in the previous case.

The above operation is the same at the discrete time n ₃ , and the digital waveform signal x (n ₃ ) is
01 is stored. Subsequently, a digital waveform signal x (n ₄ ) is input at discrete time n ₄ , and at the same time, a stored value r (n ₄ ) = x (n ₃ ) = a from the shift register 801.
₀ is output. In this case, x (n ₄ ) <r
(N ₄ ), the output of the comparator 804 is logic “0”.
Becomes This output is input to the AND gate 823 with negative logic, and at the same time, the serial zero cross signal z (n ₄ )
When the logic “1” of (ZCR) is input to the AND gate 823, the AND gate 823 is turned on at the timing when the timing signal Q5 shown in FIG. 9 becomes the logic “1”, and the pulse Φ1 sequentially outputs the logic “1”. ", The output of the AND gate AND1a is logic" 1 ".
As a result, the flip-flop FF1a is reset. Thus, in the middle of the timing of sequential pulses Φ1 of discrete time n ₄ is a logic "1", logic "0 as the maximum peak value detection signal MAX1 is 10 corresponding to the first string is the output of the flip-flop FF1a ".

As described above, the digital waveform signal x of the first string
As (n), the maximum peak value x (n ₃ ) as shown in FIG.
= To n ₄ after one discrete time a ₀ is input, the first string of the maximum peak value detection signal MAX1 logic by falls it to "0", the maximum peak value a ₀ as its 1 discrete time before the timing Input timing can be detected.

On the other hand, at the same time as the above operation, the output of the comparator 804 becomes logic “0” at the discrete time n ₄ in FIG. 10, and the inverter 810 outputs logic “1”. The terminals are connected to the terminal A, and the AND gates 806 to 809 are turned on. Therefore, the shift register 801 stores a 12-bit output from the output terminal S of the subtractor 802.

Now, for a stored value r (n) output from the shift register 801 at a certain discrete time n, the input value at the input terminal A of the subtracter 802 is r (n). If the shifter 803 performs division by 1/256 (the case of 1/16 will be described later), the input value of the input terminal B of the subtractor 802 becomes r (n) / 256, and The output value from the terminal S is as follows: r (n) -r (n) / 256 = (1-1 / 256) .r (n) (1) The carry input terminal CIN of the subtractor 802
The value of the input terminal A is always subtracted from the value of the input terminal A, and the subtracter 802 actually subtracts 1 from the value of the input terminal A. This is solved by reducing the value of the shift register 801 even after the value to the input terminal B becomes 0, and thus always subtracting 1 from the value. Therefore, the above equation (1) and the following equation are expressed as “−
Although it differs by 1 ", the value is small and will be ignored and described.

The output value of the subtractor 802 is input to the shift register 801 via the data switch 805 and the AND gates 806 to 809, and appears at n + 1 after one discrete time as the output value r (n + 1) on the output side. From the equation (1), the following relationship holds: r (n + 1) = (1-1 / 256) .r (n) (2)

Here, as described above, the discrete time n_Foursmell
And the 12-bit output from the output terminal S of the subtractor 802 is
If it is stored in the shift register 801,
The value is given by r (n_Four) = X (n_Three) = A₀Assign
Then, (1-1 / 256) · a ₀Becomes Therefore, n_FourLess than
The subtracter 802 and the shifter 803 are provided for each discrete time n of descending.
If the above operation is repeated by
Each output value r (n) of the shift register 801 is calculated by the above equation (2).
R (n) = (1-1 / 256)^n-n3・ A₀ ... It is expressed as (3).

At this time, the gate 813 is connected via the OR gates 816 and 821 in the gate control circuit 814.
The output x (n) of the shift register 801 is input to the shifter 803 at each discrete time n by the control signal PR which becomes the logic "1" each time the pulse Φ1 becomes the logic "1". Equation (3) is satisfied. The operation of the gate 813 and the gate control circuit 814 will be described later in detail.

The output value r (n) obtained by the equation (3) is r (n ₄ ), r (n ₄ ) at each discrete time n ₄ , n ₅ , n ₆ in FIG.
By sequentially inputting to the input terminal B of the comparator 804 as (n ₅ ) and r (n ₆ ), digital waveform signals x (n ₄ ), x (n ₅ ), x
(N ₆ ). If these digital waveform signals are smaller than the respective output values from the shift register 801 as shown in FIG. 10, the output of the comparator 804 outputs logic "0" at each discrete time, and the data changeover switch 80
5 and a subtractor 80 via AND gates 806 to 809
The operation of inputting the output of No. 2 to the shift register 801 is repeated. Accordingly, the output value r of the shift register 801 (n) may vary in accordance with the above equation (3), it has an attenuation characteristic from the maximum peak value a ₀ exponentially as shown in FIG. 10.

After the discrete time n ₄ as described above, based on the output value r (n) of the shift register 801 having an exponentially attenuating characteristic, the digital waveform signal x on the positive amplitude side corresponding to the first string is obtained. The maximum peak value of (n) is detected.

Next, a process of detecting the input timing of the minimum peak value on the negative amplitude side of the digital waveform signal x (n) of the first string in FIG. 10 will be described. Also in this processing, the timing when the pulse Φ1 sequentially becomes logic “1” (see FIG. 9)
The same output value r (n) of the shift register 801 as used for detecting the maximum peak value of the digital waveform signal x (n) on the positive amplitude side corresponding to the first string is used.

[0095] That is, first, in discrete time n ₇ in FIG. 10, although the negative amplitude side of the digital waveform signal x (n ₇₎ is input, this value is decreasing discrete time n ₄ hereinafter exponentially Since the output value of the shift register 801 is smaller than the output value r (n ₇ ), the output of the comparator 804 is logic “0”,
As in the case of discrete times n _{4 to} n ₆ , subtracter 802
Are the values stored in the shift register 801.

Subsequently, at discrete time n ₈ in FIG.
When the digital waveform signal x (n ₈ ) becomes larger than the threshold value signal r (n ₈ ) from the shift register 801, the comparator 8
04 changes to logic “1”, and the digital waveform signal x (n ₈ ) is input to the shift register 801 via the data switch 805 as in the case of the discrete time n ₁ and the next discrete time The stored value of n ₉ is r (n ₉ ).

At the same time, the serial zero-cross signal z (n ₈ ) (ZC
R) becomes logic "0", the gate is turned on at the timing when the timing signal Q5 shown in FIG. 9 becomes logic "1", and the pulse .PHI.1 becomes logic "1" sequentially. As shown in FIG.
The output of 1d becomes logic "1" and the flip-flop F
F1b is set. Thus, at the discrete time n ₈ , the minimum peak value detection signal MIN1 corresponding to the first string, which is the output of the flip-flop FF1b, is at the logical center as shown in FIG. Stand up to "1".

Thereafter, a new digital waveform signal x (n ₉ ) also becomes a stored value r (n ₁₀ ) in the shift register 801 in the discrete time n ₉ in FIG. And FIG.
Becomes the discrete time n ₁₀ 0, the digital waveform signal x
(N ₁₀ ) is the output value r (n ₁₀ ) of the shift register 801 =
Since x (n ₉ ) = | b ₀ |, the output of the comparator 804 changes to logic “0”. This output is input to the AND gate 825 with negative logic, and at the same time, the logic “0” of the serial zero cross signal z (n ₁₀ ) (ZCR) is input to the AND gate 825 with negative logic, so that the timing shown in FIG. The AND gate 825 is turned on at the timing when the signal Q5 becomes logic "1", and the pulse Φ
1 is a logical "1" and AND gate A
The output of ND1c becomes logic "1", and the flip-flop FF1b is reset. Thereby, discrete time n
_In the middle of the timing when the _ten sequential pulses Φ1 become logic “1”, the minimum peak value detection signal MIN1 corresponding to the first string, which is the output of the flip-flop FF1b, falls to logic “0” as shown in FIG.

As described above, the digital waveform signal x of the first string
As (n), the absolute value x of the minimum peak value as shown in FIG.
(N ₉ ) = n ₁₀ one discrete time after the input of | b ₀ |
By minimum peak value detection signal MIN1 of the first string falls to a logic "0", it is possible to detect the input timing of the minimum peak value b ₀ as its 1 discrete time before timing.

At the same time as the above operation, the output from the subtracter 802 becomes the value stored in the shift register 801 as in the case of the discrete time n ₄ . Then, subsequent discrete time n ₁₀ in FIG. 10, the absolute value of the minimum peak value | b ₀ | threshold signal r (n ₁₁₎ to exponentially decay again, r (n _12), ·
Are obtained from the shift register 801. in this case,
r (n) is in accordance with the above equation (3), r (n) = (1-256 ) n-n9 · | b 0 | a ... (4).

In the above operation, the pulse Φ1 sequentially changes the logic “1”.
By repeating at the timing (see FIG. 9)
Digital waveform signal x (n) on the negative amplitude side corresponding to the first string
, The input timing of the minimum peak values b ₀ , b ₁ ,... Can be detected as the timing at which the minimum peak value detection signal MIN1 falls from logic “1” to logic “0”.

Subsequently, the digital waveform signal x of the first string
For (n), from the discrete time n ₁₃ in FIG. 10, so that the signal of the positive amplitude side is input again. First, at discrete time n ₁₃ in FIG. 10, the positive amplitude side of the digital waveform signal x
(N ₁₃ ) is input. Since this value is smaller than the output value r (n ₁₃ ) of the shift register 801 which has decreased exponentially after the discrete time n ₁₀ , the output of the comparator 804 is logic “0”. And the output from the subtractor 802 becomes the value stored in the shift register 801 in the same manner as at the discrete times n _{4 to} n ₆ .

Next, when the digital waveform signal x (n ₁₄ ) becomes larger than the threshold value signal r (n ₁₄ ) from the shift register 801 at the discrete time n ₁₄ in FIG.
The output of the 4 is changed to a logic "1", as in the case of the discrete time n _1, the following discrete time digital waveform signal x (n ₁₄₎ are input to the shift register 801 through the data selector switch 805 stored value of n ₁₅ becomes r (n _15). At the same time, if the flip-flop FF1a in the same discrete time n ₁ is set, the first string of the maximum peak value detection signal MAX1 is, rises to a logic "1" as shown in FIG. 10.

Thereafter, a new digital waveform signal x (n ₁₅ ) also becomes a stored value r (n ₁₆ ) in the shift register 801 at a discrete time n ₁₅ in FIG. And FIG.
When the discrete time n ₁₆ reaches 0, the digital waveform signal x
(N ₁₆ ) is the output value r (n ₁₆ ) of the shift register 801 =
Since x (n ₁₅ ) = a ₁ , the output of the comparator 804 changes to logic “0”, and the output from the subtractor 802 is changed to the shift register 80 in the same manner as at the discrete time n _4.
The stored value is 1. At the same time, discrete time in the same manner as in n ₄ flipflop FF1a is reset, the maximum peak value detection signal MAX1 of the first string falls to a logic "0" as shown in FIG. 10. Thus, as the timing of one discrete time before the fall timing, it is possible to detect the input timing of the maximum peak value a _1.

After the discrete time n ₁₆ in FIG. 10, the threshold signal r exponentially attenuates again from the maximum peak value a _1.
(N ₁₇ ), r (n ₁₈ ),...
Obtained from In this case, r (n) is given by r (n) = (1-256) ⁿ⁻ⁿ¹⁵ · a ₁ (5) in accordance with the above equation (3) and the like.

Subsequently, digital waveform signals x (n ₁₉ ),... On the negative amplitude side are input again from discrete time n ₁₉ .
When the digital waveform signal x (n ₂₀ ) becomes larger than the threshold signal r (n ₂₀ ) from the shift register 801 at the discrete time n ₂₀ in FIG. 10, the output of the comparator 804 changes to logic “1”, As in the case of the discrete time n ₇ , the digital waveform signal x (n ₂₀ ) is input to the shift register 801 via the data switch 805 and becomes the stored value r (n ₂₀ ) of the next discrete time n _21. . At the same time, the discrete case of time n ₇ and is set flip-flop FF1b similarly, the minimum peak value detection signal MIN1 of the first string is raised to a logic "1" as shown in FIG. 10.

Thereafter, a new digital waveform signal x (n ₂₁ ) also becomes a stored value r (n ₂₂ ) in the shift register 801 in the discrete time n ₂₁ in FIG. And FIG.
When the discrete time n ₂₂ becomes 0, the digital waveform signal x
(N ₂₂ ) is the output value r (n ₂₂ ) of the shift register 801 =
x (n ₂₁ ) = | b ₁ |, the output of the comparator 804 changes to logic “0”, and the output from the subtractor 802 is shifted to the shift register in the same manner as at the discrete time n _10. 801 is the stored value. At the same time, discrete time n ₁₀
The flip-flop FF1b is reset in the same manner as in the case of FIG.
As shown by 0, it falls to logic "0". This allows
It can detect input timing of the minimum peak value b _1.

Then, discrete time n in FIG._{twenty two}After
Although not particularly shown, the minimum peak value b ₁Exponentially from
The attenuated threshold signal r (n) is supplied to the shift register 801
Obtained from In this case, r (n) is calculated by the formulas (3) to (5).
According to: r (n) = (1-1 / 256)^n-n21・ | B₁| ... (6)

As described above, with respect to the digital waveform signal x (n) which is inputted with the positive and negative amplitude sides of the first string mixedly as the positive polarity, the timing at which the pulse Φ1 becomes the logic "1" sequentially. By performing the processing in common in FIG.
The maximum peak values a ₀ , a which are the peak values on the positive amplitude side shown in FIG.
_1, the minimum peak value b ₀ is the peak value of the input timing and the negative amplitude side of ..., b _1, each input timing of ..., the maximum peak value detection signal of the first string MAX1 and 1
It can be detected as the minimum string peak value detection signal MIN1.

Although not shown, the digital waveform signal D1 = x (n) corresponding to the first string contains a peak component of an overtone. Even in such a case, since the threshold signal r (n) corresponding to the first string, which is the output 827 of the shift register 801, attenuates slowly and exponentially, the timing of the pseudo peak component as described above is not extracted. Thus, only the peak timing of each cycle can be accurately extracted.

Further, even when the amplitude of the digital waveform signal D1 = x (n) is small, the threshold signal r (n) is determined based on each amplitude value in accordance with the equations (1) to (6). Therefore, the peak timing of each pitch cycle can be accurately extracted.

As described above, the peak detection circuit 701 shown in FIG. 7 or FIG. 8 has the digital waveform signal D1 (x) having only the positive amplitude value corresponding to the first string as shown in FIG.
(N)), only one type of threshold signal r (r (n)) is used, and based on this, the maximum peak value detection signal MA
X1 and a minimum peak value detection signal MIN1 are generated. < Processing for Other Strings > As described above, the digital waveform signal D1 corresponding to the first string is sequentially processed at the timing when the pulse Φ1 becomes logic "1" as shown in FIG.

On the other hand, those corresponding to the other second to sixth strings of the digital waveform signal D1 are time-division-processed at each timing when each of the sequential pulses Φ2 to Φ6 in FIG. This is basically the same as the case of the first string except for the detailed processing timing.

In this case, the operation of detecting the maximum peak value detection signals MAX2 to MAX6 corresponding to the second to sixth strings is as follows.
Assuming that i = 2 to 6, each flip-flop FFia, the reset AND gate ANDia, and the set AND gate ANDib are FF1a, AND1 corresponding to the first string.
a, which is realized by operating exactly the same as AND1b. Similarly, each of the minimum peak value detection signals MIN2 to MI
Also in the detection operation of N6, each flip-flop FFib, reset AND gate ANDic and set AND gate ANDid are connected to the first string corresponding to FF1a, AND1c,
This is realized by operating in exactly the same way as AND1d.

However, in the above operation, the subtractor 802 and the shifter 803 in FIG. 8 perform the subtraction operation as shown in the expressions (1) to (6) slightly differently for each string. This is due to the operation of the gate 813 and the gate control circuit 814, and these operations will be described below.

Now, in the gate control circuit 814 shown in FIG.
The gate 813 is controlled as it is as the control signal PR via 1. Accordingly, each timing PR for the first string and the second string of the control signal PR for turning on the gate 813
(1st string) and PR (2nd string) are the same as the cycle in which the respective pulses Φ1 and Φ2 become logic “1” as shown in FIG.

On the other hand, since the respective sequential pulses Φ3 and Φ4 input to the OR gate 817 are output via the AND gate 819, the lower bit output terminal Q of the counter 815
Only the cycle in which the output from _A is logic "1" is output.
Now, the logic of each output from each of the output terminals Q _B and Q _{A of} the counter 815 is (0,0) (0,1) (1,
0) (1, 1) (0, 0)... Therefore, the control signal PR for turning on the gate 813
Each timing PR for the third and fourth strings (3rd string)
And PR (fourth string) are each successive pulse Φ as shown in FIG.
3, once every two cycles for the cycle in which Φ4 becomes logic “1”.

Further, since the respective sequential pulses Φ5 and Φ6 input to the OR gate 818 are output via the AND gate 820, the upper bit output terminal Q of the counter 815
Each output from B and the lower bit output terminal QA is output only during the period in which both are logic "1". Therefore, the gate 81
The timings PR (fifth string) and PR (sixth string) for the fifth and sixth strings of the control signal PR for turning on the third signal are shown in FIG.
As described above, the cycle in which each of the pulses Φ5 and Φ6 becomes logic “1” is once every four cycles.

With the above operation, for the first string and the second string, the division operation by the shifter 803 and the subtraction operation 802 by the subtractor 802 are performed in each cycle synchronized with each of the pulses Φ1 and Φ2. The threshold calculation is performed according to the expressions (1) to (6). For the third and fourth strings, the above-described threshold calculation is performed once in two cycles synchronized with the respective pulses Φ3 and Φ4. In the cycle in which the gate 813 is turned off, the output of the shifter 803 becomes 0, so that the output 82
7 passes through the subtractor 802, and the threshold value does not change. Further, for the fifth and sixth strings, each successive pulse Φ
5, the threshold value calculation is performed once in four cycles synchronized with Φ6, and in the cycle in which the gate 813 is turned off, the threshold value does not change in the same manner as described above.

Therefore, the decay rate of the threshold signal which is the output value 827 of the shifter 801 shown as r (n) in FIG. 10 is large for the first and second strings, and is large for the third and fourth strings. The value is medium for the strings, and small for the fifth and sixth strings. This is because the string vibration cycle on the treble side, that is, the first string side is short, and the string vibration cycle on the bass side, that is, the sixth string side is long, so that the threshold signal is attenuated in accordance with each string vibration cycle. is there.

As described above, to detect the timing of each peak value from the digital waveform signal D1 for six strings,
It suffices to prepare six types of threshold signals as r (n) and the like in FIG. 10, and the time division processing using those threshold signals may be the six time division processing. In order to store the threshold signal, the shift register 801 shown in FIG. 8 only needs to have six stages, and the hardware scale (the number of stages) of the shift register is halved as compared with the conventional one. be able to. ( Explanation of Time Constant Conversion Control Circuit ) Next, the time constant conversion control circuit 704 of FIG. 7 constituting the pitch extraction digital section 103 of FIG. 1 will be described. Since this part is not directly related to the present invention, only a schematic operation will be described.

Here, a time constant change signal GX for changing the division ratio in the shifter 803 described in FIG. 8 in the peak detection circuit 701 in FIG. 7 is generated, and thereby the threshold signal described in FIG. The decay rate (time constant) such as r (n) is changed. That is, by changing the attenuation rate of the threshold signal r (n) or the like according to the situation, it works so that the timing of the maximum / minimum peak value in the peak detection circuit 701 in FIG. 7 can be accurately extracted. The change processing of the attenuation rate in the time constant conversion control circuit 704 is performed by the MCP shown in FIG.
In synchronization with the pitch extraction operation based on software processing performed by the MCP 101, the MCP 101
04 is controlled.

When the time constant change signal GX is sent from the time constant conversion control circuit 704 to the shifter 803 in FIG. 8 in the peak detection circuit 701 in FIG.
The control is changed from the division of / 256 to the division of 1/16.
By inputting the changed division result to the subtraction input terminal B of the subtractor 802, the attenuation rate of the threshold signal output via the subtractor 802 increases. That is,
By the time constant change signal GX, the threshold signal r (n) in FIG. 10 operates so as to rapidly attenuate.

The above operation largely depends on the pitch extraction operation of the MCP 101. For example, since the vibration period of each string varies widely depending on the position where the player presses the string on the fret, the digital waveform signal D1
When the waveform of the time-division signal corresponding to each string rises,
In order to quickly detect the vibration of the waveform, the threshold signal rapidly attenuated in a relatively short time lapse corresponding to each string, and immediately after that, in order to not pick up harmonic components etc. of each pitch cycle, each The time until the time constant is changed is set so as to rapidly decay in a relatively long time cycle. And
After the pitch period starts to be effectively extracted, the time until the threshold signal is rapidly attenuated is determined based on the extracted pitch period at each point in time. As a result, it is possible to follow a change in the pitch cycle of each string of the digital waveform signal D1 due to the performance operation, and it is possible to accurately extract the timing of the maximum and minimum peak values from the signal. ( Description of Zero-Cross Time Capture Circuit ) Next, the zero-cross time capture circuit 702 of FIG. 7 that constitutes the pitch extraction digital section 103 of FIG. 1 will be described. Since this part is not directly related to the present invention, only a schematic operation will be described.

In the present embodiment, as described with reference to FIG. 2 in the section "Schematic operation of this embodiment", FIG.
Pitch extracting the digital waveform signal D1 output from the analog portion 102, each string peak value for each a ₀ ~a ₃ or b ₀ ~b ₃ like extracts (FIG. 2), the zero-crossing time immediately after each peak value at the same time Extract t ₀ -t ₇ etc. (FIG. 2)
By sending these data to the MCP 101 in FIG. 1, the MCP 101 performs a pitch extraction operation by software processing, and extracts the pitch period of each string by T _{0 to} T ₅ (FIG. 2).

Therefore, the zero-cross time acquisition circuit 7 shown in FIG.
02 is a zero-cross signal Z1 to Z6 corresponding to each string output from the pitch extraction analog unit 102 in FIG. 1 or FIG. 3, and a maximum peak value detection signal MAX1 corresponding to each string output from the peak detection circuit 701 in FIG. ＭＡMAX6, based on the minimum peak value detection signals MIN1 to MIN6, fetches the zero crossing time immediately after the maximum peak value or the minimum peak value for each string and outputs it to the MCP 101 in FIG.

More specifically, the zero-cross time acquisition circuit 70
2 is a time base counter 7 common to each string as shown in FIG.
021. The same circuit 702 detects, for each string, the timing at which the maximum / minimum peak value detection signals MAX1 to MAX6 and MIN1 to MIN6 output from the peak detection circuit 701 fall from the high level to the low level (see FIG. 10). Then, at the zero-crossing time, which is the time when the zero-crossing signals Z1 to Z6 change immediately after the timing,
The output of the time base counter 7021 is latched.

When the latch operation is performed, the zero-crossing time acquisition circuit 702 subsequently outputs an interrupt signal INT to the MCP 101 in FIG. Thereby, MCP10
In accordance with a control signal input from 1 through a control line (not shown), the string number at which the zero cross has occurred and the zero cross time corresponding to the latched string are sequentially output to the MCP 101 via the bus BUS. Where MCP101
It is possible to determine whether the zero cross is immediately after the minimum peak value or the zero cross immediately after the maximum peak value by, for example, adding a positive / negative flag to the most significant bit of the zero cross time. ( Description of the peak value capturing circuit ) Subsequently, the peak value capturing circuit 703 of FIG. 7 constituting the pitch extraction digital section 103 of FIG.
Will be described. Since this part is not directly related to the present invention, only a schematic operation will be described.

In the present embodiment, the above-mentioned “zero-crossing time
Of digital waveform signal
For signal D1, peak value a for each string₀~ A_ThreeOr b₀
~ B _Three(FIG. 2) must be extracted. Also, in FIG.
During the pitch extraction process, the MCP 101
For one of the strings, the digital waveform signal D1
In some cases, an instantaneous value is required.

Therefore, the peak value capturing circuit 703 in FIG.
Is output from the peak detection circuit 701 in FIG. 7 or FIG.
MAX1 to MAX6 corresponding to each string
And the minimum peak value detection signals MIN1 to MIN6.
1 or 3 from the pitch extraction analog section 102.
The maximum peak value of each string of the digital waveform signal D1 (FIG. 2A)
₀~ A_ThreeEtc.) or minimum peak value (FIG. 2b)₀~ B_Threeetc),
And the instantaneous value, and outputs it to the MCP 101 in FIG.
You.

Specifically, the peak value capturing circuit 703 demultiplexes the digital waveform signal D1 output from the pitch extraction analog section 102 in FIG. 1 or 3 in a time division manner into a peak value for each string. (Decompose) processing. Then, at a timing one discrete time before the maximum or minimum peak value detection signals MAX1 to MAX6 and MIN1 to MIN6 from the peak detection circuit 701 of FIG. 7 or 8 fall from the high level to the low level (see FIG. 10), The peak value of the demultiplexed digital waveform signal D1 is held.
To this end, the peak value capturing circuit 703 includes a digital waveform signal D (the previous one discrete time before) internally, although not particularly shown.
It has a buffer that holds the peak value of 1.

Then, the peak value capturing circuit 703
101 (FIG. 1) sequentially outputs the maximum peak value or the minimum peak value of the string accessed via a control line (not shown) to the MCP 101 via the bus BUS.

Further, the peak value capturing circuit 703 includes the MCP1
When 01 prompts the output of an instantaneous value for a certain string, the instantaneous value of the digital waveform signal D1 held in the same circuit 703 is sequentially output to the MCP 101 via the bus BUS at that timing. << Schematic Operation of Central Controller (MCP) >> Finally, the schematic operation of the central controller (MCP) 101 will be described. Here, the pitch extraction operation by software processing is executed. However, since the present invention relates to the above-described peak detection circuit 701 in FIG. 7, only the operation of the MCP 101 will be described briefly. For details of the pitch extraction processing, etc., refer to Japanese Patent Application No. 63-76492 filed by the present applicant.
"Electronic musical instruments" and Japanese Patent Application No. 63-109625 "Electronic stringed musical instruments" are disclosed.

By the operation described above, the pitch shown in FIG.
From the extraction digital unit 103, the maximum or minimum peak value,
Locross time, positive / negative flag indicating positive / negative of peak value, etc.
Is input to the MCP 101 in FIG. This allows MCP1
01 is the same as that of FIG.
As described above, the first data set (b₀, T₀)
The corresponding string is picky at the point when (Fig. 2) is input.
It is determined that the pitching has been performed, and the operation for detecting the pitch period is started.
Thereafter, the interrupt signal I is output from the pitch extraction digital section 103.
The data that is input every time an interrupt is applied
Pair (a₀, T₁), (B)₁, T_Two), (A₁, T_Three),
.. (FIG. 2) and the like, the MCP 101
Switch extraction processing and its correction processing, etc.
Switch period T ₀~ T_FiveEtc. are extracted in real time. this
MCP 101 is based on the obtained pitch period
Generated pitch information, and the tone generation circuit 104 generates the pitch information.
Produce musical sounds. Thus, in the present embodiment, in FIG.
Pitch extraction analog section 102 and pitch extraction digital section
103 hardware part and software by MCP101
By operating in cooperation with the
It allows pitch extraction. ｛Other embodimentsで は In the embodiment described above, the threshold signal shown in FIG.
The signal r and the like have the maximum peak value (a₀Etc.)
And the minimum peak value (b₀Etc.)
The decay rate is the same. On the other hand, for example,
Digital waveform signal D1 differs between the positive amplitude side and the negative amplitude side.
Characteristics (for example, different duty ratios or maximum peak
The absolute value of the amplitude of the minimum peak value that is adjacent to the peak value is different.)
If, for example, attenuate from the maximum peak value
The attenuation rate differs between
As shown, the time constant conversion control circuit 704 in FIG.
The detection circuit 701 may be controlled. like this
The probability of false detection of false peaks
Smaller pitch for more accurate pitch extraction
Becomes

[0135]

According to the present invention, the timing of the maximum peak value or the minimum peak value for extracting pitch information is determined by
When detecting based on a threshold signal that gradually decreases from a past peak value, only one type of threshold signal is generated and used corresponding to one input waveform signal, so that time division is performed on a plurality of input waveform signals. When performing the processing, the same number of threshold signals may be prepared, and the time division processing using those threshold signals may be the same number of time division timing processing. Then, in order to store these threshold signals, the same number of storage control means may be prepared. Therefore, both the speed of the time-division processing and the scale of hardware such as the shift register and the RAM can be reduced to １ ／ as compared with the conventional example.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of an embodiment of the present invention.

FIG. 2 is a schematic operation explanatory diagram of the present embodiment.

FIG. 3 is a configuration diagram of a pitch extraction analog unit.

FIG. 4 is an operation timing chart of a pitch extraction analog unit.

FIG. 5 is a relationship diagram of Φ1, W1, V _IN , V _OUT and ZCR.

FIGS. 6A and 6B are diagrams showing the relationship between the string envelope and the note-on time.

FIG. 7 is an overall block diagram of a pitch extraction digital unit.

FIG. 8 is a specific configuration diagram of a peak detection circuit.

FIG. 9 is a specific operation timing chart of the peak detection circuit.

FIG. 10 is a diagram illustrating a specific operation of the peak detection circuit.

FIG. 11 is a timing chart of the subtraction operation for each string of the peak detection circuit.

FIG. 12 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 103 Pitch extraction digital section 701 Peak detection circuit 801 Shift register 802 Subtractor 804 Comparator 805 Data changeover switch D1 Digital waveform signal r Threshold signal

Claims (2)

(57) [Claims] Polarity detection means for detecting the polarity of claim 1] input waveform signal on the basis of the polarity detection result of the polar detecting means, the negative portion polarity of the input waveform signal is inverted to the positive polarity, Polarity conversion means for converting the input waveform signal so as to include only a signal component of a positive polarity, and storage control for storing the positive waveform signal from the polarity conversion means while decreasing a past peak value of the signal. Means, after detecting the previous peak value of the positive polarity waveform signal, using the output signal of the storage control means as a threshold signal, detecting a point in time when the positive polarity waveform signal next exceeds the threshold signal, If the polarity detecting means detects a positive polarity from the input waveform signal, a maximum peak value detection signal is output immediately after the detection time, and if a negative polarity is detected, a minimum peak value detection signal is output immediately after the detection time. Out Input waveform control apparatus characterized by comprising: a peak detecting means, a to. Wherein the input waveform signal of multiple digital multiplexing, from each of the digital multiplexed input waveform signal,
2. The input waveform control device according to claim 1, wherein each input timing of a maximum peak value and a minimum peak value corresponding to each of the input waveform signals is detected by time division processing .