JP2013191665A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device composed of group III nitride excellent in crystallinity.SOLUTION: When the distance between the centers of adjacent salients 101 of a substrate 100 is D [μm], the width of each salient 101 is d [μm], the height of a first semiconductor layer 111 is t1 [μm], and the height of a second semiconductor layer 112 is t2 [μm], the following formula is met: 0.8×(D-d)<(t1+t2)<2.0 [μm].

Description

  The present invention relates to a group III nitride semiconductor device and a method for manufacturing a group III nitride semiconductor device.

  Group III nitride semiconductors typified by gallium nitride have a wide band gap and can emit blue light, and are therefore widely used in light-emitting elements such as LEDs (light-emitting diodes).

  A general nitride semiconductor light emitting device is formed on a substrate such as sapphire by crystal growth using MOCVD or MBE.

  In order to improve the light emission characteristics of a light emitting device using such a group III nitride semiconductor, as a method for reducing light confinement inside the light emitting device and improving light extraction efficiency, for example, Japanese Patent Laid-Open No. 2002-280611 A gazette (patent document 1) is mentioned.

  Patent Document 1 proposes a method of forming irregularities on the surface of a sapphire substrate and growing a group III nitride semiconductor layer thereon. In this method, the interface between the sapphire substrate and the group III nitride semiconductor layer becomes uneven, and light is diffusely reflected at the interface due to the difference in refractive index between the sapphire substrate and the group III nitride semiconductor layer, so Light confinement can be reduced, and light extraction efficiency can be improved.

  Further, JP 2009-123717 A (Patent Document 2) discloses that a plurality of convex portions having a surface non-parallel to the C-plane of the substrate are formed on the substrate so that the C-plane is formed on the substrate. A substrate processing step for forming an upper surface composed of a flat surface and a convex portion is disclosed, and a method for growing a group III nitride semiconductor layer on the processed substrate is also described.

JP 2002-280611 A JP 2009-123717 A

  By the way, generally, when unevenness is formed on the surface of a sapphire substrate, there is a problem that it is difficult to grow a group III nitride semiconductor layer having excellent crystallinity on the surface. For example, pits and white turbidity are likely to occur on the surface of the grown semiconductor layer, cracks are likely to occur, and lattice distortion increases and crystallinity deteriorates.

  Therefore, an object of the present invention is to provide a semiconductor element made of a group III nitride having excellent crystallinity. Moreover, it is providing the method of manufacturing this semiconductor element stably.

In order to solve the above problems, the semiconductor element of the present invention is
A substrate having a plurality of convex portions formed on the surface;
A first semiconductor layer made of a group III nitride semiconductor formed on the substrate;
A second semiconductor layer made of a group III nitride semiconductor formed on the first semiconductor layer,
The top of the second semiconductor layer is formed with a facet crystal plane,
The distance between the centers of the adjacent convex portions is D [μm],
The width of the convex portion is d [μm],
The height of the first semiconductor layer is t1 [μm],
When the height of the second semiconductor layer is t2 [μm],
0.8 × (D−d) <(t1 + t2) <2.0 [μm]
It is characterized by satisfying.

  According to the semiconductor element of the present invention, since 0.8 × (Dd) <(t1 + t2) <2.0 [μm] is satisfied, a semiconductor element having excellent crystallinity can be stably manufactured. And by using this semiconductor element for a light emitting element, a light emitting element excellent in light extraction efficiency and internal quantum efficiency can be manufactured.

  On the other hand, when (t1 + t2) is smaller than 0.8 × (D−d), a flat portion appears at the top of the second semiconductor layer, and the crystallinity is deteriorated. On the other hand, if (t1 + t2) is larger than 2.0 [μm], the film thickness of the third semiconductor layer formed on the second semiconductor layer and obtaining a film with good flatness becomes large. Cracks are likely to occur.

In the semiconductor device of one embodiment,
The height t1 of the first semiconductor layer is
0.1 [μm] <t1 <0.5 [μm]
Meet.

  According to the semiconductor element of this embodiment, since 0.1 [μm] <t1 <0.5 [μm] is satisfied, a semiconductor element with further excellent crystallinity can be formed.

  On the other hand, when t1 is smaller than 0.1 μm, the first semiconductor layer does not become flat, which causes crystallinity deterioration and pit generation. On the other hand, when t1 is larger than 0.5 μm, the crystal is likely to grow around the apex of the convex portion of the substrate, and the crystal grown from the flat portion of the substrate may be associated with the crystal grown from the convex portion of the substrate. In this association, crystal distortion is increased and crystallinity is deteriorated.

In one embodiment of the method for manufacturing a semiconductor device,
A first step of forming a first semiconductor layer made of a group III nitride semiconductor on a substrate having a plurality of convex portions formed on the surface;
A second step of forming a second semiconductor layer made of a group III nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer made of a group III nitride semiconductor on the second semiconductor layer,
The temperature for growing the first semiconductor layer is T1,
The temperature for growing the second semiconductor layer is T2,
When the temperature for growing the third semiconductor layer is T3,
T3>T1> T2
Meet.

  According to the method of manufacturing a semiconductor device of this embodiment, T3> T1> T2 is satisfied, so that T3 is larger than T1 and T2, and thereby the lateral growth of the third semiconductor layer proceeds, The facet surface of the second semiconductor layer can be more efficiently filled with the third semiconductor layer.

  In addition, T1 becomes larger than T2, which makes it difficult for the first semiconductor layer to grow on the convex portion of the substrate, thereby obtaining a flat semiconductor layer and stabilizing the facet surface of the second semiconductor layer. Making it easier to grow.

  Therefore, a high quality semiconductor device can be manufactured stably.

In one embodiment of the method for manufacturing a semiconductor device,
A first step of forming a first semiconductor layer made of a group III nitride semiconductor on a substrate having a plurality of convex portions formed on the surface;
A second step of forming a second semiconductor layer made of a group III nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer made of a group III nitride semiconductor on the second semiconductor layer,
The pressure for growing the first semiconductor layer is P1,
The pressure for growing the second semiconductor layer is P2,
When the pressure for growing the third semiconductor layer is P3,
P2 ≧ P1> P3
Meet.

  According to the method for manufacturing a semiconductor element of this embodiment, P2 ≧ P1> P3 is satisfied, so that P3 is smaller than P1 and P2, and thereby the lateral growth of the third semiconductor layer proceeds, The facet surface of the second semiconductor layer can be more efficiently filled with the third semiconductor layer.

  In addition, P2 is equal to or larger than P1, thereby making it difficult for the first semiconductor layer to grow on the convex portion of the substrate and obtaining a semiconductor layer with good flatness, and to make the facet of the second semiconductor layer. It becomes easy to grow the surface stably.

  Therefore, a high quality semiconductor device can be manufactured stably.

In one embodiment of the method for manufacturing a semiconductor device,
The distance between the centers of the adjacent convex portions is D [μm],
The width of the convex portion is d [μm],
The height of the first semiconductor layer is t1 [μm],
When the height of the second semiconductor layer is t2 [μm],
0.8 × (D−d) <(t1 + t2) <2.0 [μm]
Meet.

  According to the method for manufacturing a semiconductor device of this embodiment, since 0.8 × (D−d) <(t1 + t2) <2.0 [μm] is satisfied, a semiconductor device having excellent crystallinity is stably manufactured. be able to. And by using this semiconductor element for a light emitting element, a light emitting element excellent in light extraction efficiency and internal quantum efficiency can be manufactured.

  On the other hand, when (t1 + t2) is smaller than 0.8 × (D−d), a flat portion appears at the top of the second semiconductor layer, and the crystallinity is deteriorated. On the other hand, if (t1 + t2) is larger than 2.0 [μm], the film thickness of the third semiconductor layer formed on the second semiconductor layer and obtaining a film with good flatness becomes large. Cracks are likely to occur.

  According to the semiconductor element of the present invention, since 0.8 × (Dd) <(t1 + t2) <2.0 [μm] is satisfied, a semiconductor element having excellent crystallinity can be stably manufactured.

  According to the method for manufacturing a semiconductor element of the present invention, T3> T1> T2 or P2 ≧ P1> P3 is satisfied, so that a high-quality semiconductor element can be manufactured stably.

It is sectional drawing of the semiconductor element of one Embodiment of this invention. It is a top view which shows the state of the board | substrate of the said semiconductor element. It is sectional drawing which shows the state of the 1st semiconductor layer of the said semiconductor element. It is sectional drawing which shows the state of the 2nd semiconductor layer of the said semiconductor element. It is a top view which shows the state of the 2nd semiconductor layer of the said semiconductor element. It is sectional drawing which shows the manufacturing process of the said semiconductor element. It is sectional drawing which shows the manufacturing process of the said semiconductor element. It is sectional drawing which shows the manufacturing process of the said semiconductor element. It is sectional drawing which shows the manufacturing process of the said semiconductor element. 4 is a SEM photograph showing the top surface of the semiconductor element according to Example 1. 3 is a SEM photograph showing a cross section of the semiconductor element according to Example 1; 4 is a SEM photograph showing the top surface of a semiconductor element according to Comparative Example 1. 6 is a SEM photograph showing the upper surface of a semiconductor element according to Comparative Example 2.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  In this specification, the expression “B on A” refers to the case where B is formed so that the bottom surface of B is in contact with the top surface of A, and that one or more layers are formed on the top surface of A. In this case, both cases where B is formed are included. Further, the above expression also includes the case where the upper surface of A and the bottom surface of B are in partial contact, and there are one or more layers between A and B in other portions.

  FIG. 1 is a simplified cross-sectional view showing a semiconductor element according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor element includes a substrate 100 having a plurality of convex portions 101 formed on the surface, and a first semiconductor layer 111 made of a group III nitride formed on a flat portion 102 of the substrate 100. A second semiconductor layer 112 made of a group III nitride formed on the first semiconductor layer 111, and a third semiconductor layer 113 made of a group III nitride formed so as to fill the facets of the second semiconductor layer 112; have.

  The substrate 100 is made of a material different from that of the group III nitride semiconductor. For example, sapphire, silicon carbide, silicon, zinc oxide and the like can be mentioned, and sapphire is particularly preferable.

  FIG. 2 is a plan view for explaining the substrate 100 on which the plurality of convex portions 101 are formed, and shows an example of the surface of the substrate 100.

  As shown in FIGS. 1 and 2, a region where the convex portion 101 of the substrate 100 is not formed becomes a flat portion 102. As a method of forming the convex portion 101, for example, patterning is performed according to the convex portion shape using a normal photolithography technique, and etching is performed using a dry etching method or the like.

  The plurality of convex portions 101 formed on the substrate 100 have a predetermined width d and height, and are formed to have a uniform size and shape. In the present embodiment, examples of the shape of the convex portion include a hemispherical shape. However, in the present invention, the shape of the convex portion 101 is not particularly limited.

  Here, the width d of the convex portion 101 is the maximum diameter of the convex portion 101, and the width d is preferably 0.05 μm to 5 μm. When the width d is less than 0.05 μm, when a group III semiconductor light emitting device is manufactured using the substrate 100, the effect of irregularly reflecting the light emission may not be obtained sufficiently. In addition, when the width d is larger than 5 μm, it is very difficult to obtain the flat first semiconductor layer 111. Therefore, by limiting the width d to the above range, it is possible to sufficiently obtain the effect of irregularly reflecting light emission and to obtain the flat first semiconductor layer 111.

  Further, the plurality of convex portions 101 are installed with a predetermined distance on the surface of the substrate 100, and the interval between the centers of the adjacent convex portions 101, 101 is D. The arrangement of the convex portions 101 includes a lattice shape, a staggered shape, and the like, but is not limited thereto.

  In addition, the shape of the convex portion 101 may be an ellipse, an oval, a rectangle, or the like in addition to a circle in plan view. The direction of the width d of the convex portion 101 and the direction of the interval D between the adjacent convex portions 101 and 101 are the same direction.

  FIG. 3 is a cross-sectional view illustrating the first semiconductor layer 111 formed on the substrate 100 on which the plurality of convex portions 101 are formed.

As shown in FIGS. 1 and 3, the first semiconductor layer 111 is made of a group III nitride semiconductor and is formed on the flat portion 102 of the substrate 100. _{Examples of the} group III nitride semiconductor include Al _x Ga _y In _z N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1). In particular, GaN has crystallinity and productivity. From the viewpoint of

  Here, the height t1 of the first semiconductor layer 111 is preferably in the range of 0.1 μm <t1 <0.5 μm. When t1 is smaller than 0.1 μm, the first semiconductor layer 111 is not flat, which causes deterioration of crystallinity and generation of pits. On the other hand, when t1 is larger than 0.5 μm, the crystal easily grows around the apex of the convex portion 101, and the crystal grown from the flat portion 102 may be associated with the crystal grown from the convex portion 101. During this association, crystal distortion is increased and crystallinity is deteriorated.

  Therefore, since the state of the first semiconductor layer 111 greatly affects the crystallinity of the layer formed thereon, the crystallinity is excellent particularly by limiting the height t1 of the first semiconductor layer 111 to the above range. A semiconductor element can be formed.

  FIG. 4 is a cross-sectional view illustrating the second semiconductor layer 112 formed on the first semiconductor layer 111, and FIG. 5 is a top view illustrating the surface of the second semiconductor layer 112.

As shown in FIGS. 4 and 5, the second semiconductor layer 112 is made of a group III nitride semiconductor and is formed on the first semiconductor layer 111. _{Examples of the} group III nitride semiconductor include Al _x Ga _y In _z N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1). In particular, GaN has crystallinity and productivity. From the viewpoint of

  Here, the top of the second semiconductor layer 112 is formed only on a crystal face forming a facet. That is, the top of the second semiconductor layer 112 has a mountain shape in which the facets forming crystal planes intersect at the top, and this top does not have a crystal plane other than the facets forming crystal face. . By forming the second semiconductor layer 112 as described above, the crystallinity of the third semiconductor layer 113 formed so as to fill the second semiconductor layer 112 is improved.

  Note that at least part of the top of the second semiconductor layer 112 may be formed with a facet crystal plane, which is preferable for the crystallinity of the third semiconductor layer 113. The crystallinity of the third semiconductor layer 113 can be further improved by forming all the top portions of the second semiconductor layer layer 112 with facet crystal planes.

  Furthermore, the crystal plane forming the second semiconductor layer 112 is preferably a {1-101} plane of a hexagonal crystal plane. The {1-101} plane represents all crystal planes equivalent to the (1-101) plane. By setting the crystal plane of the second semiconductor layer 112 to the {1-101} plane, the crystallinity of the third semiconductor layer 113 formed so as to fill the second semiconductor layer 112 is dramatically improved.

  Furthermore, when the height of the second semiconductor layer 112 is t2, 0.8 × (D−d) <(t1 + t2) <2.0 [μm] is satisfied. If (t1 + t2) is smaller than 0.8 × (D−d), a planar portion appears at the top of the second semiconductor layer 112. This is because if the facet plane is a hexagonal {1-101} plane, the angle formed by the facet plane is about 60 degrees. When there is a planar portion at the top of the second semiconductor layer 112, dislocations in the crystal extend through the planar portion to the upper portion of the crystal as crystal growth proceeds, so that the crystallinity deteriorates. On the other hand, if (t1 + t2) is larger than 2.0 μm, the film thickness of the third semiconductor layer 113 for obtaining a film with good flatness is increased, so that cracks are likely to occur.

  Therefore, by limiting the sum of the height t1 of the first semiconductor layer 111 and the height t2 of the second semiconductor layer 112 to the above range, a semiconductor element having excellent crystallinity can be stably manufactured.

  Next, a method for manufacturing a semiconductor element will be described with reference to FIGS. 6A to 6D.

  As shown in FIG. 6A, a substrate 100 having a plurality of convex portions 101 on the surface is prepared, and a group III nitride semiconductor crystal is epitaxially grown on the substrate 100. This crystal growth method is preferably performed by organometallic compound vapor phase growth (MOVPE) using an organic metal as a group III material, but vapor phase growth (HVPE) or molecular by a chloride transport method using a chloride as a group III material. Line epitaxy growth (MBE) may be used.

  First, surface treatment necessary for growing a group III nitride on a normal flat substrate, such as cleaning the surface of the substrate 100 or growing a buffer layer, is performed. As the buffer layer, a known layer may be used, and examples thereof include group III nitride semiconductors such as GaN and AlN.

  After the buffer layer is fabricated, the first semiconductor layer 111 is grown as shown in FIG. 6B. As a growth condition of the first semiconductor layer 111, it is preferable to set a condition that makes it difficult for the convex portion 101 to grow. For example, the growth temperature T1 is set to a temperature lower by 50 to 100 ° C. than the normal high-temperature GaN growth temperature. Further, by setting the growth pressure P1 to 200 Torr or more, a semiconductor layer with good flatness can be obtained.

  Here, the growth conditions are adjusted so that the height t1 of the first semiconductor layer 111 is 0.1 μm <t1 <0.5 μm, but it is preferable to adjust the growth time or the group III material flow rate.

  Then, as shown in FIG. 6C, the second semiconductor layer 112 is grown on the first semiconductor layer 111. The growth conditions are set so that the top of the second semiconductor layer 112 is formed only by the crystal face forming the facet. For example, the growth temperature T2 is a temperature lower by 70 to 150 ° C. than the normal high-temperature GaN growth temperature. Set to. In addition, by setting the growth pressure P2 to 400 Torr or more, it becomes easy to stably grow the facet surface.

  Here, the sum of the height t1 of the first semiconductor layer 111 and the height t2 of the second semiconductor layer 112 is 0.8 × (D−d) <(t1 + t2) <2.0 [μm]. T1 and t2 are adjusted according to the growth conditions, but it is preferable to adjust the growth time or the group III raw material flow rate. Therefore, as described above, by limiting the sum of t1 and t2 to the above range, a semiconductor element having excellent crystallinity can be stably manufactured.

  After the second semiconductor layer 112 is obtained, as shown in FIG. 6D, the growth conditions are changed, and the third semiconductor layer 113 is formed so as to fill the second semiconductor layer 112. At this time, by increasing the growth temperature T3 or decreasing the growth pressure P3, the lateral growth proceeds and the facet surface of the second semiconductor layer 112 can be filled more efficiently. Preferably, the growth temperature T3 is set to a temperature comparable to that of normal GaN growth, and the growth pressure P3 is set to 200 Torr or less.

  In this way, the semiconductor element of the present invention is manufactured.

  Regarding the growth temperatures T1, T2 and T3, it is preferable to satisfy T3> T1> T2. T3 becomes larger than T1 and T2, whereby the lateral growth of the third semiconductor layer 113 proceeds, and the facet surface of the second semiconductor layer 112 is more efficiently filled with the third semiconductor layer 113. be able to. T1 becomes larger than T2, which makes it difficult for the first semiconductor layer 112 to grow on the convex portion 101 of the substrate 100, thereby obtaining a semiconductor layer with good flatness. Further, the facet surface of the second semiconductor layer 112 is increased. It becomes easy to grow stably. Therefore, a high quality semiconductor device can be manufactured stably.

  About the said growth pressure P1, P2, P3, it is preferable to satisfy | fill P2> = P1> P3. P3 becomes smaller than P1 and P2, whereby the lateral growth of the third semiconductor layer 113 proceeds, and the facet surface of the second semiconductor layer 112 is more efficiently filled with the third semiconductor layer 113. be able to. P2 is the same as or larger than P1, whereby the first semiconductor layer 111 is less likely to grow on the convex portion 101 of the substrate 100, and a semiconductor layer with good flatness can be obtained, and the second semiconductor layer 112 is obtained. It becomes easy to grow the facet surface stably. Therefore, a high quality semiconductor device can be manufactured stably.

  Next, (Example 1) as a sample of the present invention and (Comparative Example 1) (Comparative Example 2) (Comparative Example 3) as samples for comparison with the present invention will be described.

Example 1
First, referring to FIG. 1, a sapphire substrate 101 having a plurality of convex portions 101 arranged in a staggered pattern on the surface is prepared. The shape of the convex portion 101 is hemispherical, the width d of the convex portion 101 is 1 μm, and the interval D between adjacent convex portions 101 is 2 μm. Then, GaN was grown by the following MOVPE method.

  The sapphire substrate 100 was set in a reaction chamber of a shower type MOVPE apparatus, and the substrate was annealed in a hydrogen atmosphere at a chamber pressure of 100 Torr and a heater temperature of 1240 ° C.

  Then, the heater temperature is lowered to 715 ° C., the pressure in the chamber is set to 400 Torr, TMG and NH 3 are supplied, a low temperature GaN buffer layer is grown, the heater temperature is raised to 1240 ° C., and TMG and NH 3 are supplied. Then, the first semiconductor layer 111 was grown by 0.3 μm. When the surface of the first semiconductor layer 111 was observed with a scanning electron microscope (SEM), the surface was flat without pits, and no growth from the periphery of the apex of the convex portion 101 was observed.

  In short, by setting the height t1 of the first semiconductor layer 111 to 0.3 μm, 0.1 μm <t1 <0.5 μm is satisfied.

  Thereafter, the heater temperature was lowered to 1170 ° C., and the second semiconductor layer 112 was grown by 1.5 μm. When the surface and cross-sectional shape of the crystal of the second semiconductor layer 112 are observed with an SEM, it is composed of a {1-101} plane of GaN and has a triangular cross-sectional shape as shown in FIGS. 7A and 7B. Was confirmed.

  In short, by setting the height t2 of the second semiconductor layer 112 to 1.5 μm, 0.8 × (D−d) = 0.8 × (2-1) = 0.8 μm, and t1 + t2 = 0.3 + 1 0.5 = 1.8 μm, which satisfies 0.8 μm <(t1 + t2) <2.0 μm.

  Then, the heater temperature was raised to 1310 ° C., the pressure in the chamber was set to 200 Torr, TMG and NH 3 were supplied, and the GaN layer (third semiconductor layer 113) was grown by 4 μm. The crystal surface had no pits and was flat, and the X-ray rocking curve had a full width at half maximum (XRC-FWHM) of 130 arcsec on the (0004) plane and 160 arcsec on the (1-102) plane. .

  (Comparative Example 1) (Comparative Example 2) In (Comparative Example 3), except that the height t1 of the first semiconductor layer and the height t2 of the second semiconductor layer were changed depending on the growth time, the above (Example 1) and A semiconductor element was produced in the same manner.

(Comparative Example 1)
The XRC-FWHM of the semiconductor element in which the height t1 of the first semiconductor layer is 0.05 μm and the height t2 of the second semiconductor layer is 1.5 μm is that the (0004) plane is 150 arcsec and the (1-102) plane is It was 180 arcsec.

  As shown in FIG. 8, when the surface of the first semiconductor layer 111A was observed with an SEM, it was confirmed that the surface had many dents and was not flat. In short, since the height t1 of the first semiconductor layer 111A is smaller than 0.1 μm, the first semiconductor layer 111A did not become flat. Reference numeral 101A in the figure indicates a convex portion of the substrate.

(Comparative Example 2)
The XRC-FWHM of the semiconductor element in which the height t1 of the first semiconductor layer is 0.6 μm and the height t2 of the second semiconductor layer is 1.2 μm is (arc) 160 arcsec, (1-102) plane It was 180 arcsec.

  As shown in FIG. 9, when the surface of the first semiconductor layer (GaN) 111B was observed with an SEM, it was confirmed that GaN was also grown near the apex of the convex portion 101B of the substrate. In short, since the height t1 of the first semiconductor layer 111A is larger than 0.5 μm, the crystal easily grows around the apex of the convex portion 101B of the substrate.

(Comparative Example 3)
The semiconductor element in which the height t1 of the first semiconductor layer was 0.3 μm and the height t2 of the second semiconductor layer was 1.8 μm had cracks on the surface. In short, since (t1 + t2) is 2.1 μm and is larger than 2.0 μm, cracks are likely to occur.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  For example, in the method for manufacturing a semiconductor element, at least one of T3> T1> T2 or P2 ≧ P1> P3 may be satisfied.

100 substrate 101 convex portion 102 flat portion 111 first semiconductor layer 112 second semiconductor layer 113 third semiconductor layer

Claims (5)

A substrate having a plurality of convex portions formed on the surface;
A first semiconductor layer made of a group III nitride semiconductor formed on the substrate;
A second semiconductor layer made of a group III nitride semiconductor formed on the first semiconductor layer,
The top of the second semiconductor layer is formed with a facet crystal plane,
The distance between the centers of the adjacent convex portions is D [μm],
The width of the convex portion is d [μm],
The height of the first semiconductor layer is t1 [μm],
When the height of the second semiconductor layer is t2 [μm],
0.8 × (D−d) <(t1 + t2) <2.0 [μm]
The semiconductor element characterized by satisfy | filling. The semiconductor device according to claim 1,
The height t1 of the first semiconductor layer is
0.1 [μm] <t1 <0.5 [μm]
The semiconductor element characterized by satisfy | filling. A first step of forming a first semiconductor layer made of a group III nitride semiconductor on a substrate having a plurality of convex portions formed on the surface;
A second step of forming a second semiconductor layer made of a group III nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer made of a group III nitride semiconductor on the second semiconductor layer,
The temperature for growing the first semiconductor layer is T1,
The temperature for growing the second semiconductor layer is T2,
When the temperature for growing the third semiconductor layer is T3,
T3>T1> T2
Semiconductor device manufacturing method characterized by satisfying A first step of forming a first semiconductor layer made of a group III nitride semiconductor on a substrate having a plurality of convex portions formed on the surface;
A second step of forming a second semiconductor layer made of a group III nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer made of a group III nitride semiconductor on the second semiconductor layer,
The pressure for growing the first semiconductor layer is P1,
The pressure for growing the second semiconductor layer is P2,
When the pressure for growing the third semiconductor layer is P3,
P2 ≧ P1> P3
Semiconductor device manufacturing method characterized by satisfying In the manufacturing method of the semiconductor element according to claim 3 or 4,
The distance between the centers of the adjacent convex portions is D [μm],
The width of the convex portion is d [μm],
The height of the first semiconductor layer is t1 [μm],
When the height of the second semiconductor layer is t2 [μm],
0.8 × (D−d) <(t1 + t2) <2.0 [μm]
The manufacturing method of the semiconductor element characterized by satisfy | filling.