JP2012257205A - Ringing suppression circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ringing suppression circuit which can suppress ringing reliably by consuming the energy of waveform distortion with a simpler configuration.SOLUTION: An N channel MOSFET 7 is connected between a pair of signal lines 3P, 3N, and when the fact that the level of a differential signal transmitted via a transmission line 3 has changed from high to low is detected, a control circuit 14 turns the N channel MOSFET 7 on for a predetermined period. More specifically, impedance between the signal lines 3P, 3N decreases significantly because the N channel MOSFET 7 is brought into conduction in the period when the level of a differential signal transits, and the distortion energy of the differential signal waveform is absorbed thus suppressing the occurence of ringing reliably.

Description

  The present invention relates to a circuit that is connected to a transmission line that transmits a differential signal by a pair of high-potential side signal line and low-potential side signal line, and that suppresses ringing that occurs when the signal is transmitted.

  When a digital signal is transmitted through a transmission line, a part of the signal energy is reflected at the timing when the signal level changes on the receiving side, thereby causing waveform distortion such as overshoot or undershoot, that is, ringing. There are problems that arise. Conventionally, various proposals have been made on techniques for suppressing waveform distortion. For example, in Patent Document 1, when the signal voltage level transitions between low and high in the termination circuit 11 of the transmission line, the impedance of the termination 5 is temporarily reduced during the delay time given in the delay circuit 13. Techniques for making them disclosed are disclosed.

  In Patent Document 1, an auxiliary switching circuit 41 is connected in parallel to a conventionally used termination switching circuit 40. In the auxiliary switching circuit 41, four MOSFETs are connected in series between the power source Vcc and the ground. They are connected, and their switching control is performed by a signal transmitted to the terminal 5 and a signal obtained by delaying and inverting the signal by three series of inverters 21 to 23. However, in such a configuration, when the termination 5 is temporarily connected to the power supply Vcc or the ground, the on-resistances of a plurality of MOSFETs are connected in series or in series and in parallel between the two. It becomes. For this reason, the impedance of the termination | terminus 5 cannot fully be reduced. In order to reduce the on-resistance, it is necessary to increase the size of the MOSFET, but in this case, the termination circuit 11 is increased in size.

  In Patent Document 2, a switch 202 is connected between a high-voltage signal line 102 and a low-voltage signal line 103 that transmit a differential signal, and the waveform distortion detector 201 reverses the magnitude relationship of the voltage between the lines 102 and 103. When this is detected, a configuration is disclosed in which the switch 202 is closed and the lines 102 and 103 are short-circuited.

JP 2001-127805 A (see FIG. 1) JP 2010-103944 A (refer to FIG. 8)

  As in Patent Document 2, if the lines 102 and 103 are short-circuited, the impedance between the lines becomes zero, and the distortion of the signal waveform can be reduced in the vicinity of the node that receives the transmitted signal. However, since the energy of the waveform distortion component is not consumed in the case of a short circuit, the energy is reflected from the short circuit point and reaches the side of the node that transmitted the signal. As a result, other nodes are adversely affected.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a ringing suppression circuit capable of consuming waveform distortion energy with a simpler configuration and reliably suppressing ringing.

  According to the ringing suppression circuit of the first aspect, a voltage-driven single line switching element is connected between a pair of signal lines constituting the transmission line, and the control means is transmitted via the transmission line. When it is detected that the level of the differential signal changes between high and low, the line switching element is turned on for a certain period. In other words, the line-switching element conducts during the period when the level of the differential signal transitions, greatly reducing the impedance between the signal lines and absorbing the distortion energy of the differential signal waveform to more reliably suppress the occurrence of ringing. can do.

  According to the ringing suppression circuit of claim 2, the control means includes an inverting circuit that inverts and outputs the level of the differential signal, and a delay circuit that delays and outputs the level of the differential signal for a certain period. The switching operation of the line-to-line switching element is controlled by a logical product signal of the signal output from the inverting circuit and the signal output from the delay circuit. The “logical product” referred to here may be either positive logic or negative logic for input / output. For example, the input may be positive logic and the output may be negative logic. With this configuration, since the output signal of the inverting circuit and the output signal of the delay circuit have the same logic during a certain period given by the delay circuit, the line switching element is made conductive by the logical product signal. Ringing can be suppressed.

  According to the ringing suppression circuit of the third aspect, the inverting circuit is configured by the first switching element, and the delay circuit is configured by including the second and third switching elements and the RC filter circuit. The non-reference-side conduction terminal of the third switching element is connected to the control terminal of the second switching element, and the RC filter circuit is connected between one of the pair of signal lines and the control terminal of the third switching element. That is, the signal level can be inverted through the first switching element, and the delay time of the signal can be set according to the time constant of the RC filter circuit. Then, the switching operation of the third and second switching elements is performed by the signal delayed through the RC filter circuit, and the line-to-line switching element is made conductive by the logical product with the first switching elements connected in parallel. it can.

  By the way, in the structure which transmits a differential signal via a transmission line, the node of a transmission side transmits a signal by driving a signal line on the basis of own ground potential. However, when the transmission line becomes long and the distance between the transmission-side node and the reception-side node or termination circuit is large, the ground potential at each node may differ by several volts. Accordingly, since the ground potential is different between the ringing suppression circuit and the transmission side node, it is assumed that the ringing suppression effect cannot be sufficiently obtained if the charge / discharge time of the capacitor constituting the RC filter circuit changes. Is done.

  On the other hand, in the configuration of claim 3, since the RC filter circuit is connected between the transmission lines (the capacitor is connected between the control terminal of the second switching element and the other of the signal lines), even the node Even if there is a ground potential difference between them, the charging / discharging time of the capacitor is determined by the potential difference of the differential signal, so that the time for conducting the line switching element is constant. Accordingly, it is possible to reliably suppress ringing by eliminating the influence of the ground potential difference.

  According to the ringing suppression circuit of claim 4, the control terminal of the third switching element is connected to one of the pair of signal lines, and the RC filter circuit is connected to the non-reference side conduction terminal of the third switching element and the second switching element. Connect to the control terminal of the element. If comprised in this way, it will become the trigger that the level of the differential signal changed, the charge state of the capacitor | condenser which comprises RC filter circuit will be changed via a 2nd switching element, and it will change according to the change of the said charge state. A delay of a certain period can be given by changing the switching state of the three switching elements.

  That is, the signal level can be inverted through the first switching element, and the delay time of the signal can be set according to the time constant of the RC filter circuit. Then, the switching operation of the second switching element is performed by the signal delayed through the RC filter circuit, and the line-to-line switching element can be made conductive by the logical product with the first switching element connected in parallel.

  According to the ringing suppression circuit of the fifth aspect, between each pair of signal lines, each switching element performs a switching operation using the potential of the low potential side signal line as a reference potential, and each switching element has a high level. A second suppression circuit that performs a switching operation using the potential of the potential side signal line as a reference potential is connected in parallel. That is, the voltage-driven switching element performs a switching operation in accordance with a potential difference (referred to as an inter-terminal potential difference) between the potential reference side conduction terminal and the control terminal. Therefore, when the potential of the low potential side signal line or the potential of the high potential side signal line as the reference potential changes, the potential difference between the terminals may increase or decrease depending on the conductivity type and connection state of each switching element. .

  Since each switching element constituting the first suppression circuit performs a switching operation using the potential of the low potential side signal line as a reference potential, if the potential difference between the low potential side signal line and the control terminal becomes large, the switching operation is reliably performed. However, if the potential difference becomes small, the switching operation becomes difficult. In addition, since each switching element constituting the second suppression circuit performs a switching operation using the potential of the high potential side signal line as a reference potential, if the potential difference between the high potential side signal line and the control terminal becomes large, the switching operation is ensured. However, if the potential difference is small, the switching operation is difficult to be performed.

  Further, as described in claim 4, since there is a difference in the ground potential between the nodes, the potential of the low potential side signal line when the differential signal becomes high level with respect to the ground level on the suppression circuit side. If it is higher, the potential difference between the control terminal and the low-potential side signal line is narrowed, so that the switching element on the first suppression circuit side becomes difficult to perform the switching operation. However, at this time, the potential of the high potential side signal line is also higher than usual with respect to the ground level on the suppression circuit side, so that the switching element on the second suppression circuit side can easily perform the switching operation.

  Conversely, if the potential of the low potential signal line when the differential signal becomes high level is lower than the ground level on the suppression circuit side, the potential difference between the control terminal and the low potential signal line is widened. However, since the switching element on the first suppression circuit side can easily perform the switching operation, the potential of the high-potential side signal line is also lower than the normal level with respect to the ground level on the suppression circuit side. It becomes difficult to work. Therefore, if the first and second suppression circuits are connected in parallel between the pair of signal lines, either the first or the second suppression circuit operates reliably even when there is a difference in the ground potential between the nodes. Thus, ringing can be reliably suppressed.

  According to the ringing suppression circuit of the sixth aspect, the line-to-line switching element and the first to third switching elements are constituted by the zeroth to third N-channel MOSFETs. In this case, the sources that are potential reference side conduction terminals of the N-channel MOSFETs are all connected to the low-potential side signal line, and the first N-channel MOSFET corresponds to the potential difference from the high-potential side signal line connected to the gate. Switching operation is performed. That is, it is turned on when the differential signal is at a high level and turned off when it is at a low level.

  In the third N-channel MOSFET, the drain is pulled up via a resistance element. In the configuration corresponding to claim 3, the third N-channel MOSFET is turned on when the differential signal level is high, and discharges the capacitor of the RC filter circuit. As a result, the second N-channel MOSFET is turned off, but the first N-channel MOSFET is turned on, so that the gate potential of the 0th N-channel MOSFET is at a low level and is in the off state.

  When the differential signal level changes from high to low, the first N-channel MOSFET is turned off, so that the 0th N-channel MOSFET is turned on with the gate potential being high. As a result, the pair of signal lines are connected via the ON resistance of the 0th N-channel MOSFET, and distortion energy at the fall of the differential signal waveform is consumed. At the same time, the third N-channel MOSFET is turned off, and charging of the capacitor of the RC filter circuit is started. When the terminal voltage of the capacitor exceeds the threshold voltage after a certain period of time has elapsed, the second N-channel MOSFET is turned on, so that the 0th N-channel MOSFET is turned off with the gate potential being at a low level.

  In the configuration corresponding to claim 4, since the connection order of the third N-channel MOSFET and the RC filter circuit is reversed, the capacitor of the RC filter circuit is charged when the differential signal level is high, and the third N-channel MOSFET is charged. The channel MOSFET is on and the second N-channel MOSFET is off. Then, when the differential signal level changes from high to low, the capacitor starts discharging, and when the differential signal level falls below the threshold voltage, the third N-channel MOSFET is turned off and the second N-channel MOSFET is turned on. Therefore, the operation after the second N-channel MOSFET is the same as that of the third aspect.

  According to the ringing suppression circuit of the seventh aspect, the resistance element for pulling up the gate of the line switching element is set to have a diode whose anode is on the power supply side and the resistance value is smaller than that of the pull-up resistance element. A series circuit with a resistive element is connected in parallel. If comprised in this way, the resistance value of the current pathway at the time of flowing the electric current which charges the gate of the switching element between lines from a power supply will become low. Therefore, the line switching element can be turned on earlier to further suppress ringing.

  According to the ringing suppression circuit of the eighth aspect, the blocking element control means is the control unit of the communication node that outputs a standby signal for shifting the communication node connected to the transmission line to the standby state. The shut-off element control means gives a standby signal to the control terminal of the shut-off element connected between the 0th N-channel MOSFET and the second N-channel MOSFET, and turns off the shut-off element when shifting to the standby state.

  That is, in the configuration of the sixth or seventh aspect, since the gate is pulled up, the second N-channel MOSFET is in the ON state during the period when the differential signal is at the low level. Therefore, current flows from the power supply to the low potential signal line side via the second N-channel MOSFET, and unnecessary current consumption occurs. And since there is no possibility of communication during the period when the communication node is in the standby state, it is possible to suppress unnecessary current consumption by cutting off the current path by turning off the blocking element by the standby signal. .

  According to the ringing suppression circuit of the ninth aspect, the cutoff element control means detects the differential voltage level in the transmission line, and turns off the cutoff element during a period in which the differential voltage level falls below a predetermined threshold. That is, the differential voltage between the signal lines is 0 V (low level) during the period when the differential signal is not transmitted on the transmission line, so unnecessary current consumption is detected if the state is detected and the blocking element is turned off. Can be suppressed.

  According to the ringing suppression circuit of the tenth aspect, a series circuit of a resistance element and a capacitor connected between a pair of signal lines is provided, and a common connection point of the series circuit is connected to the gate of the first N-channel MOSFET. That is, the series circuit functions as a delay circuit that delays the time for raising the gate potential of the first N-channel MOSFET when the differential signal becomes high level. Thus, when an overshoot occurs after the differential signal waveform falls, the first N-channel MOSFET is prevented from turning on following the overshoot, and the 0th N-channel MOSFET is temporarily turned off. Can be prevented.

  According to the ringing suppression circuit of the eleventh aspect, the anode is provided with the diode connected in parallel to the resistance element in the direction of the common connection point side of the series circuit. As a result, when the differential signal level changes from high to low, the charged charge of the capacitor is rapidly discharged through the diode, and when the differential signal waveform falls, the first N-channel MOSFET is immediately turned off. be able to.

  According to the ringing suppression circuit of the twelfth aspect, the line-to-line switching element and the first to third switching elements are constituted by the 0th to third P-channel MOSFETs. In this case, the source that is the potential reference side conduction terminal of each P-channel MOSFET is connected to the high-potential side signal line, and the first P-channel MOSFET corresponds to the potential difference from the low-potential side signal line connected to the gate. Switching operation is performed. That is, it is turned on when the differential signal is at a high level and turned off when it is at a low level.

  The drain of the third P-channel MOSFET is pulled down via a resistance element. In the configuration corresponding to claim 3, the third P-channel MOSFET is turned on when the differential signal level is high, and discharges the capacitor of the RC filter circuit. As a result, the second P-channel MOSFET is turned off. However, since the first P-channel MOSFET is turned on, the gate potential of the 0th P-channel MOSFET is at a low level and is in the off state.

  When the differential signal level changes from high to low, the first P-channel MOSFET is turned off, so that the 0th P-channel MOSFET is turned on with the gate potential being low. As a result, the pair of signal lines are connected via the ON resistance of the 0th P-channel MOSFET, and distortion energy at the fall of the differential signal waveform is consumed. At the same time, the third P-channel MOSFET is turned off and charging of the capacitor of the RC filter circuit is started. When the terminal voltage of the capacitor exceeds the threshold voltage after a certain period of time has elapsed, the second P-channel MOSFET is turned on, so that the 0th P-channel MOSFET is turned off with the gate potential being at a high level.

  In the configuration corresponding to claim 4, the connection order of the third P-channel MOSFET and the RC filter circuit is reversed. Therefore, when the differential signal level is high, the capacitor of the RC filter circuit is charged. The channel MOSFET is turned on and the second P-channel MOSFET is turned off. When the differential signal level changes from high to low, the capacitor starts discharging, and when the differential signal level falls below the threshold voltage, the third P-channel MOSFET is turned off and the second P-channel MOSFET is turned on. Therefore, the operation after the second P-channel MOSFET is the same as that of the third aspect.

  14. The ringing suppression circuit according to claim 13, wherein the resistance element for pulling down the gate of the line switching element includes a diode whose cathode is on the ground side, and a resistance element whose resistance value is set smaller than that of the pull-down resistance element. And connect the series circuit in parallel. If comprised in this way, the resistance value of the electric current path at the time of flowing the electric current which discharges the gate of a switching element between lines to a low electric potential side signal line will become low. Therefore, the line switching element can be turned on earlier to further suppress ringing.

  According to the ringing suppression circuit of the fourteenth aspect, the blocking element control means is a communication node control unit that outputs a standby signal to shift the communication node connected to the transmission line to the standby state. The shut-off element control means gives a standby signal to the control terminal of the shut-off element connected between the 0th P-channel MOSFET and the second P-channel MOSFET, and turns off the shut-off element when shifting to the standby state.

  That is, in the configuration of the twelfth or thirteenth aspect, since the gate of the second P-channel MOSFET is pulled down, the second P-channel MOSFET is in an on state during a period in which the differential signal is not transmitted. Therefore, current flows from the power source to the low potential signal line side via the second P-channel MOSFET, and unnecessary current consumption occurs. And since there is no possibility of communication during the period when the communication node is in the standby state, it is possible to suppress unnecessary current consumption by cutting off the current path by turning off the blocking element by the standby signal. .

  According to the ringing suppression circuit of the fifteenth aspect, the blocking element control means detects the differential voltage level in the transmission line, and turns off the blocking element during a period in which the differential voltage level falls below a predetermined threshold. That is, since the differential voltage between the signal lines is 0 V during the period when the differential signal is not transmitted on the transmission line, unnecessary current consumption can be suppressed by detecting the state and turning off the blocking element.

  According to another aspect of the present invention, there is provided a ringing suppression circuit including a series circuit of a capacitor and a resistance element connected between a pair of signal lines, and a common connection point of the series circuit is connected to the gate of the first P-channel MOSFET. That is, the series circuit acts as a delay circuit that delays the time for raising the source-gate voltage of the first P-channel MOSFET when the differential signal becomes high level. As a result, if an overshoot occurs after the differential signal waveform falls, the first P-channel MOSFET is prevented from turning on following the overshoot, and the 0th P-channel MOSFET is temporarily turned off. Can be prevented.

  According to the ringing suppression circuit of the seventeenth aspect, the anode is provided with the diode connected in parallel to the resistance element in the direction of the common connection point side of the series circuit. As a result, when the differential signal level changes from high to low, the charged charge of the capacitor is rapidly discharged through the diode, and when the differential signal waveform falls, the first P-channel MOSFET is immediately turned off. be able to.

The figure which is a 1st Example and shows the structure of a ringing suppression circuit Timing chart showing operation of ringing suppression circuit FIG. 1 equivalent view showing the second embodiment 2 equivalent diagram FIG. 1 equivalent view showing the third embodiment FIG. 1 equivalent view showing the fourth embodiment The figure which shows the result of simulating the operation of the ringing suppression circuit FIG. 1 equivalent view showing the fifth embodiment Fig. 7 equivalent (when ground offset is 0V) Fig. 7 equivalent (Ground offset -7.5V) 7 equivalent diagram (in case of ground offset + 9.5V) FIG. 1 equivalent view showing the sixth embodiment Fig. 7 equivalent (when ground offset is 0V) Fig. 7 equivalent (Ground offset -7.5V) 7 equivalent diagram (in case of ground offset + 9.5V) FIG. 12 equivalent view showing the seventh embodiment The figure which shows the result of simulating the operation of the ringing suppression circuit FIG. 5 equivalent view showing the eighth embodiment The figure which shows the result of simulating the operation of the ringing suppression circuit Block diagram schematically showing the configuration of the communication node FIG. 18 equivalent diagram showing the ninth embodiment. 2 equivalent diagram FIG. 18 equivalent diagram showing the tenth embodiment.

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 shows the configuration of the ringing suppression circuit. The ringing suppression circuit 1 is connected in parallel between a transmission circuit 3 (which may be a reception circuit) 2 and a transmission line 3 including a high potential side signal line 3P and a low potential side signal line 3N. The ringing suppression circuit 1 includes four N-channel MOSFETs 4 to 7 (third to 0th N-channel MOSFETs) whose sources (potential reference-side conduction terminals) are all connected to the low-potential-side signal line 3N. The gate 6 (control terminal) is connected to the high potential side signal line 3P.

The drain (non-reference side conduction terminal) of the N-channel MOSFET 7 (interline switching element) is connected to the high potential side signal line 3P, and the drains of the N-channel MOSFETs 4 and 6 are connected to the gate of the N-channel MOSFET 7. And pulled up to a high level (power supply level; Vcc) via the resistance element 8. The drain of the N-channel MOSFET 4 (third switching element) is pulled up to a high level via the resistance element 9 and connected to the gate of the N-channel MOSFET 5 (second switching element) via the resistance element 10. Yes. The gate is connected to the low potential side signal line 3N via the capacitor 11.
That is, the resistance element 10 and the capacitor 11 constitute an RC filter circuit 12. The N-channel MOSFETs 4 and 5, the resistor element 9 and the RC filter circuit 12 constitute a delay circuit 13. The delay circuit 13, the resistor element 8 and the N-channel MOSFET 6 (first switching element) are controlled by a control circuit (control). Means) 14 is configured.

  Next, the operation of the first embodiment will be described with reference to FIG. The transmission line 3 transmits a binary signal of high level and low level as a differential signal by the transmission line 3 like CAN which is one of in-vehicle LANs, for example. For example, when the power supply voltage is 5 V, the high potential side signal line 3P (CAN-H) and the low potential side signal line 3N (CAN-L) are both set to an intermediate potential of 2.5 V in the non-driving state. The differential voltage is 0 V, and the differential signal is at a low level (recessive).

  When the transmission circuit 2 drives the transmission line 3, the high potential side signal line 3P is driven to, for example, 3.5V or more, the low potential side signal line 3N is driven to, for example, 1.5V or less, and the differential voltage becomes 2V or more. The differential signal becomes high level (dominant). Although not shown, both ends of the high-potential side signal line 3P and the low-potential side signal line 3N are terminated by 120Ω resistive elements. Therefore, when the differential signal level changes from high to low, the transmission line 3 is in a non-driven state and the impedance of the transmission line 3 is increased, so that ringing occurs in the differential signal waveform.

  FIG. 2 shows (a) the gate potential of each N-channel MOSFET 4-7 when the differential signal level changes from high to low, that is, the on / off state. When the differential signal level is high, (c) N-channel MOSFETs 4 and 6 are on, and (d) N-channel MOSFET 5 is off. Therefore, (b) the N-channel MOSFET 7 is in an off state.

  From this state, when (a) the differential signal level changes from high to low, (c) N-channel MOSFETs 4 and 6 are turned off, and (b) N-channel MOSFET 7 is turned on. Then, the high potential side signal line 3P and the low potential side signal line 3N are connected via the ON resistance of the N-channel MOSFET 7, and the impedance is lowered. As a result, energy of waveform distortion generated in the falling period in which the differential signal level changes from high to low is consumed by the on-resistance, and ringing is suppressed.

  When the N-channel MOSFET 4 is turned off, the capacitor 11 is charged via the resistance elements 9 and 10, and therefore, when the terminal voltage of the capacitor 11 rises above the threshold voltage of the N-channel MOSFET 5, (d) the N-channel MOSFET 5 is turned on. . Then, (b) the gate voltage of the N-channel MOSFET 7 becomes low level, and the N-channel MOSFET 7 is turned off. That is, the N-channel MOSFET 7 is turned on during a period when the N-channel MOSFETs 4 to 6 are all off (distortion suppression period), and the high-potential side signal line 3P and the low-potential side signal line 3N are connected via the on-resistance. Connecting.

  Here, the operation in which the ringing suppression circuit 1 turns on the N-channel MOSFET 7 triggered by the change of the differential signal from the high level to the low level can be regarded as operating with the following logic. That is, the N-channel MOSFET 6 is an inverting circuit that inverts the differential signal level applied to the gate and outputs the inverted signal level to the drain. The N-channel MOSFET 5 changes the falling change of the differential signal with the N-channel MOSFET 4 and the RC filter circuit 12. The signal is output to the drain after a certain delay. The N-channel MOSFET 7 is turned on in accordance with the logical product condition of both drain levels during the period when the drain levels of the N-channel MOSFETs 4 and 6 are both high. Therefore, this is equivalent to a configuration in which a logical product signal of the output signal of the inverting circuit and the output signal of the delay circuit 13 is output to the gate of the N-channel MOSFET 7.

  As described above, according to the present embodiment, the N-channel MOSFET 7 is connected between the pair of signal lines 3P and 3N, and the control circuit 14 determines that the level of the differential signal transmitted through the transmission line 3 is high to low. When it is detected that the N-channel MOSFET 7 has been changed, the N-channel MOSFET 7 is turned on for a certain period. In other words, the N-channel MOSFET 7 becomes conductive during the period when the level of the differential signal transitions, thereby greatly reducing the impedance between the signal lines 3P and 3N and absorbing the distortion energy of the differential signal waveform, thereby more reliably generating ringing. Can be suppressed.

  The control circuit 14 includes an inverting circuit that inverts and outputs the level of the differential signal; an N-channel MOSFET 6 and a delay circuit 13 that outputs the differential signal level after being delayed for a certain period. The N-channel MOSFET 7 is turned on by a logical product signal of the signal output from the circuit and the signal output from the delay circuit 13. Further, the delay circuit 13 is configured to include the N-channel MOSFETs 4 and 5 and the RC filter circuit 12, the drain of the N-channel MOSFET 5 is connected to the gate of the N-channel MOSFET 7, and the RC filter circuit 12 and the N-channel MOSFET 4 are connected. The drain was connected between the signal line 3N.

  As a result, the change in the level of the differential signal is used as a trigger, and the charge state of the capacitor 11 constituting the RC filter circuit 12 is changed via the N-channel MOSFET 4, and the RC filter is changed according to the change in the charge state. The switching state of the N-channel MOSFET 5 can be changed according to the time constant of the circuit 12 to give a delay of a certain period. Therefore, the output signal of the N-channel MOSFET 6 and the output signal of the delay circuit 13 have the same logic during a certain period given as a delay time by the RC filter circuit 12, and therefore the N-channel MOSFET 7 is set by the logical product signal thereof. It can be turned on to suppress ringing.

(Second embodiment)
3 and 4 show a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be described. The ringing suppression circuit 15 of the second embodiment is obtained by switching the connection order of the N-channel MOSFET 4 and the RC filter circuit 12 in the configuration of the ringing suppression circuit 1 of the first embodiment. That is, one end of the resistance element 10 that is the input terminal of the RC filter circuit 12 is connected to the high potential side signal line 3P, and the other end of the resistance element 10 that is the output terminal of the RC filter circuit 12 is connected to the gate of the N-channel MOSFET 4. Has been. The drain of the N channel MOSFET 4 is connected to the gate of the N channel MOSFET 5. The configuration in which the connection order of the N-channel MOSFET 4 and the RC filter circuit 12 is changed constitutes the delay circuit 16, and the N-channel MOSFET 6 and the resistance element 8 added to the delay circuit 16 is a control circuit (control means). 17 is constituted.

  FIG. 4 is a diagram corresponding to FIG. 2. (a) When the differential signal level changes from high to low, (e) only the N-channel MOSFET 6 is turned off at first, and (d) the N-channel MOSFET 5 is turned off at this time. (B) The N-channel MOSFET 7 is turned on. Then, a delay time is applied while the capacitor 11 of the RC filter circuit 12 that has been charged with the differential signal level being high is discharged. (C) When the gate of the N-channel MOSFET 4 becomes low level, MOSFET 4 is turned off. Then, (d) the N-channel MOSFET 5 is turned on, and (b) the gate voltage of the N-channel MOSFET 7 becomes low level, and the N-channel MOSFET 7 is turned off. As a result, the operation is the same as that of the first embodiment.

  Further, the ringing suppression circuit 15 of the second embodiment has the following operation. In the case of the ringing suppression circuit 1 of the first embodiment, the power supply voltage applied to the input terminal of the RC filter circuit 12 via the resistance element 9 is set to 5 V or the like with reference to the ground level G1 of the ringing suppression circuit 1. Yes. On the other hand, the high and low levels of the differential signal transmitted through the transmission line 3 are determined according to the ground level G2 of the transmission node that drives the transmission line 3. And in the structure where a communication node is arrange | positioned at each part of a vehicle like the transmission line 3 of vehicle-mounted LAN, it is assumed that the potential of the ground in each communication node is different (ground offset).

  For example, if the magnitude relationship between the ground levels G1 and G2 is G1> G2, the low level of the low potential side signal line 3N when the differential signal becomes dominant becomes lower than the assumed level. (For example, when what was assumed at 1.5 V as described above is a lower level), the potential difference between the power supply and the low level becomes larger. Then, since the time for charging the capacitor 11 of the RC filter circuit 12 is shortened, the delay time given by the RC filter circuit 12 is shortened, and the period during which the N-channel MOSFET 7 is turned on is shortened, thereby suppressing the ringing. May not be sufficiently obtained.

  On the other hand, in the ringing suppression circuit 15 of the second embodiment, the RC filter circuit 12 is directly connected between the high potential side signal line 3P and the low potential side signal line 3N, so that the differential signal becomes dominant. In this case, the differential voltage is constant regardless of the magnitude relationship between the ground levels G1 and G2. Therefore, since the delay time provided by the RC filter circuit 12 is constant, the period during which the N-channel MOSFET 7 is turned on is also constant, and the ringing suppression effect can be obtained with certainty.

  As described above, according to the second embodiment, the RC filter circuit 12 constituting the delay circuit 16 is connected between the high potential side signal line 3P and the gate of the N-channel MOSFET 5. If comprised in this way, the charge state of the capacitor | condenser 11 which comprises the RC filter circuit 12 will change with the level of the differential signal changing from high to low as a trigger. Then, the switching state of the N-channel MOSFETs 5 and 6 can be changed according to the change of the charging state, and a delay of a certain period can be given. Therefore, even if there is a ground potential difference between the communication nodes or between the communication nodes and the ringing suppression circuit 15, the charging / discharging time of the capacitor 11 is determined by the potential difference of the differential signal. It is possible to reliably suppress ringing by eliminating the influence of the ground potential difference.

(Third embodiment)
FIG. 5 shows a third embodiment, and only the parts different from the second embodiment will be described. The ringing suppression circuit 18 of the third embodiment is different from the ringing suppression circuit 15 of the second embodiment in the configuration on the gate side of the N-channel MOSFET 6. A series circuit of a resistance element 19 and a capacitor 20 is connected between the high potential side signal line 3P and the low potential side signal line 3N, and a common connection point of both is connected to the gate of the N-channel MOSFET 6. The diode 21 is connected in parallel to the resistance element 19 so that the anode is on the gate side. These constitute a delay circuit 22. A control circuit (control means) 23 is configured by adding a delay circuit 22 to the control circuit 17 of the second embodiment.

  Next, the operation of the third embodiment will be described. In the ringing suppression circuit 15 of the second embodiment, if overshoot occurs after the differential signal level falls from high to low, the N-channel MOSFET 6 is turned on and the N-channel MOSFET 7 is turned off. It is assumed that the suppression effect is reduced. Therefore, the gate of the N-channel MOSFET 6 is connected to the delay circuit 22 without being directly connected to the high potential side signal line 3P.

  That is, when the level changes from low to high due to the action of the delay circuit 22 such as an overshoot that occurs after the falling of the differential signal, the capacitor 20 is charged via the resistance element 19. The N channel MOSFET 7 is difficult to turn off. On the other hand, when the differential signal level changes from high to low, the charged charge of the capacitor 20 is immediately discharged via the diode 21, so that the turn-on of the N-channel MOSFET 7 is not affected.

  As described above, according to the third embodiment, a series circuit of the resistance element 19 and the capacitor 20 connected between the signal lines 3P and 3N is connected, and the diode 21 is connected in parallel to the resistance element 19 so that the delay circuit 22 is connected. The common connection point of the resistance element 19 and the capacitor 20 is connected to the gate of the N-channel MOSFET 6. Therefore, when an overshoot occurs after the differential signal waveform falls, the N-channel MOSFET 6 can be prevented from turning on following the overshoot, and the N-channel MOSFET 7 can be prevented from turning off temporarily. Further, when the differential signal level changes from high to low by the diode 21 connected in parallel to the resistance element 19, the charge of the capacitor 20 is rapidly discharged through the diode 21, and the differential signal waveform is When falling, the N-channel MOSFET 6 can be immediately turned off.

(Fourth embodiment)
6 and 7 show a fourth embodiment. The ringing suppression circuit 24 of the fourth embodiment uses a P-channel MOSFET having the same operation as the ringing suppression circuit 1 with the ringing suppression circuit 1 of the first embodiment as a ringing suppression circuit 1N (first suppression circuit). The ringing suppression circuit 1P (second suppression circuit) configured symmetrically is connected to the transmission line 3 in parallel.

  Hereinafter, the configuration of the ringing suppression circuit 1P will be described by adding “P” to the reference numerals corresponding to the components of the ringing suppression circuit 1N. The ringing suppression circuit 1P includes four P-channel MOSFETs 4P to 7P (third to zeroth P-channel MOSFETs) whose sources are all connected to the high potential side signal line 3P, and the gates (control terminals) of the P-channel MOSFETs 4P and 6P. Is connected to the low potential side signal line 3N.

  The drain of the P-channel MOSFET 7P is connected to the low potential side signal line 3N, and the drains of the P-channel MOSFETs 4P and 6P are connected to the gate of the P-channel MOSFET 7P and at the low level (ground level) via the resistance element 8P. ). The drain of the P-channel MOSFET 4P is pulled down to a low level via the resistance element 9P, and is connected to the gate of the N-channel MOSFET 5P via the resistance element 10P. The gate is connected to the high potential side signal line 3P through the capacitor 11P. That is, the resistance element 10P and the capacitor 11P constitute an RC filter circuit 12P.

  The operation of the ringing suppression circuit 1P is the same as that of the ringing suppression circuit 1N. That is, when the differential signal level is high, the P-channel MOSFETs 4P and 6P are on, so the P-channel MOSFET 5P is off and the P-channel MOSFET 7P is off. When the differential signal level changes from high to low, the P-channel MOSFETs 4P and 6P are turned off, so that the P-channel MOSFET 7P is turned on. Then, the high-potential-side signal line 3P and the low-potential-side signal line 3N are connected via the on-resistance of the P-channel MOSFET 7P, the impedance is lowered, the waveform distortion energy is consumed by the on-resistance, and ringing is suppressed. The

  When the P-channel MOSFET 4P is turned off, the capacitor 11P is charged through a path through the resistance elements 9P and 10P. Therefore, when the terminal voltage of the capacitor 11P rises above the threshold voltage of the P-channel MOSFET 5P, the P-channel MOSFET 5P is turned on. Then, the gate voltage becomes low level, and the P-channel MOSFET 7P is turned off.

Then, by connecting the ringing suppression circuits 1N and 1P in parallel to the transmission line 3, the following effects can be obtained. When only the ringing suppression circuit 1N is connected, as described in the second embodiment, there is a potential difference between the ground levels G1 and G2, and when G1 <G2, the ringing suppression circuit 1N has an N-channel MOSFET 4N. Since the gate-source voltage of ˜7 N is smaller, it is difficult to reliably turn them on. However, when this state is viewed with respect to the ringing suppression circuit 1P, the gate-source voltages of the P-channel MOSFETs 4P to 7P become larger, so that they are surely turned on. Further, if the magnitude relationship between the ground levels G1 and G2 is G1> G2, the above relationship is reversed, the ringing suppression circuit 1N is easy to operate, and the ringing suppression circuit 1P is difficult to operate.
Therefore, by connecting the ringing suppression circuits 1N and 1P in parallel, even when a ground offset exists between the communication nodes, at least one of the ringing suppression circuits 15N and 15P operates reliably.

  FIG. 7 shows a result of simulating the operation of the ringing suppression circuit 24 when there is no offset in the ground level of the transmission node and the reception node. FIG. 7 shows a network model used for the simulation. The three junction connectors J / C1, J / C2, and J / C3 are connected by a transmission line of 5 m, and each of the six communication nodes of the junction connectors J / C1 and J / C3 is 2 m. It is connected via a transmission line. A transmission node and a reception node are connected to the junction connector J / C2 via a transmission line of 4 m, respectively, and a ringing suppression circuit 24 is connected to the transmission line on the reception node side.

  FIG. 7 shows simulation results, both when the ringing suppression circuit 24 is connected (solid line; with distortion suppression) and when not connected (broken line; without distortion suppression). FIG. 7A shows voltage waveforms when the differential signal changes from dominant to recessive, and FIG. 7B shows voltage waveforms of the signal lines CAN-H and CAN-L at that time. As shown in FIG. 7A, it can be seen that the vibration of the voltage waveform after the transition to recessive converges more quickly in the case of “with distortion suppression”.

  As described above, according to the fourth embodiment, between the signal lines 3P and 3N, the ringing suppression circuit 1N in which each switching element is composed of N-channel MOSFETs 4N to 7N, and each switching element is composed of P-channel MOSFETs 4P to 7P. Since the ringing suppression circuit 1P is connected in parallel, one of the ringing suppression circuits 1N and 1P operates reliably even when there is a difference in the ground potential between the communication nodes, and the suppression of ringing is ensured. (Simulation regarding this action is shown in the fifth embodiment).

(5th Example)
8 to 11 show a fifth embodiment. In the ringing suppression circuit 25 of the fifth embodiment, the ringing suppression circuit 15 of the second embodiment is used as a ringing suppression circuit 15N (first suppression circuit), and a P-channel MOSFET is used that has the same function as the ringing suppression circuit 15. The ringing suppression circuit 15P (second suppression circuit) configured symmetrically is connected to the transmission line 3 in parallel. 9 corresponds to FIG. 8 when there is no ground offset, FIG. 10 corresponds to FIG. 8 when the ground offset is −7.5V, and FIG. 11 corresponds to FIG. 8 when the ground offset is + 9.5V. Accordingly, in FIG. 10B, the intermediate potential in the recessive state is −5V, and in FIG. 11B, the intermediate potential is 12V. Then, as shown in FIGS. 9A to 11A, it can be seen that the fluctuation of the ringing waveform is suppressed when the ringing suppression circuit 25 is connected regardless of the presence or absence of the ground offset.

(Sixth embodiment)
12 to 15 show a sixth embodiment. The ringing suppression circuit 26 of the sixth embodiment uses a P-channel MOSFET having the same operation as the ringing suppression circuit 18 with the ringing suppression circuit 18 of the third embodiment used as the ringing suppression circuit 18N (first suppression circuit). The ringing suppression circuit 18P (second suppression circuit) configured symmetrically is connected to the transmission line 3 in parallel. However, the diode 21 is not connected, and the diode 27 is connected to both ends of the resistance element 10. The anode of the diode 27N is connected to the high potential side signal line 3P, and the anode of the diode 27P is connected to the gate of the P-channel MOSFET 4P.

  13 corresponds to FIG. 8 when there is no ground offset, FIG. 14 corresponds to FIG. 8 when the ground offset is −7.5V, and FIG. 15 corresponds to FIG. 8 when the ground offset is + 9.5V. Accordingly, in FIG. 14B, the intermediate potential in the recessive state is −5V, and in FIG. 15B, the intermediate potential is 12V. Then, as shown in FIGS. 13A to 15A, it can be seen that the fluctuation of the ringing waveform is suppressed when the ringing suppression circuit 26 is connected regardless of the presence or absence of the ground-off line.

(Seventh embodiment)
16 and 17 show a seventh embodiment. In the ringing suppression circuit 28 of the seventh embodiment, a diode 21 is connected in parallel to the resistance element 19 in the ringing suppression circuits 18N and 18P of the sixth embodiment, as in the third embodiment. Further, a series circuit of a diode 29 and a resistance element 30 is connected to the resistance element 8 in parallel. The resistance element 8N is connected in a direction in which the anode of the diode 29N is on the power supply Vcc side, and the resistance element 8P is connected in the direction in which the cathode of the diode 29P is on the ground side. The above constitutes the ringing suppression circuits 18N ′ and 18P ′. The resistance value of the resistance element 30N is set smaller than the resistance value of the pull-up resistance element 8N, and the resistance value of the resistance element 30P is set smaller than the resistance value of the pull-down resistance element 8P. ing.

  Next, the operation of the seventh embodiment will be described with reference to FIG. FIG. 17 shows the result of simulating the circuit operation of the ringing suppression circuit 18P. Note that the voltage 0V on the vertical axis is 0V for the communication voltage (differential voltage), and the gate voltage of the P-channel MOSFET 7P is shown by shifting the reference voltage for convenience of illustration. The waveform before providing the series circuit of the diode 29 and the resistance element 30 (without countermeasures) is indicated by a broken line, and the waveform after being provided (with countermeasures) is indicated by a solid line.

  By connecting a series circuit of a diode 29P and a resistance element 30P in parallel to the element 8P which is a pull-down resistor, the gate voltage Vgs of the P-channel MOSFET 7P is discharged from the gate to the ground when attempting to transition from the high level to the low level. The resistance value of the path through which current flows becomes lower. As a result, the fall of the gate voltage Vgs is steeper than when the series circuit is not connected, and the P-channel MOSFET 7P (final stage PMOS) is turned on earlier.

As for the N-channel MOSFET 7N, the gate voltage Vgs of the N-channel MOSFET 7N attempts to transition from the low level to the high level by connecting the series circuit of the diode 29N and the resistance element 30N in parallel to the element 8N that is a pull-up resistor. In this case, the resistance value of the path through which the charging current flows from the power source Vcc to the gate becomes lower. As a result, the rise of the gate voltage Vgs becomes steeper than when the series circuit is not connected, so that the N-channel MOSFET 7N is turned on earlier.
According to the seventh embodiment configured as described above, the N-channel MOSFETs 7N and 7P can be turned on earlier, and ringing can be further suppressed.

(Eighth embodiment)
18 to 20 show an eighth embodiment. As shown in FIG. 20, each communication node 31 connected to the transmission line 3 includes a transceiver IC 32 including a transmission circuit and a reception circuit 2 and a controller IC 33 (blocking element control means, control unit) that performs communication control. It is configured. The controller IC 33 is configured mainly with a microcomputer. For example, in an idle state where communication is not required, there is a controller IC 33 having a function of shifting to a standby mode to reduce power consumption. Therefore, in the eighth embodiment, a high-active standby signal is output to the transceiver IC 32 when the controller IC 33 shifts to the standby mode.

  Further, in the eighth embodiment, as shown in FIG. 18, in the configuration of the third embodiment shown in FIG. 5, a P-channel MOSFET 34 (blocking element) is provided between the drain of the N-channel MOSFET 6 and the drain of the N-channel MOSFET 5. And the standby signal is applied to the gate (control terminal) of the P-channel MOSFET 34. The above constitutes the ringing suppression circuit 35.

  Next, the operation of the eighth embodiment will be described. When the controller IC 33 performs communication in the normal operation mode, since the standby signal is inactive (low), the P-channel MOSFET 34 is on. Therefore, the ringing suppression circuit 35 operates in the same manner as in the third embodiment. On the other hand, when the controller IC 33 shifts to the standby mode, the P-channel MOSFET 34 is turned off to change the standby signal to active (power supply voltage Vcc level).

  That is, even when a differential signal is not transmitted on the transmission line 3 and the differential voltage is 0 V (low level), the N-channel MOSFET 5 is kept on because the gate is pulled up. Therefore, a current flows from the power source to the signal line 3N via the resistance element 8 and the N-channel MOSFET 5. Therefore, if the P-channel MOSFET 34 is turned off, the current flowing in the above state can be cut off to reduce power consumption.

  Note that FIG. 19 is a simulation of the falling waveform of the differential signal in the state where the P-channel MOSFET 34 is not added (without countermeasures) and the state where it is added (with countermeasures). By adding the P-channel MOSFET 34, the resistance value of the path connected to the gate of the N-channel MOSFET 7 increases by the on-resistance of the P-channel MOSFET 34. However, there is almost no difference between the two, and the ringing suppression effect is not affected.

As described above, according to the eighth embodiment, the controller IC 33 controls on / off of the P-channel MOSFET 34 connected between the gate of the N-channel MOSFET 7 and the drain of the N-channel MOSFET 5. In this case, the controller IC 33 gives a standby signal for shifting the communication node 31 to the standby state to the gate of the P-channel MOSFET 34, and turns off the P-channel MOSFET 34 during the transition to the standby state.
That is, since there is no possibility of communication during the period when the communication node 31 is in the standby state, the P channel MOSFET 34 is turned off by the standby signal, so that the current is supplied from the power source through the N channel MOSFET 5 to the low potential signal. By interrupting the path flowing to the line 3N side, unnecessary current consumption can be suppressed.

(Ninth embodiment)
21 and 22 show a ninth embodiment. In the ninth embodiment, as in the eighth embodiment, a P-channel MOSFET 34 is connected between the drain of the N-channel MOSFET 6 and the drain of the N-channel MOSFET 5. Here, the receiving circuit 2 has a built-in configuration for determining whether or not a differential signal is transmitted through the transmission line 3. For example, the differential amplifier circuit detects the differential voltage of the transmission line 3, and the output signal of the differential amplifier circuit is compared with a predetermined threshold voltage by the comparator to determine whether or not a dominant level signal is received. To do.

  Therefore, when the output signal of the comparator is input from the receiving circuit 2 to the controller IC 33A and the differential voltage of the transmission line 3 exceeds a threshold value of, for example, 1.0 V, a high level signal is input to the controller IC 33A. The controller IC 33A applies a gate signal to the gate of the P-channel MOSFET 34. If the input signal is low level, the gate signal is set to high level, and if the input signal is high level, the gate signal is set to low level. FIG. 22 is a diagram corresponding to FIG. 2, and the P-channel MOSFET 34 is turned off when the differential signal is not transmitted on the transmission line 3 (see (a) and (e)). Therefore, it is possible to prevent a current from flowing from the power source to the signal line 3N via the resistance element 8 and the N-channel MOSFET 5. The above constitutes the ringing suppression circuit 35 '.

  As described above, according to the ninth embodiment, the controller IC 33A detects the differential voltage level in the transmission line by the receiving circuit 3, and turns off the P-channel MOSFET 34 when the differential voltage level falls below a predetermined threshold value. Thereby, unnecessary current consumption can be suppressed during a period when the differential signal is at a low level in the transmission line 3.

(Tenth embodiment)
FIG. 23 shows a tenth embodiment. In the tenth embodiment, the configuration of the eighth embodiment is applied to the ringing suppression circuit 15P shown in FIG. 8, and an N-channel MOSFET 37 (blocking element) is provided between the drain of the P-channel MOSFET 5P and the gate of the P-channel MOSFET 7P. Are connected to form a ringing suppression circuit 38P. A gate signal is given to the gate of the N-channel MOSFET 37 by the controller IC as in the eighth embodiment, but the signal level is the inverse of the eighth embodiment. According to the tenth embodiment configured as described above, unnecessary power consumption can be reduced even in the ringing suppression circuit 38P configured by a P-channel MOSFET.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The ringing suppression circuit may be connected to any one or more of the transmission lines, but may be connected to the vicinity of each communication node.
The delay circuit is not limited to the RC filter circuit, and for example, a delay line may be used.
The ringing suppression circuit may be configured to suppress ringing that occurs when the differential signal level changes from low to high.
The configurations of the seventh to tenth embodiments may be applied to other embodiments. For example, the ninth and tenth embodiments may be implemented in combination.
The communication protocol is not limited to CAN, and can be applied as long as it is a communication protocol that transmits a differential signal through a transmission line including a pair of signal lines.

In the drawings, 1 is a ringing suppression circuit, 3 is a transmission line, 3P is a high potential side signal line, 3N is a low potential side signal line, 4N to 6N are N channel MOSFETs (third to first switching elements), 4P to 6P. Is a P-channel MOSFET (third to first switching elements), 7N is an N-channel MOSFET (interline switching element), 7P is a P-channel MOSFET (interline switching element), 8 to 10 are resistance elements, 11 is a capacitor, Is an RC filter circuit, 13 is a delay circuit, 14 is a control circuit (control means), 15 is a ringing suppression circuit, 16 is a delay circuit, 17 is a control circuit (control means), 18 is a ringing suppression circuit, 19 is a resistance element, 20 is a capacitor, 21 is a diode, 22 is a delay circuit, 23 is a control circuit (control means), 24 to 26 and 28 are ringing suppression circuits, 9 diode, 30 is a resistor, 31 is a communication node,
33 and 33A are controller ICs (blocking element control means, control unit), 34 is a P-channel MOSFET (blocking element), 35 and 35 'are ringing suppression circuits, 37 is an N-channel MOSFET (blocking element), and 38P is A ringing suppression circuit is shown.

Claims (17)

Ringing suppression that suppresses ringing caused by transmission of the signal connected to a transmission line that transmits a differential signal that changes to a binary level of high and low by a pair of high potential side signal line and low potential side signal line In the circuit
A voltage-driven single line switching element connected between the pair of signal lines;
A ringing suppression circuit comprising: control means for turning on the line-to-line switching element for a certain period when it detects that the level of the differential signal has changed. The control means includes an inverting circuit that inverts and outputs the level of the differential signal;
A delay circuit that delays and outputs the level of the differential signal for the predetermined period,
2. The ringing suppression circuit according to claim 1, wherein a logical product signal of the signal output from the inverting circuit and the signal output from the delay circuit is output to a control terminal of the line switching element. In the inverting circuit, a control terminal is connected to one of the pair of signal lines, a potential reference side conduction terminal is connected to the other of the pair of signal lines, and a non-reference side conduction terminal is a control terminal of the line switching element. A voltage-driven first switching element connected to
The delay circuit includes a voltage-driven second switching element connected in parallel to the first switching element, an RC filter circuit, and a potential reference side conduction terminal connected to the potential reference side conduction terminal of the second switching element. A voltage-driven third switching element,
The non-reference side conduction terminal of the third switching element is connected to the control terminal of the second switching element,
The ringing suppression circuit according to claim 2, wherein the RC filter circuit is connected between one of the pair of signal lines and a control terminal of the third switching element. In the inverting circuit, a control terminal is connected to one of the pair of signal lines, a potential reference side conduction terminal is connected to the other of the pair of signal lines, and a non-reference side conduction terminal is a control terminal of the line switching element. A voltage-driven first switching element connected to
The delay circuit includes a voltage-driven second switching element connected in parallel to the first switching element, an RC filter circuit, and a potential reference side conduction terminal connected to the potential reference side conduction terminal of the second switching element. A voltage-driven third switching element,
The control terminal of the third switching element is connected to one of the pair of signal lines,
The ringing suppression circuit according to claim 2, wherein the RC filter circuit is connected between a non-reference-side conduction terminal of the third switching element and a control terminal of the second switching element. A first suppression circuit that performs a switching operation between the pair of signal lines using the potential of the low-potential side signal line as a reference potential;
5. The ringing suppression circuit according to claim 3, wherein each of the switching elements is connected in parallel to a second suppression circuit that performs a switching operation using the potential of the high potential side signal line as a reference potential. The line switching element is a 0th N-channel MOSFET in which a gate is pulled up via a resistance element, a drain is connected to the high potential side signal line, and a source is connected to the low potential side signal line,
The first switching element is a first N-channel MOSFET having a gate connected to the high-potential side signal line, a drain connected to the gate of the 0th N-channel MOSFET, and a source connected to the low-potential side signal line. ,
The second switching element is a second N-channel MOSFET connected in parallel to the first N-channel MOSFET;
6. The third switching element according to claim 3, wherein the third switching element is a third N-channel MOSFET in which a drain is pulled up via a resistance element and a source is connected to the low potential side signal line. The ringing suppression circuit described.   A series circuit of a resistance element that pulls up the gate of the line switching element, a diode whose anode is on the power supply side, and a resistance element whose resistance value is set to be smaller than that of the pull-up resistance element is connected in parallel. 7. The ringing suppression circuit according to claim 6, wherein A blocking element connected between the gate of the 0th N-channel MOSFET and the drain of the second N-channel MOSFET;
An interruption element control means for controlling on / off of the interruption element;
The blocking element control means is a control unit of the communication node that outputs a standby signal in order to shift a communication node connected to the transmission line to a standby state,
8. The ringing suppression circuit according to claim 6, wherein the standby signal is applied to a control terminal of the blocking element, and the blocking element is turned off when the standby state is entered. A blocking element connected between the gate of the 0th N-channel MOSFET and the drain of the second N-channel MOSFET;
An interruption element control means for controlling on / off of the interruption element;
8. The blocking element control means detects a differential voltage level in the transmission line and turns off the blocking element during a period in which the differential voltage level falls below a predetermined threshold. The ringing suppression circuit described. A series circuit of a resistance element and a capacitor connected between the pair of signal lines;
The ringing suppression circuit according to claim 6, wherein the common connection point of the series circuit is connected to the gate of the first N-channel MOSFET.   The ringing suppression circuit according to claim 10, further comprising a diode connected in parallel to the resistance element in a direction in which an anode becomes a common connection point side of the series circuit. The line switching element is a 0th P-channel MOSFET in which a gate is pulled down via a resistance element, a drain is connected to the low potential side signal line, and a source is connected to the high potential side signal line,
The first switching element is a first P-channel MOSFET having a gate connected to the low-potential side signal line, a drain connected to the gate of the 0th P-channel MOSFET, and a source connected to the high-potential side signal line. ,
The second switching element is a second P-channel MOSFET connected in parallel to the first P-channel MOSFET;
6. The third switching element according to claim 3, wherein the third switching element is a third P-channel MOSFET in which a drain is pulled down via a resistance element and a source is connected to the high potential side signal line. Ringing suppression circuit.   A series circuit of a resistance element that pulls down the gate of the line-to-line switching element and a diode whose cathode is the ground side and a resistance element whose resistance value is set smaller than that of the pull-down resistance element is connected in parallel. The ringing suppression circuit according to claim 12. A blocking element connected between the gate of the 0th P-channel MOSFET and the drain of the second P-channel MOSFET;
An interruption element control means for controlling on / off of the interruption element;
The blocking element control means is a control unit of the communication node that outputs a standby signal in order to shift a communication node connected to the transmission line to a standby state,
14. The ringing suppression circuit according to claim 12, wherein the standby signal is supplied to a control terminal of the cutoff element, and the cutoff element is turned off when the standby state is entered. A blocking element connected between the gate of the 0th P-channel MOSFET and the drain of the second P-channel MOSFET;
An interruption element control means for controlling on / off of the interruption element;
The shut-off element control means detects a differential voltage level in the transmission line, and turns off the shut-off element during a period in which the differential voltage level falls below a predetermined threshold. The ringing suppression circuit described. A series circuit of a capacitor and a resistance element connected between the pair of signal lines,
16. The ringing suppression circuit according to claim 12, wherein a common connection point of the series circuit is connected to a gate of the first P-channel MOSFET.   The ringing suppression circuit according to claim 16, further comprising a diode connected in parallel to the resistance element in a direction in which an anode is on a common connection point side of the series circuit.

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