JP5543402B2 - Ringing suppression circuit - Google Patents

Description

  The present invention relates to a circuit that is connected to a transmission line that transmits a differential signal by a pair of high-potential side signal line and low-potential side signal line, and that suppresses ringing that occurs when the signal is transmitted.

  When a digital signal is transmitted through a transmission line, a part of the signal energy is reflected at the timing when the signal level changes on the receiving side, thereby causing waveform distortion such as overshoot or undershoot, that is, ringing. There are problems that arise. Conventionally, various proposals have been made on techniques for suppressing waveform distortion. For example, in Patent Document 1, when the signal voltage level transitions between low and high in the termination circuit 11 of the transmission line, the impedance of the termination 5 is temporarily reduced during the delay time provided in the delay circuit 20. Techniques for making them disclosed are disclosed.

  In Patent Document 1, an auxiliary switching circuit 41 is connected in parallel to a conventionally used termination switching circuit 40. In the auxiliary switching circuit 41, four MOSFETs are connected in series between the power source Vcc and the ground. They are connected, and their switching control is performed by a signal transmitted to the terminal 5 and a signal obtained by delaying and inverting the signal by three series of inverters 21 to 23. However, in such a configuration, when the termination 5 is temporarily connected to the power supply Vcc or the ground, the on-resistances of a plurality of MOSFETs are connected in series or in series and in parallel between the two. It becomes. For this reason, the impedance of the termination | terminus 5 cannot fully be reduced. In order to reduce the on-resistance, it is necessary to increase the size of the MOSFET, but in this case, the termination circuit 11 is increased in size.

  In Patent Document 2, a switch 202 is connected between a high-voltage signal line 102 and a low-voltage signal line 103 that transmit a differential signal, and the waveform distortion detector 201 reverses the magnitude relationship of the voltage between the lines 102 and 103. When this is detected, a configuration is disclosed in which the switch 202 is closed and the lines 102 and 103 are short-circuited.

JP 2001-127805 A (see FIG. 1) JP 2010-103944 A (refer to FIG. 8)

  As in Patent Document 2, if the lines 102 and 103 are short-circuited, the impedance between the lines becomes zero, and the distortion of the signal waveform can be reduced in the vicinity of the node that receives the transmitted signal. However, since the energy of the waveform distortion component is not consumed in the case of a short circuit, the energy is reflected from the short circuit point and reaches the side of the node that transmitted the signal. As a result, other nodes are adversely affected.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a ringing suppression circuit capable of consuming waveform distortion energy with a simpler configuration and reliably suppressing ringing.

  According to the ringing suppression circuit of the first aspect, the voltage-driven first and second interline switching elements are connected in series between the pair of signal lines, and the control means changes the level of the differential signal. When this is detected, the first and second line switching elements are simultaneously turned on for a certain period. In other words, the switching between the two line switching elements becomes conductive during the transition of the differential signal level, thereby greatly reducing the impedance between the signal lines and absorbing the distortion energy of the differential signal waveform to more reliably generate ringing. Can be suppressed.

  According to the ringing suppression circuit of claim 2, the control means includes an inverting circuit that inverts and outputs the level of the differential signal, and a delay circuit that delays and outputs the level of the differential signal for a certain period. In this configuration, one of the first and second line switching elements is turned on by a signal output from the inverting circuit, and the other of the first and second line switching elements is turned off by a signal output from the delay circuit. In other words, if one of the line switching elements is off and the other line switching element is on before the differential signal level changes, the former is immediately turned on when the differential signal level changes. As a result, both line-to-line switching elements are turned on. If a certain period of time elapses from that point, the other line switching element is turned off, and the ringing suppression operation is stopped.

  According to the ringing suppression circuit of claim 3, the potential reference side conduction terminal is connected to one of the pair of signal lines and the control terminal becomes conductive when the differential signal indicates a high level. And a non-reference-side conduction terminal is constituted by a voltage-driven control switching element connected to one control terminal of the line-to-line switching element. That is, the control switching element becomes conductive when the differential signal indicates a high level, thereby setting the non-reference side conductive terminal, that is, the control terminal of one of the line switching elements to a low level.

  The delay circuit is configured by a series circuit of a resistor element and a capacitor connected between a pair of signal lines, and a common connection point of the resistor element and the capacitor is connected to the other control terminal of the line-to-line switching element. That is, if the differential signal is at a low level, the capacitor is in a discharged state, and charging of the capacitor is started when the differential signal is at a high level. When a certain period of time elapses, the potential at the common connection point of the series circuit becomes high level. As a result, the logic of each signal output from the inverting circuit and the delay circuit is different for a certain period after the level of the differential signal changes. Therefore, if the conductivity types of the first and second line-to-line switching elements are different from each other, both switching elements are simultaneously turned on during a certain period in which the logic of each signal is different.

  According to the ringing suppression circuit of claim 4, the control switching element has a source connected to the low potential side signal line, a drain pulled up via the resistor, and connected to the control terminal of the line switching element. The gate of the N channel MOSFET is connected to the high potential side signal line. Thereby, the inverted signal of the differential signal level is output to the drain of the N-channel MOSFET, that is, to the control terminal of one of the line switching elements.

  According to the ringing suppression circuit of claim 5, the control switching element has a source connected to the low potential side signal line, a drain pulled up via the resistor, and connected to a control terminal of the line switching element. N-channel MOSFET. Further, as an inverting circuit, a series circuit of a resistance element and a capacitor connected between the high potential side signal line and the low potential side signal line is provided, and the gate of the N-channel MOSFET is connected to a common connection point of the series circuit. . With this configuration, when the differential signal level becomes high, the rise in the gate potential of the N-channel MOSFET can be delayed by the time constant of the series circuit. Therefore, when an overshoot occurs after the differential signal waveform falls, it is possible to suppress the N-channel MOSFET from turning on following the overshoot and prevent the line-to-line switching element from turning off temporarily. .

  According to the ringing suppression circuit of the sixth aspect, the diode is connected in parallel to the resistance element constituting the inverting circuit in such a direction that the anode faces the low potential side signal line. As a result, even when a series circuit that delays the follow-up operation with respect to the occurrence of overshoot is provided, the signal can be rapidly inverted when the differential signal level transitions from high to low.

  According to the ringing suppression circuit of the seventh aspect, the control switching element has the source connected to the high potential side signal line, the drain pulled down via the resistor, and connected to the control terminal of the line switching element. A P-channel MOSFET is used, and the gate of the P-channel MOSFET is connected to the low potential side signal line. Thereby, the inverted signal of the differential signal level is output to the drain of the P-channel MOSFET, that is, to the control terminal of one of the line switching elements.

  According to the ringing suppression circuit according to claim 8, the source of the control switching element is connected to the high potential side signal line, the drain is pulled down via the resistor, and is connected to the control terminal of the line switching element. A P-channel MOSFET is used. The inverting circuit includes a series circuit of a capacitor and a resistance element connected between the high potential side signal line and the low potential side signal line, and the gate of the P-channel MOSFET is connected to the common connection point of the series circuit. . With this configuration, when the differential signal level becomes high, the rise of the source-gate potential of the P-channel MOSFET can be delayed by the time constant of the series circuit. Therefore, when an overshoot occurs after the differential signal waveform falls, it is possible to suppress the P-channel MOSFET from turning on following the overshoot and prevent the line-to-line switching element from turning off temporarily. .

  According to the ringing suppression circuit of the ninth aspect, the diode is connected in parallel to the resistance element constituting the inverting circuit in a direction in which the anode faces the low potential side signal line. As a result, even when a series circuit that delays the follow-up operation with respect to the occurrence of overshoot is provided, the signal can be rapidly inverted when the differential signal level transitions from high to low.

  According to the ringing suppression circuit of claim 10, two sets of series circuits of the first and second line switching elements are connected in parallel between the pair of signal lines, one of them being the first series circuit and the other being the other. The second series circuit is provided, and the control means includes two sets of first control means for controlling the first series circuit and second control means for controlling the second series circuit. Then, the first and second control switching elements constituting the first and second control means are connected to different control terminals, potential reference side conduction terminals, and a pair of signal lines having different connection relations. It is composed of mold elements. In addition, the non-reference-side conduction terminals of the first and second control switching elements are pulled up or pulled down via resistance elements, respectively, and the control terminals of the line-type switching elements of the same conductivity type in the first and second series circuits Connected to.

  Here, the voltage-driven switching element performs a switching operation according to a potential difference (referred to as an inter-terminal potential difference) between the potential reference side conduction terminal and the control terminal. Therefore, when the potential difference between the power supply voltage and the low potential side signal line or the potential difference between the high potential side signal line and the ground changes, the potential difference between the terminals widens and narrows depending on the conductivity type and connection state of each switching element. There is. In a configuration in which a differential signal is transmitted through a transmission line, a transmission-side node transmits a signal by driving a signal line with reference to its own ground potential. However, when the transmission line becomes long and the distance between the transmission-side node and the reception-side node or termination circuit is large, the ground potential at each node may differ by several volts.

  In the first and second series circuits, one of the control terminals of the line-type switching element having the same conductivity type as that of the first and second control switching elements is pulled up and the other is pulled down. Therefore, for the line switching element in which the control terminal is pulled up, the potential of the high potential side signal line when the differential signal becomes high level is higher than the ground level reference on the ringing suppression circuit side. If it becomes low, it will become easy to perform switching operation, and if it becomes lower, it will become difficult to perform switching operation. On the other hand, for the line switching element whose control terminal is pulled down, if the potential of the low potential signal line when the differential signal becomes high level is higher than the power supply level reference on the ringing suppression circuit side Switching operation becomes difficult, and if it is lower, switching operation is easier.

  As described above, since the ground potential between the nodes is different, the potential of the low potential side signal line when the differential signal becomes high level is higher than usual with respect to the ground level on the suppression circuit side. If it is higher, the potential difference between the power supply voltage and the low-potential side signal line is narrowed, so that one of the switching elements of the first and second series circuits is difficult to perform the switching operation. However, at this time, since the potential of the high potential side signal line is also higher than usual with respect to the ground level on the suppression circuit side, the other switching element is easily switched.

  Conversely, if the potential of the low potential signal line when the differential signal becomes high is lower than normal with respect to the ground level on the suppression circuit side, the potential difference between the power supply voltage and the low potential signal line However, since the potential of the high-potential side signal line is also lower than normal with respect to the ground level on the suppression circuit side, the other switching element is difficult to perform the switching operation. Become. Therefore, if the first and second series circuits are connected in parallel between the pair of signal lines and each is controlled by the first and second control means, either one of them is in a state where there is a difference in the ground potential between the nodes. It becomes possible to operate reliably, and ringing can be reliably suppressed.

  According to the ringing suppression circuit of claim 11, the drains of the first and second line switching elements are connected in common, and the sources are connected to the high potential side signal line and the low potential side signal line, respectively. Since the P channel MOSFET and the N channel MOSFET are used, the gate potential of the P channel MOSFET is set to the low level with respect to the high potential side signal line, and the gate potential of the N channel MOSFET is set to the high level with respect to the low potential side signal line. Both can be turned on at the same time.

The figure which is a 1st Example and shows the structure of a ringing suppression circuit Timing chart showing operation of ringing suppression circuit FIG. 1 equivalent view showing the second embodiment FIG. 1 equivalent view showing the third embodiment FIG. 1 equivalent view showing the fourth embodiment FIG. 1 equivalent view showing the fifth embodiment The figure which shows the simulation result of the circuit operation (the 1) Figure 7 equivalent (part 2) Figure 7 equivalent (part 3) FIG. 1 equivalent view showing the fifth embodiment Diagram showing simulation results of circuit operation

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 shows the configuration of the ringing suppression circuit. The ringing suppression circuit 1 is connected in parallel between a transmission circuit 3 (which may be a reception circuit) 2 and a transmission line 3 including a high potential side signal line 3P and a low potential side signal line 3N. The ringing suppression circuit 1 includes a P-channel MOSFET 4 and an N-channel MOSFET 5 (first and second line switching elements) connected in series with a common drain (non-reference side conduction terminal) between the transmission lines 3. Yes.

  Further, a series circuit of a capacitor 6 and a resistance element 7 is connected between the transmission lines 3, and a common connection point between them is connected to the gate (control terminal) of the P-channel MOSFET 4. The series circuit constitutes a delay circuit 8. The source (potential reference side conduction terminal) of the N-channel MOSFET 9 (inverting circuit, control switching element) is connected to the low potential side signal line 3N, and the drain is set to the high level (power supply level) via the resistance element 10. Pulled up, the gate is connected to the high potential side signal line 3P. Note that the delay circuit 8, the N-channel MOSFET 9 and the resistance element 10 constitute a control circuit (control means) 11.

  Next, the operation of the first embodiment will be described with reference to FIG. The transmission line 3 transmits a binary signal of high level and low level as a differential signal by the transmission line 3 like CAN which is one of in-vehicle LANs, for example. For example, when the power supply voltage is 5 V, the high potential side signal line 3P (CAN-H) and the low potential side signal line 3N (CAN-L) are both set to an intermediate potential of 2.5 V in the non-driving state. The differential voltage is 0 V, and the differential signal is at a low level (recessive).

  For example, when the transmission circuit 2 drives the transmission line 3, the high potential side signal line 3P is driven to, for example, 3.5V or more, the low potential side signal line 3N is driven to, for example, 1.5V or less, and the differential voltage is 2V or more. Thus, the differential signal becomes high level (dominant). Although not shown, both ends of the high-potential side signal line 3P and the low-potential side signal line 3N are terminated by 120Ω resistive elements. Therefore, when the differential signal level changes from high to low, the transmission line 3 is in a non-driven state and the impedance of the transmission line 3 is increased, so that ringing occurs in the differential signal waveform.

  FIG. 2 shows (a) the gate potential of each of the MOSFETs 4, 5 and 9 when the differential signal level changes from high to low, that is, the on / off state. When the differential signal level is high, (c) since the N-channel MOSFET 9 is on, the N-channel MOSFET 5 is off. (B) Since the source-reference gate potential (negative potential) of the P-channel MOSFET 4 is equal to the charging voltage of the capacitor 6, the P-channel MOSFET 4 is on.

  From this state, (a) when the differential signal level changes from high to low, (c) the N-channel MOSFET 9 is turned off and the N-channel MOSFET 5 is turned on. Then, the high potential side signal line 3P and the low potential side signal line 3N are connected via the on-resistances of the P channel MOSFET 4 and the N channel MOSFET 5, and the impedance is lowered. As a result, energy of waveform distortion generated in the falling period in which the differential signal level changes from high to low is consumed by the on-resistance, and ringing is suppressed.

  (B) Since the charge of the capacitor 6 is discharged through the resistance element 7, the absolute value of the gate-source voltage of the P-channel MOSFET 4 gradually decreases, and turns off when it falls below the threshold value. Therefore, the high-potential side signal line 3P and the low-potential side signal line 3N are connected via their on-resistances only during the strain suppression period in which both the P-channel MOSFET 4 and the N-channel MOSFET 5 are on, and the impedance is reduced. .

  As described above, according to this embodiment, the series circuit of the P-channel MOSFET 4 and the N-channel MOSFET 5 is connected between the pair of signal lines 3P and 3N, and the control circuit 11 changes the level of the differential signal from high to low. When the change is detected, the P-channel MOSFET 4 and the N-channel MOSFET 5 are simultaneously turned on for a certain period. As a result, the impedance between the signal lines 3P and 3N is greatly reduced during the period in which the level of the differential signal transitions, and the distortion energy of the differential signal waveform is absorbed by the on-resistances of the FETs 4 and 5, thereby reliably generating ringing. Can be suppressed.

  The control circuit 11 includes an N-channel MOSFET 9 that inverts and outputs the differential signal level, and a delay circuit 8 that outputs the differential signal level after being delayed for a certain period. The N-channel MOSFET 5 is turned on by turning off, and the delay circuit 8 is constituted by a series circuit of a capacitor 6 and a resistance element 7 connected between the signal lines 3P and 3N, and a common connection point between them is a gate of the P-channel MOSFET 4. To connect to.

  That is, when the differential signal is at a high level, the capacitor 6 is charged and the P-channel MOSFET 4 is on and the N-channel MOSFET 9 is on, so the P-channel MOSFET 5 is off and the level of the differential signal changes to low. Then, the latter is immediately turned on and both FETs 4 and 5 are turned on. If a certain period of time elapses from that point, the P-channel MOSFET 4 is turned off and the ringing suppression operation stops. Therefore, the period during which the ringing suppression operation is effective can be adjusted by the time constant of the delay circuit 8.

(Second embodiment)
FIG. 3 shows a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Hereinafter, different parts will be described. The ringing suppression circuit 12 of the second embodiment is configured such that the on / off states of the P-channel MOSFET 4 and the N-channel MOSFET 5 are opposite to those of the first embodiment.

  In other words, the source of a P-channel MOSFET (inverting circuit, control switching element) 13 instead of the N-channel MOSFET 9 is connected to the high potential side signal line 3P, the gate is connected to the low potential side signal line 3N, and the drain is the gate of the P channel MOSFET 4. And is pulled down to the ground potential via the resistance element 10. The gate of the N-channel MOSFET 5 is connected to the high potential side signal line 3P through the resistance element 7 and is connected to the low potential side signal line 3N through the capacitor 6. The series circuit of the resistance element 7 and the capacitor 6 constitutes a delay circuit 8 '. The delay circuit 8 ′ and the N-channel MOSFET 13 constitute a control circuit (control means) 14.

  Next, the operation of the second embodiment will be described. When the differential signal level is high, the P-channel MOSFET 13 is on, and the P-channel MOSFET 4 is off. Further, since the gate potential of the N-channel MOSFET 5 is equivalent to the charging voltage of the capacitor 6; high level, the N-channel MOSFET 5 is turned on. When the differential signal level changes from high to low from this state, the P-channel MOSFET 13 is turned off and the P-channel MOSFET 4 is turned on. Then, the high potential side signal line 3P and the low potential side signal line 3N are connected via the ON resistances of the P-channel MOSFET 4 and the N-channel MOSFET 5, and the waveform distortion that occurs during the falling period of the differential signal. Energy is consumed by the on-resistance, and ringing is suppressed.

  And since the charge of the capacitor 6 is discharged through the resistance element 7, the gate potential of the N-channel MOSFET 5 gradually decreases and turns off when it falls below the threshold value. Therefore, the high-potential side signal line 3P and the low-potential side signal line 3N are connected via their on-resistance only during the period when both the P-channel MOSFET 4 and the N-channel MOSFET 5 are on, as in the first embodiment. Is done.

  As described above, according to the second embodiment, the inverting circuit has a source P connected to the high potential side signal line 3P, a drain pulled down via the resistance element 10, and connected to the gate of the P-channel MOSFET 4. The channel MOSFET 13 is configured, and the gate of the P channel MOSFET 13 is connected to the low potential side signal line 3N. As a result, the inverted signal of the differential signal level is output to the drain of the P-channel MOSFET 13, that is, to the gate of the P-channel MOSFET 4, so that the same effect as in the first embodiment can be obtained.

(Third embodiment)
FIG. 4 shows a third embodiment, and the differences from the first embodiment will be described. The ringing suppression circuit 15 of the third embodiment forms a delay circuit 17 by connecting a diode 16 to the resistance element 7 in parallel in the ringing suppression circuit 1 of the first embodiment. Further, the gate of the N-channel MOSFET 9 is connected to the high potential side signal line 3P via the resistor element 18 and is connected to the low potential side signal line 3N via the capacitor 19, and the diode 20 is connected in parallel to the resistor element 18. Connected.

  Here, the N-channel MOSFET 9, the resistance elements 10 and 18, the capacitor 19, and the diode 20 constitute an inverting circuit 21. The diode 16 is connected so that the anode is on the high potential side signal line 3P side, and the diode 20 is connected so that the anode is on the low potential side signal line 3N side. The delay circuit 17 and the inverting circuit 21 constitute a control circuit (control means) 22.

  Next, the operation of the third embodiment will be described. In the configuration of the first embodiment, when overshoot occurs after the signal waveform falls when the differential signal level changes from high to low, the N-channel MOSFET 9 is turned on and the N-channel MOSFET 5 is turned off. It is assumed that the suppression effect is reduced. Therefore, the gate of the N-channel MOSFET 9 is not directly connected to the high potential side signal line 3P, but is connected to the common connection point of the resistance element 18 and the capacitor 19.

  As a result, when the differential signal level changes from low to high, the capacitor 19 is charged through the resistance element 18, so that the gate potential rises slowly and the differential signal level changes from high to low. In this case, the capacitor 19 is rapidly discharged through the diode 20. Therefore, the ringing of the differential signal is immediately suppressed so that ringing is suppressed, and the ON state of the P-channel MOSFET 4 and the N-channel MOSFET 5 is maintained as much as possible even if an overshoot occurs after the falling. In this way, the ringing suppression action is continued.

  When the differential signal level changes from low to high due to the action of the delay circuit 17, the capacitor 6 is charged via the diode 16 during a period in which the terminal voltage of the resistance element 7 is equal to or higher than the forward voltage. When the charging of the capacitor 6 progresses rapidly and the terminal voltage becomes less than the forward voltage, the charging current flows through the resistance element 7 and the charging becomes slow. Therefore, the given delay time is slightly shorter than in the first embodiment.

  As described above, according to the third embodiment, the inverting circuit 21 includes the series circuit of the resistor element 18 and the capacitor 19 connected between the high potential side signal line 3P and the low potential side signal line 3N, and N The gate of the channel MOSFET 9 was connected to the common connection point of the series circuit. Therefore, when an overshoot occurs after the differential signal waveform falls, it is possible to suppress the N-channel MOSFET 9 from turning on following the overshoot and prevent the N-channel MOSFET 5 from being turned off temporarily.

  Also, since the diode 20 is connected in parallel to the resistance element 18 in such a direction that the anode is on the low potential side signal line 3N side, even when a series circuit that delays the follow-up operation against the occurrence of overshoot is provided, the differential signal level Can be rapidly inverted when the signal goes from high to low. In addition, the delay time provided can be adjusted by connecting the diode 16 in parallel to the resistance element 7 constituting the delay circuit 17.

(Fourth embodiment)
FIG. 5 shows the fourth embodiment, and the differences from the second or third embodiment will be described. The ringing suppression circuit 23 of the fourth embodiment has a configuration in which a delay circuit is added to the ringing suppression circuit 12 of the second embodiment as in the third embodiment. That is, the diode 16 is connected to both ends of the resistance element 7 in the same direction as in the third embodiment to constitute a delay circuit 17 ′. Further, in the delay circuit 21 of the third embodiment, a circuit in which the order of connection of the resistor element 16 and the capacitor 17 is reversed constitutes a delay circuit 21 ′, and the common connection point between the two is connected to the gate of the P-channel MOSFET 13. It is connected. The delay circuit 17 ′ and the inverting circuit 21 ′ constitute a control circuit (control means) 22 ′.
According to the fourth embodiment configured as described above, the same effects as those of the third embodiment can be obtained with respect to the configuration of the second embodiment.

(5th Example)
6 to 9 show a fifth embodiment. In the fifth embodiment, the ringing suppression circuit 1 of the first embodiment and the ringing suppression circuit 12 of the second embodiment are connected in parallel between the transmission lines 3, and the ringing suppression circuit 24 is configured. Yes. The ringing suppression circuits 1 and 12 with the same reference numerals are distinguished by attaching (−) to the former code and (+) to the latter code. In this case, the series circuit of the P-channel MOSFET 4 (−) and the N-channel MOSFET 5 (−) corresponds to the first series circuit, and the series circuit of the P-channel MOSFET 4 (+) and the N-channel MOSFET 5 (+) is the first series circuit. Equivalent to. The control circuit 11 of the ringing suppression circuit 1 corresponds to first control means, and the control circuit 14 of the ringing suppression circuit 12 corresponds to second control means.

  By adopting such a configuration, the following effects can be obtained. In the case where the communication node is arranged in each part of the vehicle like the transmission line 3 of the in-vehicle LAN, it is assumed that the ground potentials connected to each communication node are different (ground offset). In the case of the ringing suppression circuit 1, the gate of the P-channel MOSFET 5 is pulled up to the power supply level. Therefore, if the potential of the low potential side signal line 3N rises when the differential signal indicates a high level, that is, if the ground level of the transmitting node is higher than the ground level of the own node, the gate − The potential difference between the sources becomes small, and it becomes difficult for the P-channel MOSFET 5 to be kept on. At this time, however, the ringing suppression circuit 12 does not affect the operation of the N-channel MOSFET 5 that operates with a differential voltage, and the source potential of the P-channel MOSFET 4 whose gate is pulled down to the ground level of its own node increases. Because it is equivalent to, it can work without problems.

  The above relationship is reversed when the ground level of the transmission node is lower than the ground level of its own node, and there is no problem in operation because the potential difference between the gate and the source of the P-channel MOSFET 5 of the ringing suppression circuit 1 becomes large. On the other hand, the P-channel MOSFET 4 of the ringing suppression circuit 11 has a small gate-source potential difference and is difficult to operate. Therefore, by connecting the ringing suppression circuits 1 and 12 in parallel, even when there is a ground offset between the communication nodes, at least one of the ringing suppression circuits 1 and 12 operates reliably. It is definitely obtained.

  7 to 9 show results of simulating the operation of the ringing suppression circuit 24. FIG. FIG. 7 shows a CAN network model used for the simulation. The three junction connectors J / C1, J / C2, and J / C3 are connected by a transmission line of 5 m, and each of the six communication nodes of the junction connectors J / C1 and J / C3 is 2 m. It is connected via a transmission line. A transmission node and a reception node are connected to the junction connector J / C2 via a transmission line of 4 m, respectively, and a ringing suppression circuit 24 is connected to the transmission line on the reception node side.

  FIG. 7A shows a simulation result when there is no offset in the ground level of the transmitting node and the receiving node. When the ringing suppression circuit 24 is connected (solid line; with distortion suppression), when not connected (broken line; distortion) Both without control). FIG. 7A shows voltage waveforms when the differential signal changes from dominant to recessive, and FIG. 7B shows voltage waveforms of the signal lines 3P and 3N (CAN-H, CAN) -L at that time. It is. As shown in FIG. 7A, it can be seen that the vibration of the voltage waveform after the transition to recessive converges more quickly in the case of “with distortion suppression”.

FIG. 8 is a diagram corresponding to FIG. 7 when the ground level of the transmission node is 7.5 V lower than the ground level of the reception node. As shown in FIG. 8B, the voltage waveforms of the signal lines 3P and 3N are − The differential voltage is centered on 5V. FIG. 9 is a diagram corresponding to FIG. 7 when the ground level of the transmitting node is 9.5 V higher than the ground level of the receiving node. As shown in FIG. 9B, the voltage waveforms of the signal lines 3P and 3N are as follows. The differential voltage is centered on 12V. From these results, it can be seen that the ringing suppression circuit 24 operates to suppress ringing even when there is a potential difference in the ground between the communication nodes.
As described above, according to the fifth embodiment, the ringing suppression circuit 24 is configured by connecting the ringing suppression circuits 1 and 12 in parallel between the signal lines 3P and 3N. Therefore, even when there is a difference in the ground potential between the communication nodes, either one can operate reliably, and ringing can be reliably suppressed.

(Sixth embodiment)
10 and 11 show a sixth embodiment. In the sixth embodiment, the ringing suppression circuit 25 is configured by connecting the ringing suppression circuit 15 of the third embodiment and the ringing suppression circuit 23 of the fourth embodiment in parallel between the signal lines 3P and 3N. Each of the ringing suppression circuits 15 and 23 is provided with a countermeasure for suppressing overshoot that occurs after the falling of the differential signal waveform. FIG. 11 shows a simulation result when there is no ground offset. When FIG. 7A is compared with FIG. 11, the peak value of the former overshoot exceeds 3V, while the peak value of the latter is less than 3V. In addition, the amplitude of the ringing waveform is reduced as a whole, and the time for the fluctuation to converge is also shortened, and it can be said that the ringing suppression effect is generally higher.
According to the sixth embodiment configured as described above, since the ringing suppression circuits 15 and 23 are connected in parallel between the signal lines 3P and 3N, a higher ringing suppression effect than that of the fifth embodiment can be obtained. it can.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The ringing suppression circuit may be connected to any one or more of the transmission lines, but may be connected to the vicinity of each communication node.
The first and second line switching elements may be composed of elements of the same conductivity type.
The diode 20 constituting the inverting circuit 21 may be connected as necessary.
The switching element is not limited to a MOSFET but may be a voltage driven element.
The ringing suppression circuit may be configured to suppress ringing that occurs when the differential signal level changes from low to high.
The present invention is not limited to CAN and can be applied to any communication protocol that transmits a differential signal through a pair of signal lines.

  In the drawings, 1 is a ringing suppression circuit, 3 is a transmission line, 3P is a high potential side signal line, 3N is a low potential side signal line, 4 is a P channel MOSFET (first interline switching element), and 5 is an N channel MOSFET ( (Second line switching element), 6 is a capacitor, 7 is a resistance element, 8 is a delay circuit, 9 is an N-channel MOSFET (inversion circuit, control switching element), 10 is a resistance element, and 11 is a control circuit (control means) , 12 is a ringing suppression circuit, 13 is a P-channel MOSFET (inversion circuit, control switching element), 14 is a control circuit (control means), 15 is a ringing suppression circuit, 16 is a diode, 17 is a delay circuit, 20 is a diode, Reference numeral 21 denotes an inverting circuit, 22 denotes a control circuit (control means), and 23 to 25 denote ringing suppression circuits.

Claims (11)

Ringing suppression that suppresses ringing caused by transmission of the signal connected to a transmission line that transmits a differential signal that changes to a binary level of high and low by a pair of high potential side signal line and low potential side signal line In the circuit
A voltage-driven first and second interline switching element connected in series between the pair of signal lines;
And a control means for reducing the impedance between the signal lines by simultaneously turning on the first and second line switching elements for a certain period when detecting that the level of the differential signal has changed. Ringing suppression circuit.
The control means includes an inverting circuit that inverts and outputs the level of the differential signal;
A delay circuit that delays and outputs the level of the differential signal for the predetermined period,
One of the first and second line switching elements is turned on by a signal output from the inverting circuit, and the other of the first and second line switching elements is turned off by a signal output from the delay circuit. The ringing suppression circuit according to claim 1. In the inverting circuit, a potential reference side conduction terminal is connected to one of the pair of signal lines, a control terminal is connected to be in a conduction state when the differential signal indicates a high level, and a non-reference side conduction terminal is A voltage-driven control switching element connected to one control terminal of the line-to-line switching element;
The delay circuit includes a series circuit of a resistor element and a capacitor connected between the pair of signal lines, and a common connection point of the resistor element and the capacitor is connected to the other control terminal of the line-to-line switching element. The ringing suppression circuit according to claim 2, wherein: The control switching element is composed of an N-channel MOSFET having a source connected to the low potential signal line, a drain pulled up via a resistor and connected to a control terminal of the line switching element,
4. The ringing suppression circuit according to claim 3, wherein the gate of the N-channel MOSFET is connected to the high potential side signal line. The control switching element is composed of an N-channel MOSFET having a source connected to the low potential signal line, a drain pulled up via a resistor and connected to a control terminal of the line switching element,
The inversion circuit includes a series circuit of a resistance element and a capacitor connected between the high potential side signal line and the low potential side signal line,
4. The ringing suppression circuit according to claim 3, wherein a gate of the N-channel MOSFET is connected to a common connection point of the series circuit.   6. The ringing suppression circuit according to claim 5, wherein the inverting circuit includes a diode connected in parallel to the resistance element in a direction in which an anode faces the low potential side signal line. The control switching element is configured by a P-channel MOSFET having a source connected to the high potential side signal line, a drain pulled down via a resistor, and connected to a control terminal of the line switching element,
4. The ringing suppression circuit according to claim 3, wherein a gate of the P-channel MOSFET is connected to the low potential side signal line. The control switching element is configured by a P-channel MOSFET having a source connected to the high potential side signal line, a drain pulled down via a resistor, and connected to a control terminal of the line switching element,
The inversion circuit includes a series circuit of a capacitor and a resistance element connected between the high potential side signal line and the low potential side signal line,
4. The ringing suppression circuit according to claim 3, wherein a gate of the P-channel MOSFET is connected to a common connection point of the series circuit.   9. The ringing suppression circuit according to claim 8, wherein the inverting circuit includes a diode connected in parallel to the resistance element in a direction in which an anode faces the low potential side signal line. Each of the first and second line-to-line switching elements is composed of switching elements of different conductivity types,
When two sets of series circuits of the first and second line switching elements are connected in parallel between the pair of signal lines, one of them is a first series circuit and the other is a second series circuit.
The control means includes two sets of a first control means for controlling the first series circuit and a second control means for controlling the second series circuit,
The first and second control switching elements constituting the first and second control means are connected to different control terminals, potential reference side conduction terminals, and the pair of signal lines having different conductive relationships. Composed of mold elements,
The non-reference-side conduction terminals of the first and second control switching elements are respectively pulled up or pulled down via resistance elements, and the same conductive type line switching elements in the first and second series circuits. Connected to the control terminal,
4. The series circuit constituting the delay circuit, wherein a resistance element is connected to a common signal line side with a reference potential side conduction terminal of each of the first and second control switching elements. 10. The ringing suppression circuit according to any one of 9 above.   The first and second line switching elements are composed of a P-channel MOSFET and an N-channel MOSFET, the drains of which are connected in common, and the sources of which are respectively connected to the high potential side signal line and the low potential side signal line. 11. The ringing suppression circuit according to claim 1, wherein the ringing suppression circuit is any one of claims 1 to 10.

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