JP2006019497A - Semiconductor device, and method for manufacturing the same - Google Patents

Semiconductor device, and method for manufacturing the same Download PDF

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JP2006019497A
JP2006019497A JP2004195608A JP2004195608A JP2006019497A JP 2006019497 A JP2006019497 A JP 2006019497A JP 2004195608 A JP2004195608 A JP 2004195608A JP 2004195608 A JP2004195608 A JP 2004195608A JP 2006019497 A JP2006019497 A JP 2006019497A
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electrode
semiconductor device
resin layer
passivation film
conductive
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Katsuhiko Oguchi
勝彦 小口
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device high in reliability, and to provide a method for manufacturing the same. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate 8 having an integrated circuit 10 and an electrode 12; a passivation film 14, formed on the surface of the semiconductor substrate 8 mounted with the electrode 12, covering a part of the electrode 12 with other parts thereof left exposed; a resin layer 16 overlapping the electrode 12 but designed to be clear from at least a part of the electrode 12 left exposed from the passivation film 14; and an external terminal 20, contacting with the part of the electrode 12 left exposed from the passivation film 14 and from the resin 16, and mounted on the resin layer 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

半導体装置のパッケージとして、ＣＳＰ（チップスケール／サイズパッケージ）の普及率が高まってきている。また、パッケージをウエハレベルで製造する技術（ウエハレベルパッケージ）が開発されている。例えば、特許文献１は、電極から、追加して設けた応力緩和層の上に再配置配線を引き出して、再配置配線の上に外部端子（ハンダボール等）を形成している。
特開２００３−２８２７９０号公報 The spread rate of CSP (chip scale / size package) is increasing as a package of a semiconductor device. In addition, a technique for manufacturing a package at a wafer level (wafer level package) has been developed. For example, in Patent Document 1, a rearrangement wiring is drawn out from an electrode on an additionally provided stress relaxation layer, and an external terminal (solder ball or the like) is formed on the rearrangement wiring.
JP 2003-282790 A

この方法で製造されたパッケージ（例えばウエハレベルＣＳＰ）は、外部寸法が半導体チップ寸法になっているため、従来のパッケージとは構造が異なっているが、従来のパッケージと同等又はそれ以上の信頼性が要求されている。   A package manufactured by this method (for example, wafer level CSP) has a structure different from that of the conventional package because the external dimension is the size of the semiconductor chip, but the reliability is equal to or higher than that of the conventional package. Is required.

本発明の目的は、信頼性の高い半導体装置及びその製造方法を提供することにある。   An object of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof.

（１）本発明に係る半導体装置は、集積回路と電極とを有する半導体基板と、
前記半導体基板の前記電極が形成された面に、前記電極の一部を覆うとともに他の部分を露出させるように形成されてなるパッシベーション膜と、
前記電極とオーバーラップし、かつ、前記電極の前記パッシベーション膜からの露出部の少なくとも一部を避けるように形成されてなる樹脂層と、
前記電極の前記パッシベーション膜及び前記樹脂層からの露出部と接触し、かつ、前記樹脂層に載るように形成されてなる外部端子と、
を有する。本発明によれば、電極上に、外部端子に生じる応力を分散させる樹脂層があるので、電極上に外部端子を形成することが可能となり、電極数と同等数の外部端子を形成することができる。また、再配置配線を引き回す必要がなくなり、構造的にシンプルになる半導体装置を提供することができる。
（２）この半導体装置において、
前記樹脂層は、前記電極に接触する部分と、前記パッシベーション膜に接触する部分と、を含んでもよい。
（３）この半導体装置において、
前記樹脂層は、前記パッシベーション膜に接触しないように形成されてもよい。
（４）この半導体装置において、
前記樹脂層は、前記電極に接触しないように形成されてもよい。
（５）この半導体装置において、
前記パッシベーション膜は、前記電極の周縁部を覆う部分と、前記電極の中央部の一部を覆う部分と、を含んでもよい。
（６）この半導体装置において、
前記外部端子は、前記電極の一部、前記パッシベーション膜の一部及び前記樹脂層の少なくとも一部に接触する導電層と、前記導電層とは異なる材料で前記導電層上に形成されてなる導電部と、を含んでもよい。
（７）この半導体装置の製造方法において、集積回路と電極とを有する半導体基板の前記電極が形成された面に、前記電極の一部を覆うとともに他の部分を露出させるようにパッシベーション膜を形成すること、
前記電極とオーバーラップし、かつ、前記電極の前記パッシベーション膜からの露出部の少なくとも一部を避けるように樹脂層を形成すること、
前記電極の一部、前記パッシベーション膜の一部及び前記樹脂層の少なくとも一部に接触するように導電層を形成すること、及び、
前記導電層とは異なる材料で前記導電層上に導電部を形成すること、
を含む。本発明によれば、電極上に、外部端子に生じる応力を分散させる樹脂層を設けるので、電極上に外部端子を形成することが可能となり、電極数と同等数の外部端子を形成することができる。また、再配置配線を引き回す必要がなくなり、構造的にシンプルになる半導体装置の製造方法を提供することができる。 (1) A semiconductor device according to the present invention includes a semiconductor substrate having an integrated circuit and electrodes,
A passivation film formed on the surface of the semiconductor substrate on which the electrode is formed so as to cover a part of the electrode and expose the other part;
A resin layer that overlaps with the electrode and is formed so as to avoid at least part of the exposed portion of the electrode from the passivation film;
An external terminal formed so as to be in contact with the passivation film of the electrode and the exposed portion from the resin layer and to be placed on the resin layer;
Have According to the present invention, since there is a resin layer on the electrode that disperses the stress generated in the external terminal, it is possible to form the external terminal on the electrode, and it is possible to form the same number of external terminals as the number of electrodes. it can. Further, it is not necessary to route the rearrangement wiring, and a semiconductor device that is structurally simple can be provided.
(2) In this semiconductor device,
The resin layer may include a portion in contact with the electrode and a portion in contact with the passivation film.
(3) In this semiconductor device,
The resin layer may be formed so as not to contact the passivation film.
(4) In this semiconductor device,
The resin layer may be formed so as not to contact the electrode.
(5) In this semiconductor device,
The passivation film may include a portion that covers a peripheral portion of the electrode and a portion that covers a part of the central portion of the electrode.
(6) In this semiconductor device,
The external terminal includes a conductive layer in contact with at least a part of the electrode, a part of the passivation film, and the resin layer, and a conductive material formed on the conductive layer using a material different from the conductive layer. May be included.
(7) In this method of manufacturing a semiconductor device, a passivation film is formed on a surface of the semiconductor substrate having an integrated circuit and an electrode so as to cover a part of the electrode and expose the other part. To do,
Forming a resin layer so as to overlap with the electrode and avoid at least part of the exposed portion of the electrode from the passivation film;
Forming a conductive layer so as to contact a part of the electrode, a part of the passivation film, and at least a part of the resin layer; and
Forming a conductive portion on the conductive layer with a material different from the conductive layer;
including. According to the present invention, since the resin layer that disperses the stress generated in the external terminal is provided on the electrode, the external terminal can be formed on the electrode, and the number of external terminals equal to the number of electrodes can be formed. it can. Also, it is possible to provide a method for manufacturing a semiconductor device that eliminates the need for routing rearranged wiring and is structurally simple.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施の形態に係る半導体装置の断面図である。図２は、図１に示す半導体装置の一部（導電層２２及び導電部２４）を除外した平面図である。   FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view excluding a part of the semiconductor device (conductive layer 22 and conductive portion 24) shown in FIG.

本実施の形態に係る半導体装置は、半導体基板８を有する。半導体基板８は、半導体チップであってもよいし、半導体ウエハであってもよい。半導体基板８には、１つ又は複数の集積回路１０が形成されている。半導体チップには、１つの集積回路１０が形成され、半導体ウエハには、複数の集積回路１０が形成されている。半導体基板８には、複数の電極（例えばパッド）１２が形成されている。電極１２は、例えばＡｌで形成されている。電極１２の平面形状は矩形であり、正方形であっても長方形であってもよい。半導体基板８の表面（電極１２が形成された面）には、電極１２の一部を覆うとともに他の部分を露出させるようにパッシベーション膜１４が形成されている。パッシベーション膜１４は、電極１２の周縁部を覆う部分と、電極１２の中央部の一部を覆う部分と、を含んでもよい。パッシベーション膜１４は、電極１２の中央部を避けて周縁部を覆う部分のみからなってもよい。パッシベーション膜１４は、ＳｉＮ，ＳｉＯ２，ＭｇＯなどから形成されている。 The semiconductor device according to the present embodiment has a semiconductor substrate 8. The semiconductor substrate 8 may be a semiconductor chip or a semiconductor wafer. One or a plurality of integrated circuits 10 are formed on the semiconductor substrate 8. One integrated circuit 10 is formed on the semiconductor chip, and a plurality of integrated circuits 10 are formed on the semiconductor wafer. A plurality of electrodes (for example, pads) 12 are formed on the semiconductor substrate 8. The electrode 12 is made of, for example, Al. The planar shape of the electrode 12 is rectangular, and may be square or rectangular. A passivation film 14 is formed on the surface of the semiconductor substrate 8 (the surface on which the electrode 12 is formed) so as to cover a part of the electrode 12 and expose the other part. The passivation film 14 may include a portion that covers the peripheral edge portion of the electrode 12 and a portion that covers a part of the central portion of the electrode 12. The passivation film 14 may consist only of a portion that covers the peripheral edge portion while avoiding the central portion of the electrode 12. The passivation film 14 is made of SiN, SiO 2 , MgO or the like.

本実施の形態に係る半導体装置は、樹脂層１６を有する。樹脂層１６は、電極１２とオーバーラップし、かつ、電極１２のパッシベーション膜１４からの露出部の少なくとも一部を避けるように形成されている。樹脂層１６は、電極１２に接触する部分と、パッシベーション膜１４に接触する部分と、を含んでもよい。樹脂層１６は、感光性レジストにより形成してもよい。樹脂層１６は、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）等の樹脂で形成することができる。   The semiconductor device according to the present embodiment has a resin layer 16. The resin layer 16 is formed so as to overlap with the electrode 12 and to avoid at least a part of the exposed portion of the electrode 12 from the passivation film 14. The resin layer 16 may include a portion that contacts the electrode 12 and a portion that contacts the passivation film 14. The resin layer 16 may be formed of a photosensitive resist. The resin layer 16 can be formed of a resin such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO).

本実施の形態に係る半導体装置は、複数の外部端子２０を有する。外部端子２０は、電極１２のパッシベーション膜１４及び樹脂層１６からの露出部と接触し、かつ、樹脂層１６に載るように形成されている。こうすることで、外部端子２０に生じる応力が樹脂層１６により分散されるので、電極１２上に外部端子２０を形成することが可能となり、電極１２数と同等数の外部端子２０を形成することができる。外部端子２０は、電極１２の一部、パッシベーション膜１４の一部及び樹脂層１６の少なくとも一部に接触する導電層２２と、導電層２２とは異なる材料で導電層２２上に形成されてなる導電部２４と、を含んでもよい。導電部２４は、導電性を有する金属（例えば合金）であって、溶融させて電気的な接続を図るためのもの（例えばハンダ）である。導電部２４は、軟ろう（soft solder）又は硬ろう（hard solder）のいずれで形成されてもよい。導電部２４は、球状をなしていてもよく、例えばハンダボールであってもよい。   The semiconductor device according to the present embodiment has a plurality of external terminals 20. The external terminal 20 is formed so as to be in contact with the passivation film 14 of the electrode 12 and the exposed portion from the resin layer 16 and to be placed on the resin layer 16. By doing so, since the stress generated in the external terminal 20 is dispersed by the resin layer 16, the external terminal 20 can be formed on the electrode 12, and the number of external terminals 20 equal to the number of electrodes 12 can be formed. Can do. The external terminal 20 is formed on the conductive layer 22 using a material different from the conductive layer 22 and a conductive layer 22 that contacts a part of the electrode 12, a part of the passivation film 14, and at least a part of the resin layer 16. The conductive portion 24 may be included. The conductive portion 24 is a conductive metal (for example, an alloy) and is used for melting and achieving electrical connection (for example, solder). The conductive portion 24 may be formed of either soft solder or hard solder. The conductive portion 24 may have a spherical shape, for example, a solder ball.

本実施の形態に係る半導体装置は、上述のように構成されており、以下その製造方法を説明する。本実施の形態では、集積回路１０と電極１２とを有する半導体基板８の電極１２が形成された面に、電極１２の一部を覆うとともに他の部分を露出させるようにパッシベーション膜１４を形成する。   The semiconductor device according to the present embodiment is configured as described above, and the manufacturing method thereof will be described below. In the present embodiment, the passivation film 14 is formed on the surface of the semiconductor substrate 8 having the integrated circuit 10 and the electrode 12 where the electrode 12 is formed so as to cover a part of the electrode 12 and expose the other part. .

樹脂層１６を電極１２とオーバーラップし、かつ、電極１２のパッシベーション膜１４からの露出部の少なくとも一部を避けるように形成する。樹脂層１６の形成プロセスは、半導体基板８に樹脂前駆体（例えば、熱硬化性樹脂前駆体）を塗布すること、あるいは、半導体基板８上で樹脂前駆体をスピンコートによって広げて、樹脂前駆体層を形成することを含んでもよい。放射線（光線（紫外線、可視光線）、Ｘ線、電子線）に感応する性質を有する放射線感応性樹脂前駆体を使用して、連続的又は一体的な樹脂前駆体層を形成し、これを樹脂層１６にパターニングしてもよい。パターニングにはリソグラフィを適用する。あるいは、印刷（例えば、スクリーン印刷）によって、樹脂層１６を形成してもよい。樹脂層１６は、複数層になるように形成してもよいし、１層になるように形成してもよい。樹脂層１６は、電極１２に接触する部分と、パッシベーション膜１４に接触する部分と、を含んでもよい。樹脂層１６は、感光性レジストにより形成してもよい。   The resin layer 16 is formed so as to overlap the electrode 12 and to avoid at least a part of the exposed portion of the electrode 12 from the passivation film 14. The resin layer 16 is formed by applying a resin precursor (for example, a thermosetting resin precursor) to the semiconductor substrate 8 or by spreading the resin precursor on the semiconductor substrate 8 by spin coating. It may also include forming a layer. Using a radiation-sensitive resin precursor having properties sensitive to radiation (light rays (ultraviolet rays, visible rays), X-rays, electron beams), a continuous or integral resin precursor layer is formed, and this is used as a resin. The layer 16 may be patterned. Lithography is applied for patterning. Alternatively, the resin layer 16 may be formed by printing (for example, screen printing). The resin layer 16 may be formed to have a plurality of layers or may be formed to have a single layer. The resin layer 16 may include a portion that contacts the electrode 12 and a portion that contacts the passivation film 14. The resin layer 16 may be formed of a photosensitive resist.

外部端子２０を電極１２のパッシベーション膜１４及び樹脂層１６からの露出部と接触し、かつ、樹脂層１６に載るように形成する。こうすることで、外部端子２０に生じる応力が樹脂層１６により分散されるので、電極１２上に外部端子２０を形成することが可能となり、電極１２数と同等数の外部端子２０を形成することができる。外部端子２０は、電極１２の一部、パッシベーション膜１４の一部及び樹脂層１６の少なくとも一部に接触する導電層２２と、導電層２２とは異なる材料で導電層２２上に形成されてなる導電部２４と、を含んでもよい。導電部２４は、導電性を有する金属（例えば合金）であって、溶融させて電気的な接続を図るためのもの（例えばハンダ）である。導電部２４は、軟ろう（soft solder）又は硬ろう（hard solder）のいずれで形成されてもよい。導電部２４は、球状をなしていてもよく、例えばハンダボールであってもよい。   The external terminal 20 is formed so as to be in contact with the passivation film 14 of the electrode 12 and the exposed portion from the resin layer 16 and to be placed on the resin layer 16. By doing so, since the stress generated in the external terminal 20 is dispersed by the resin layer 16, the external terminal 20 can be formed on the electrode 12, and the number of external terminals 20 equal to the number of electrodes 12 can be formed. Can do. The external terminal 20 is formed on the conductive layer 22 using a material different from the conductive layer 22 and a conductive layer 22 that contacts a part of the electrode 12, a part of the passivation film 14, and at least a part of the resin layer 16. The conductive portion 24 may be included. The conductive portion 24 is a conductive metal (for example, an alloy) and is used for melting and achieving electrical connection (for example, solder). The conductive portion 24 may be formed of either soft solder or hard solder. The conductive portion 24 may have a spherical shape, for example, a solder ball.

また、集積回路１０とオーバーラップする位置にも樹脂層１６を形成してもよい。このとき、集積回路１０とオーバーラップし、かつ集積回路１０とオーバーラップする位置の樹脂層１６上に形成された外部端子、及び該外部端子と電極（例えばパッド）を電気的に接続する配線を更に有してもよい。   Further, the resin layer 16 may be formed at a position overlapping the integrated circuit 10. At this time, an external terminal formed on the resin layer 16 at a position overlapping with the integrated circuit 10 and overlapping with the integrated circuit 10 and wiring for electrically connecting the external terminal and an electrode (for example, a pad) are provided. Furthermore, you may have.

半導体基板８が半導体ウエハである場合、半導体基板８を、集積回路１０ごとに、図示しない、例えばブレードによって切断する。半導体基板８を切断して複数の半導体装置が得られる。これによれば、ウエハ単位でパッケージングがなされる。   When the semiconductor substrate 8 is a semiconductor wafer, the semiconductor substrate 8 is cut for each integrated circuit 10 by, for example, a blade (not shown). The semiconductor substrate 8 is cut to obtain a plurality of semiconductor devices. According to this, packaging is performed in units of wafers.

（変形例）
図３、図５は、本発明の実施の形態の変形例に係る半導体装置の断面図である。図４は、図３に示す半導体装置の一部（導電層３２及び導電部３４）を除外した平面図である。図６は、図５に示す半導体装置の一部（導電層４２、導電部４４及びソルダーレジスト４６）を除外した平面図である。図７は、本発明の実施の形態の変形例に係る半導体装置の一部を除外した平面図である。 (Modification)
3 and 5 are cross-sectional views of a semiconductor device according to a modification of the embodiment of the present invention. FIG. 4 is a plan view excluding a part of the semiconductor device (conductive layer 32 and conductive part 34) shown in FIG. FIG. 6 is a plan view excluding a part of the semiconductor device shown in FIG. 5 (conductive layer 42, conductive portion 44, and solder resist 46). FIG. 7 is a plan view excluding a part of a semiconductor device according to a modification of the embodiment of the present invention.

図３、図４に示す例では、半導体装置２の樹脂層２６は、パッシベーション膜１４に接触しないように形成されてもよい。その他の構成については、上記実施の形態で説明した内容を適用することができる。図３、図４に示す半導体装置の製造方法には、上記実施の形態で説明した事項を適用することができる。ただし、外部端子３０は、電極１２の一部、パッシベーション膜１４の一部及び樹脂層２６の少なくとも一部に接触する導電層３２と、導電層３２とは異なる材料で導電層３２上に形成されてなる導電部３４と、を含んでもよい。   In the example shown in FIGS. 3 and 4, the resin layer 26 of the semiconductor device 2 may be formed so as not to contact the passivation film 14. The contents described in the above embodiment can be applied to other configurations. The items described in the above embodiments can be applied to the method for manufacturing the semiconductor device illustrated in FIGS. However, the external terminal 30 is formed on the conductive layer 32 using a material different from the conductive layer 32 and the conductive layer 32 that contacts a part of the electrode 12, a part of the passivation film 14, and at least a part of the resin layer 26. And a conductive portion 34.

図５、図６に示す例では、半導体装置４の樹脂層３６は、電極１２に接触しないように形成されてもよい。その他の構成については、上記実施の形態で説明した内容を適用することができる。図５、図６に示す半導体装置の製造方法には、上記実施の形態で説明した事項を適用することができる。ただし、外部端子４０は、電極１２の一部、パッシベーション膜１４の一部及び樹脂層３６の少なくとも一部に接触する導電層４２と、導電層４２とは異なる材料で導電層４２上に形成されてなる導電部４４と、を含んでもよい。   In the example shown in FIGS. 5 and 6, the resin layer 36 of the semiconductor device 4 may be formed so as not to contact the electrode 12. The contents described in the above embodiment can be applied to other configurations. The items described in the above embodiments can be applied to the method for manufacturing the semiconductor device illustrated in FIGS. However, the external terminal 40 is formed on the conductive layer 42 with a conductive layer 42 that contacts a part of the electrode 12, a part of the passivation film 14, and at least a part of the resin layer 36, and a material different from the conductive layer 42. And a conductive portion 44.

図７に示す例では、電極５２の平面形状は円形であり、楕円であっても真円であってもよい。その他の構成については、上記実施の形態で説明した内容を適用することができる。図７に示す半導体装置の製造方法には、上記実施の形態で説明した事項を適用することができる。ただし、樹脂層５６は、電極５２とオーバーラップし、かつ、電極５２のパッシベーション膜５４からの露出部の少なくとも一部を避けるように形成されている。   In the example shown in FIG. 7, the planar shape of the electrode 52 is circular, and may be an ellipse or a perfect circle. The contents described in the above embodiment can be applied to other configurations. The matters described in the above embodiments can be applied to the method for manufacturing the semiconductor device illustrated in FIG. However, the resin layer 56 is formed so as to overlap with the electrode 52 and to avoid at least a part of the exposed portion of the electrode 52 from the passivation film 54.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。さらに、本発明は、実施の形態で説明した技術的事項のいずれかを限定的に除外した内容を含む。あるいは、本発明は、上述した実施の形態から公知技術を限定的に除外した内容を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment. Furthermore, the present invention includes contents that exclude any of the technical matters described in the embodiments in a limited manner. Or this invention includes the content which excluded the well-known technique limitedly from embodiment mentioned above.

本発明の実施の形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. 図１に示す半導体装置の一部を除外した平面図である。FIG. 2 is a plan view excluding a part of the semiconductor device shown in FIG. 1. 本発明の実施の形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on embodiment of this invention. 図３に示す半導体装置の一部を除外した平面図である。FIG. 4 is a plan view excluding a part of the semiconductor device shown in FIG. 3. 本発明の実施の形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on embodiment of this invention. 図５に示す半導体装置の一部を除外した平面図である。FIG. 6 is a plan view excluding a part of the semiconductor device shown in FIG. 5. 本発明の実施の形態に係る半導体装置の変形例を示す一部を除外した平面図である。It is the top view which excluded a part which shows the modification of the semiconductor device which concerns on embodiment of this invention.

符号の説明Explanation of symbols

２…半導体装置 ４…半導体装置 ８…半導体基板 １０…集積回路 １２…電極 １４…パッシベーション膜 １６…樹脂層 ２０…外部端子 ２２…導電層 ２４…導電部 ２６…樹脂層 ３０…外部端子 ３２…導電層 ３４…導電部 ３６…樹脂層 ４０…外部端子 ４２…導電層 ４４…導電部 ４６…ソルダーレジスト ５２…電極 ５４…パッシベーション膜 ５６…樹脂層 DESCRIPTION OF SYMBOLS 2 ... Semiconductor device 4 ... Semiconductor device 8 ... Semiconductor substrate 10 ... Integrated circuit 12 ... Electrode 14 ... Passivation film 16 ... Resin layer 20 ... External terminal 22 ... Conductive layer 24 ... Conductive part 26 ... Resin layer 30 ... External terminal 32 ... Conductive Layer 34 ... conductive portion 36 ... resin layer 40 ... external terminal 42 ... conductive layer 44 ... conductive portion 46 ... solder resist 52 ... electrode 54 ... passivation film 56 ... resin layer

Claims (7)

集積回路と電極とを有する半導体基板と、
前記半導体基板の前記電極が形成された面に、前記電極の一部を覆うとともに他の部分を露出させるように形成されてなるパッシベーション膜と、
前記電極とオーバーラップし、かつ、前記電極の前記パッシベーション膜からの露出部の少なくとも一部を避けるように形成されてなる樹脂層と、
前記電極の前記パッシベーション膜及び前記樹脂層からの露出部と接触し、かつ、前記樹脂層に載るように形成されてなる外部端子と、
を有する半導体装置。 A semiconductor substrate having an integrated circuit and an electrode;
A passivation film formed on the surface of the semiconductor substrate on which the electrode is formed so as to cover a part of the electrode and expose the other part;
A resin layer that overlaps with the electrode and is formed so as to avoid at least part of the exposed portion of the electrode from the passivation film;
An external terminal formed so as to be in contact with the passivation film of the electrode and the exposed portion from the resin layer and to be placed on the resin layer;
A semiconductor device. 請求項１記載の半導体装置において、
前記樹脂層は、前記電極に接触する部分と、前記パッシベーション膜に接触する部分と、を含む半導体装置。 The semiconductor device according to claim 1,
The said resin layer is a semiconductor device containing the part which contacts the said electrode, and the part which contacts the said passivation film. 請求項１記載の半導体装置において、
前記樹脂層は、前記パッシベーション膜に接触しないように形成されてなる半導体装置。 The semiconductor device according to claim 1,
The resin layer is a semiconductor device formed so as not to contact the passivation film. 請求項１記載の半導体装置において、
前記樹脂層は、前記電極に接触しないように形成されてなる半導体装置。 The semiconductor device according to claim 1,
The resin layer is a semiconductor device formed so as not to contact the electrode. 請求項１から請求項４のいずれかに記載の半導体装置において、
前記パッシベーション膜は、前記電極の周縁部を覆う部分と、前記電極の中央部の一部を覆う部分と、を含む半導体装置。 The semiconductor device according to any one of claims 1 to 4,
The said passivation film is a semiconductor device containing the part which covers the peripheral part of the said electrode, and the part which covers a part of center part of the said electrode. 請求項１から請求項５のいずれかに記載の半導体装置において、
前記外部端子は、前記電極の一部、前記パッシベーション膜の一部及び前記樹脂層の少なくとも一部に接触する導電層と、前記導電層とは異なる材料で前記導電層上に形成されてなる導電部と、を含む半導体装置。 The semiconductor device according to any one of claims 1 to 5,
The external terminal includes a conductive layer in contact with at least a part of the electrode, a part of the passivation film, and the resin layer, and a conductive material formed on the conductive layer using a material different from the conductive layer. A semiconductor device. 集積回路と電極とを有する半導体基板の前記電極が形成された面に、前記電極の一部を覆うとともに他の部分を露出させるようにパッシベーション膜を形成すること、
前記電極とオーバーラップし、かつ、前記電極の前記パッシベーション膜からの露出部の少なくとも一部を避けるように樹脂層を形成すること、
前記電極の一部、前記パッシベーション膜の一部及び前記樹脂層の少なくとも一部に接触するように導電層を形成すること、及び、
前記導電層とは異なる材料で前記導電層上に導電部を形成すること、
を含む半導体装置の製造方法。 Forming a passivation film on a surface of the semiconductor substrate having an integrated circuit and an electrode on which the electrode is formed so as to cover a part of the electrode and expose the other part;
Forming a resin layer so as to overlap with the electrode and avoid at least part of the exposed portion of the electrode from the passivation film;
Forming a conductive layer so as to contact a part of the electrode, a part of the passivation film, and at least a part of the resin layer; and
Forming a conductive portion on the conductive layer with a material different from the conductive layer;
A method of manufacturing a semiconductor device including:
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273547A (en) * 2006-03-30 2007-10-18 Nec Corp Semiconductor element and semiconductor device
JP2008091632A (en) * 2006-10-02 2008-04-17 Manabu Bonshihara Structure of external circuit connection section in semiconductor device and method of forming the same
WO2008142839A1 (en) * 2007-05-11 2008-11-27 Panasonic Corporation Semiconductor chip and semiconductor device
FR2959868A1 (en) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 SEMICONDUCTOR DEVICE HAVING CONNECTING PLATES WITH INSERTS

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273547A (en) * 2006-03-30 2007-10-18 Nec Corp Semiconductor element and semiconductor device
JP2008091632A (en) * 2006-10-02 2008-04-17 Manabu Bonshihara Structure of external circuit connection section in semiconductor device and method of forming the same
WO2008047585A1 (en) * 2006-10-02 2008-04-24 Manabu Bonkohara Semiconductor device external circuit connection unit structure and its formation method
WO2008142839A1 (en) * 2007-05-11 2008-11-27 Panasonic Corporation Semiconductor chip and semiconductor device
US7994638B2 (en) 2007-05-11 2011-08-09 Panasonic Corporation Semiconductor chip and semiconductor device
JP5052605B2 (en) * 2007-05-11 2012-10-17 パナソニック株式会社 Semiconductor chip
FR2959868A1 (en) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 SEMICONDUCTOR DEVICE HAVING CONNECTING PLATES WITH INSERTS

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