JP2004172163A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor device for alleviating stress on the mounting substrate and external terminal and for solving the missing failure of post electrode. <P>SOLUTION: The semiconductor device comprises: a semiconductor substrate (10); an element electrode (11) formed on the semiconductor substrate surface; an insulating resin layer (12) having an aperture; metal wirings (13, 15) including an external terminal forming land (21) which is continuously formed over the insulating resin layer (12) from the element electrode (11), a first post electrode (17) electrically connected to the metal wirings; a second post electrode (19) formed thereon and electrically connected thereto in the circumferential length shorter than that of the first post electrode; a sealing resin (22) formed on the insulating resin layer (12) to cover the side surface of the metal wirings(13, 15), first post electrode (17) and the second post electrode (19); and a solder bump (23) formed as an external terminal on the surface of the second post electrode (19). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a built-in semiconductor integrated circuit portion used for information communication equipment and office electronic equipment, and further having a post electrode as an external electrode, and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device that realizes improvement in adhesion between an external electrode and a sealing resin, narrowing of pitch of solder bumps formed by printing, and increase in number of pins, and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as a semiconductor device and a method for manufacturing the same have been required to be smaller and denser as electronic devices have become smaller and denser.
[0003]
Hereinafter, a semiconductor device using a post electrode as an external electrode and a solder bump portion as an external terminal in a wafer level CSP (Chip Size Package) and a method of manufacturing the same will be described with reference to cross-sectional views.
[0004]
In FIG. 5 (Patent Document 1 below), 101 is a semiconductor substrate, 102 is an element electrode, 109 is a passivation film, 103 is an insulating resin layer, 104 is a metal wiring, 108 is a land portion for forming external terminals, and 105 is a post. The electrodes, 106 are solder bumps, and 107 is a mold resin. Next, in the manufacturing method, a metal wiring 104 and an external terminal forming land portion 108 are formed from the element electrode 102 to the insulating film layer 103, and a post electrode 105 is formed on the external terminal forming land portion. A sealing resin 107 covering the insulating resin layer 103, the metal wiring 104, and the post electrode 105 is formed, and a solder bump 106 is formed on the surface of the post electrode 105. The miniaturization and high density can be achieved at the wafer level, the stress from the mounting substrate can be reduced by the structure of the post electrode, and external terminals corresponding to a further narrow pitch can be formed by forming solder bumps by printing.
[0005]
[Patent Document 1]
JP-A-2001-223242
[0006]
[Problems to be solved by the invention]
However, the conventional semiconductor device has the following problems. In the conventional semiconductor device, in order to cope with a further reduction in pitch and an increase in the number of pins, a post electrode connected to a solder bump, which is an external terminal, is required to have a smaller diameter. However, even if the side surface of the post electrode is covered with the sealing resin due to the stress generated from the mounting board and the solder bumps serving as the external terminals, the post electrode may fail to come off due to the reduction in the diameter of the post electrode. Further, it is necessary to increase the height of the post electrode in order to relieve the stress. However, there is a limit in reducing the diameter of the post electrode by the photolithography process due to the aspect ratio.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which alleviate the stress of the mounting board and the external terminals and eliminate the post electrode disconnection failure in order to solve the conventional problem.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate, an element electrode formed on a surface of the semiconductor substrate, an insulating resin layer partially opened so as to expose the element electrode, A metal wiring including an external terminal forming land portion formed continuously from over the electrode to the insulating resin layer; and at least two or more layers electrically connected to the external terminal forming land portion. A post electrode; a sealing resin formed on the insulating resin layer so as to cover the metal wiring and a side surface of the post electrode of the two or more layers; and a top electrode surface of the post electrode of the two or more layers. A semiconductor device including solder bumps formed as external terminals, wherein an upper electrode of the two or more layers of post electrodes is formed to have a shorter post peripheral length than a lower layer electrode.
[0009]
Next, in a method of manufacturing a semiconductor device according to the present invention, a first step of selectively removing a region of an insulating resin layer located above an element electrode of a semiconductor substrate to form an opening exposing the element electrode A second step of forming a metal wiring partially connected to the element electrode as a land part for forming an external terminal, from the element electrode exposed to the opening to the insulating resin layer; A third step of forming the first post electrode electrically connected to the external terminal forming land portion, and at least having a function of an external electrode electrically connected to the first post electrode. A fourth step of forming one layer of the second post electrode, the upper electrode having a shorter post peripheral length than the lower layer electrode, and a sealing step of protecting the insulating resin layer, the metal wiring, and the at least two layers of post electrodes. Fifth forming resin A step, characterized in that it comprises a sixth step of forming a solder bump on the top surface of the post electrode.
[0010]
In the present invention, the cross-sectional shape of the first post electrode and the second post electrode electrically connected on the external terminal forming land portion parallel to the semiconductor substrate surface is circular, elliptical, square, rectangular, and It is preferably at least one shape selected from polygons other than the above.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the present invention, the stress of the mounting substrate and the external terminals is reduced by the fogging of the sealing resin due to the difference in diameter and cross-sectional shape between the lower and upper post electrodes due to the step-like post electrode structure formed of two or more layers. The stress of the mounting board and the solder bumps serving as the external terminals can be relaxed, and the failure in removing the post electrode can be eliminated. In addition, the post electrodes other than the uppermost post electrode having a function as an external electrode are not restricted by the pitch of the external terminals, and by increasing the diameter of the post electrode, the adhesion with the sealing resin is increased, The stress of the mounting board and the solder bumps as the external terminals can be dispersed. As a result, a post electrode that does not cause a detachment failure can be secured.
[0012]
In the present invention, a step electrode of two or more layers is formed on the land portion for forming the external terminal. However, any number of layers of the step electrode can be formed, and the shape of the post electrode is made circular by a photolithography process. , Polygons, squares, etc. By forming the post electrode in a stepwise manner, fogging of the sealing resin onto the post electrode occurs, and it is possible to prevent the post electrode from slipping out. The diameter of the post electrodes other than the uppermost post electrode can be set to some extent freely, and the surface area in contact with the sealing resin can be increased to further improve the adhesion with the sealing resin.
[0013]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a top view showing the semiconductor device according to the present embodiment with a part of a sealing resin partially or entirely opened. FIG. 2 is a cross-sectional view of the semiconductor device of the present embodiment. Next, FIGS. 3A to 3D are cross-sectional views showing manufacturing steps of the semiconductor device in the present embodiment.
[0015]
First, in FIGS. 1 and 2, reference numeral 10 denotes a semiconductor substrate having therein a semiconductor integrated circuit including a semiconductor element such as a transistor. 11 is an element electrode on the semiconductor substrate, 24 is an SG film, 12 is an insulating resin layer, 17 is a first post electrode, 19 is a second post electrode, 20 is a land portion for forming an external terminal, 21 is a metal wiring, 22 Is a sealing resin, and 23 is a solder bump.
[0016]
In this embodiment, the post electrode structure allows the post electrode to reduce the stress generated from the mounting board and the solder bumps as the external terminals, thereby ensuring high mounting reliability. Further, with the step-like post electrode structure, it is possible to improve the failure in removing the post electrode. In addition, the uppermost post electrode having the function as an external electrode is required to have a smaller pitch in order to cope with a narrow pitch and a multi-pin structure, but the post electrode other than the uppermost one has a smaller diameter. By maintaining the contact area with the sealing resin without any problem, it is possible to further improve the adhesiveness with the sealing resin, and it is possible to secure mounting with higher reliability.
[0017]
Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (d). FIGS. 3A to 3D and 4A to 4D are cross-sectional views showing manufacturing steps for realizing the structure of the semiconductor device shown in FIGS.
[0018]
As shown in FIG. 3A, an insulating material having photosensitivity is applied on a semiconductor substrate by spin coating, dried, exposed and developed in order, and a region in the element electrode 11 on the semiconductor substrate 10 is selected. Then, an insulating resin layer 12 having an opening exposing the plurality of element electrodes 11 is formed. The insulating layer 12 having photosensitivity may be a polymer such as an ester bond type polyimide or an acrylate-based epoxy, and may be any photosensitivity. The insulating resin layer 12 having photosensitivity may be formed of a material formed in a film shape in advance. In that case, the insulating resin layer 12 is bonded on the semiconductor substrate 10, an opening is formed in the insulating layer 12 by exposure and development, and the element electrode 11 is exposed.
[0019]
Next, as shown in FIG. 3B, the entire surface of the element electrode 11 on which the insulating resin layer 12 and the opening are formed is formed by a thin film forming technique such as a sputtering method, a vacuum deposition method, a CVD method or an electroless plating method. For example, a thin metal layer 13 made of a TiW film having a thickness of about 0.2 μm and a Cu film formed thereon having a thickness of about 0.5 μm is formed.
[0020]
Next, as shown in FIG. 3C, the positive photosensitive resist film or the negative photosensitive resist film is covered by spin coating, and a plating resist 14 is formed by well-known exposure and development. A thick metal layer 15 is selectively formed on the thin metal layer 13 by using a thick film forming technique such as electrolytic plating, except for the patterned portion of the patterned plating resist 14. For example, the thick metal layer 15 made of a Cu film having a thickness of about 5 μm is selectively formed.
[0021]
Next, as shown in FIG. 3D, a thick metal layer 15 is formed, and after the plating resist 14 is melted and removed, a well-known exposure and development method including a lot of a positive photosensitive resist film or a negative photosensitive resist film is used. To form a plating resist 16. Here, as the plating resist 16 having photosensitivity, a material formed in a film shape in advance may be used. The first post electrode 17 is selectively formed on the thick metal layer 15 by a post forming technique such as electrolytic plating, except for the pattern portion of the patterned plating resist 16. For example, when the electrode material is Cu and the forming method is electrolytic plating, if the external terminal pitch is 0.4 mm, the post electrode having a thickness of about 50 μm is circular and the cross-sectional shape of the post electrode is about 200 μm. Of the first post electrode 17 can be selectively formed. Note that the cross-sectional shape of the post electrode formed in the photolithography step can be polygonal or star-shaped for the purpose of increasing the area of adhesion to the sealing resin.
[0022]
Next, as shown in FIG. 4A, the first post electrode 17 is formed, and the plating resist 16 is melted and removed. Then, the well-known exposure and development are further performed with a positive photosensitive resist film or a negative photosensitive resist film. To form a plating resist 18. Here, the plating resist 18 having photosensitivity may be a material formed in a film shape in advance. The second post electrode 19 is selectively formed on the first post electrode 17 by a forming technique such as electrolytic plating, except for the pattern portion of the patterned plating resist 18. For example, if the diameter of the first post electrode 17 is about 200 μm, the second post electrode 19 having a diameter of about 180 μm is formed on the first post electrode 17.
[0023]
Electrode plating may be performed using Cu as an electrode material. The second post electrode 19 formed on the first post electrode 17 may have a stepped portion even if the electrode center is not located at the center of the first post electrode 17. Note that the cross-sectional shape of the post electrode 19 formed in the photolithography process may be the same as or different from the cross-sectional shape of the first post electrode 17.
[0024]
Next, as shown in FIG. 4B, after forming the second post electrode 19, the plating resist 18 is melted and removed, and an etching solution capable of melting and removing the thin film metal layer 13 is applied. For example, when the Cu film is entirely etched with a cupric iron chloride solution, and the TiW film is entirely etched with a hydrogen peroxide solution, the thin film metal layer 13 thinner than the thick metal layer 15 is removed first. Is done. Through this process, predetermined metal wirings 21 and lands 20 for forming external terminals are formed on the semiconductor substrate 10. For example, for a metal wiring 21 formed by Cu plating, a line / space = 20/20 μm wiring can be formed for a thickness of 5 μm.
[0025]
Next, as shown in FIG. 4C, the metal wiring 21 and the insulating resin layer 12 are covered with a resin, pressure and heating are applied, and the sealing resin 22 is removed so that the surface of the second post electrode is exposed. Form. For example, the thickness of the sealing resin is 50 to 100 μm using an epoxy resin. The side surfaces of the metal wiring 22, the external terminal forming land 20, the first post electrode 17, and the second post electrode 19 are protected from the melted solder by the sealing resin 22.
[0026]
Next, as shown in FIG. 4D, an antioxidant treatment is performed on the surface of the second post electrode 19, and a solder bump 23 is formed on the surface of the second post electrode 19 that is in contact with the surface by the surface tension. No solder bump is formed on the surface of the sealing resin 22. The heating temperature at this time is equal to or higher than the melting point of the cream solder. In the printing process, the mask 20 may be a commonly used mask or a metal mask.
[0027]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, the stepped post electrode structure of two or more layers can alleviate the stress generated by the mounting substrate and the external terminals at the time of mounting, and can eliminate the defective post electrode. In addition, the stepped post electrodes are affected by the formation of solder bumps by printing, in which only the uppermost post electrode is an external terminal. Can be further increased, and the stress can be further relaxed.
[Brief description of the drawings]
FIG. 1 is a plan view showing a sealing resin of a semiconductor device according to an embodiment of the present invention, partially and entirely opened.
FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
FIGS. 3A to 3D are cross-sectional views illustrating a manufacturing process from formation of an insulating resin layer to formation of a first post electrode portion in a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIGS. 4A to 4D are cross-sectional views illustrating a manufacturing process from the formation of a second post electrode to the formation of a solder bump in a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view of a conventional semiconductor device on which metal bumps are formed.
[Explanation of symbols]
10, 101 Semiconductor substrate 11, 102 Semiconductor element electrode 12, 103 Insulating resin layer 13 Thin metal layer 14 Plating resist 15 Thick metal layer 16 Plating resist 17 First post electrode 18 Plating resist 19 Second post electrode 20 For forming external terminals Land 21 Metal wiring 22, 107 Sealing resin 23, 106 Solder bump 24, 109 Passivation film 104 Metal wiring 105 Post electrode

Claims (4)

A semiconductor substrate;
An element electrode formed on the surface of the semiconductor substrate,
An insulating resin layer partially opened to expose the element electrode,
A metal wiring including an external terminal forming land portion continuously formed over the element electrode over the insulating resin layer;
At least two or more layers of post electrodes electrically connected to the external terminal forming lands,
A sealing resin formed on the insulating resin layer and so as to cover the metal wiring and the side surface of the post electrode of the two or more layers;
A semiconductor device including a solder bump formed as an external terminal on an uppermost electrode surface of the two or more layers of post electrodes,
The semiconductor device according to claim 2, wherein, of the post electrodes of the two or more layers, the upper layer electrode is formed to have a shorter post peripheral length than the lower layer electrode. The cross-sectional shape parallel to the semiconductor substrate surface of the first post electrode and the second post electrode electrically connected to the external terminal forming land portion is a circle, an ellipse, a square, a rectangle, and a polygon other than the above. The semiconductor device according to claim 1, wherein the semiconductor device has at least one shape selected. A first step of selectively removing a region of the insulating resin layer located above the device electrode of the semiconductor substrate to expose the device electrode and form an opening;
A second step of forming a metal wiring that is partially connected to the element electrode as an external terminal formation land from the element electrode exposed to the opening to the insulating resin layer;
A third step of forming the first post electrode electrically connected to the external terminal forming land,
A fourth step of forming at least one layer of the second post electrode electrically connected to the first post electrode and having the function of an external electrode, wherein the upper layer electrode has a shorter post peripheral length than the lower layer electrode;
A fifth step of forming a sealing resin for protecting the insulating resin layer, the metal wiring, and the at least two layers of post electrodes;
Forming a solder bump on the outermost surface of the post electrode. 4. The semiconductor device according to claim 3, wherein a cross-sectional shape of the first post electrode and the second post electrode parallel to the semiconductor substrate surface is at least one shape selected from a circle, an ellipse, a square, and a polygon other than the above. 5. Production method.

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