JP2002198437A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a high performance resistive element region. SOLUTION: The semiconductor device having a plurality of element regions and isolation regions formed on a semiconductor substrate comprises gate electrodes formed in specified element regions among the plurality of element regions, first insulation layers 3a and 3b covering the side wall face of the gate electrodes, and second insulation layers 4a and 4b covering the surface of the first insulation layers wherein the element regions not formed with the gate electrode are covered with the first insulation layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device which is suitable for a semiconductor device manufacturing process (silicide block process) using a diffusion layer region having no silicide layer as a resistance element.

[0002]

2. Description of the Related Art One of means for reducing the parasitic resistance of a transistor and achieving high performance is a process of forming a low-resistance silicide layer on a diffusion layer region. However,
In general, the specific resistance of the silicide layer is small, and in order to realize the resistance value required as a resistance element, it is necessary to make the shape extremely thin and long. In addition, it is difficult to achieve high integration of the semiconductor device. Against this background,
Recently, a diffusion layer having no silicide layer is formed by applying a process in which a silicide layer is not formed to a predetermined element region (hereinafter, referred to as a silicide block process). It has been tried to use as. Hereinafter, a method for manufacturing a semiconductor device using the silicide block process will be described in detail with reference to FIGS.

FIGS. 4 to 6 are sectional process diagrams showing a method of manufacturing a semiconductor device using a silicide block process.

In a conventional method of manufacturing a semiconductor device using a silicide block process, first, an element isolation step (formation of an element region and an element isolation region), a well formation step, and a gate oxide film / gate electrode formation step. By performing a manufacturing process similar to a general CMOS integrated circuit manufacturing process, a semiconductor device having a shape as shown in FIG. 4A is formed. And then, FIG.
Diffusion layer regions (hereinafter, referred to as extension regions) 2a to 2f having a shallow junction are formed in the device region of the semiconductor substrate shown in FIG.
(B)). Thereafter, as shown in FIG. 4C, an insulating material (sidewall material) 4 covering the side walls of the gate electrodes 1a and 1b is deposited on the entire surface of the semiconductor substrate 1, and further, an extension region 2c (not forming a silicide layer) is formed. The resist material 5 is patterned on the resistive element region.

After the resist material 5 is patterned on the resistive element region, the sidewall material 4 is removed by anisotropic ion etching, and then the resist material 5 is removed. As a result, as shown in FIG. 4D, a semiconductor device in which the side wall material 4 is removed except on both side surfaces of the gate electrodes 1a and 1b and the resistive element region is formed.

When the semiconductor device having the shape shown in FIG. 4D is formed, subsequently, as shown in FIG. 5E, diffusion layer regions (source / drain regions) 6a, 6 having a deep junction
b, 7a and 7b are formed by ion implantation. Thereafter, the surface of the semiconductor substrate 1 is washed to expose the substrate material,
As shown in FIG. 5F, a metal layer 10 which reacts with the semiconductor substrate 1 to form silicide is deposited on the entire surface of the substrate. Here, when Si (silicon) is used as the semiconductor substrate 1, Ti (titanium) or Co is used as the metal layer 10.
(Cobalt) or the like.

After the metal layer 10 is deposited on the surface of the semiconductor substrate, the semiconductor substrate 1 and the metal layer 10 are reacted by an appropriate heating process, and the silicide layers 8a to 8g as shown in FIG. 8 g are formed. In this heating step, the side surfaces of the gate electrodes 1a and 1b and the surface of the resistance element region are covered with the side wall material 4c, and the semiconductor substrate 1 and the metal layer 10 do not directly contact each other.
No silicide layer is formed on the side surface and the resistance element region.

When the formation of the silicide layers 8a to 8g is completed, a semiconductor substrate is then formed using an appropriate processing solution for selectively removing (dissolving) only the metal layer 10 as shown in FIG. And the unreacted metal layer 10 is removed. And FIG.
As shown in (i), an S film having an appropriate thickness as the interlayer film 11 is formed.
After depositing iO ₂ or the like, in the element regions to be connected to each other, the interlayer film 11 is removed, a contact hole is formed on the region, and a conductive material (conductive layer) 12 is embedded in the contact hole. Are connected by the wiring layer 13. Then, if necessary, after forming the second and third interlayer films and wirings, finally, the entire semiconductor device is covered with a protective film 1 such as SiN.
4 to complete a series of manufacturing processes.

In the above-described semiconductor device manufacturing process, the thickness of the side wall material 4 is M
In order not to diffuse into the inside of the channel of the OSFET, it is about 1000 ° necessary for separating the two. Therefore, at the time of ion implantation for forming the source / drain regions, impurity ions do not pass through the side wall material 4c, so that the resistance element region 2c always has a shallow junction depth.

[0010]

The resistance of the diffusion layer generally has a temperature coefficient and depends on the impurity concentration.
The impurity concentration dependence of the resistance of the diffusion layer has a minimum point, and the temperature coefficient at the minimum point is almost zero. Therefore, the impurity concentration of the diffusion layer in the resistance element region has a temperature coefficient of 0.
(This concentration varies depending on the process, but in terms of ion implantation amount, for example, ion species BF ₂ , implantation energy 20 [keV], 3.0e15cm
^-2 ). However, in the method of manufacturing a semiconductor device using the silicide block process as described above, the junction depth and the concentration of the resistance element region are controlled by MOSFE.
Because it is inevitably determined by the constraints on the performance of T (depending on the process, in terms of ion implantation amount,
For example, with ion species BF ₂ and implantation energy 3 [keV], 1.0e15
cm- ² ), the impurity concentration could not be optimized,
A high-performance resistive element region cannot be formed.

Various countermeasures have been devised in order to solve such problems. For example, as shown in FIG. 7, a device has been devised such that another ion implantation process is selectively performed only on the resistance element region. ing. However, in this case,
The ion implantation process of the resistance element region is different from that of the extension region, and there is a merit that the impurity concentration of the resistance element region can be set independently. However, a photomask, a lithography process, and a An ion implantation step is required, which increases the cost and labor required for manufacturing the semiconductor device. Further, for example, after forming the source / drain regions, an appropriate insulating material 15 is deposited on the surface of the semiconductor device, and is removed so that the insulating material 15 is selectively left only on the resistance element region. In this state, a method of manufacturing a resistance element region without a silicide layer by forming a silicide layer has been devised (see FIG. 8). However, in such a case, the ion implantation conditions in the resistance element region and the extension region can be made common, but a step of forming a silicide block different from the sidewall material on the resistance element region is required. However, this also leads to an increase in cost and labor required for manufacturing the semiconductor device.

As described above, in the conventional method of manufacturing a semiconductor device using the silicide block process, the impurity concentration of the diffusion layer in the resistance element region can be reduced without increasing the cost and labor required for manufacturing the semiconductor device. Optimization cannot form a high-performance resistor element region.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to reduce the impurity concentration of a diffusion layer in a resistance element region without increasing the cost and labor required for manufacturing a semiconductor device. It is an object of the present invention to provide a technology that can optimize and form a high-performance resistive element region.

[0014]

According to the present invention, the side wall of the gate electrode has a two-layer structure composed of a first and a second insulating layer, and the resistance element region is covered with the first insulating layer. Impurities can be implanted into the resistance element region through the insulating layer. This makes it possible to set the impurity concentration of the resistance element region to the optimum impurity concentration as the resistance element, and thus increases the diffusion layer of the resistance element region without increasing the cost and labor required for manufacturing the semiconductor device. By optimizing the impurity concentration, a high-performance resistance element region can be formed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method for manufacturing a semiconductor device according to the present invention can be applied to, for example, a semiconductor device manufacturing process using a diffusion layer region where a silicide layer is not formed as a resistance element. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS.

In the method of manufacturing a semiconductor device according to this embodiment, the steps from the element isolation step to the formation of the extension region are performed in the same manner as in the conventional process (see the prior art for details), and FIG. A semiconductor substrate in the state shown in a) is formed. Then, the following process is performed on the semiconductor substrate in the state shown in FIG.

First, a sidewall material (first insulating layer) 3 is deposited on the entire surface of the semiconductor substrate, and then a sidewall material 4 (second insulating layer) having an etching selectivity with respect to the sidewall material 3 is further deposited. Thereby, as shown in FIG. 1B, a side wall material layer having a two-layer structure is formed. In this embodiment, SiO ₂ is used as the side wall material 3 and SiN is used as the side wall material 4.

When the formation of the side wall material layer is completed, the side wall material 4 is anisotropically etched under a condition having an etching selectivity with the side wall material 3 so that the resist material 5 covers only the resistance element region 2c. Then, a resist patterning is performed to form a semiconductor device having a shape shown in FIG.

When the resist patterning process is completed, the semiconductor device having the shape shown in FIG. 1C is subjected to an anisotropic etching process to remove the side wall material 3, and then the resistive element region 2c The upper resist material 5 is removed to form a semiconductor device having the form shown in FIG. Then, an ion implantation process is performed on the semiconductor device having the configuration shown in FIG. 2D, and a diffusion layer region (source / drain region) having a deep junction depth as shown in FIG.
6a, 6b and 7a, 7b are formed. In this embodiment, the thickness of the side wall material 3 covering the resistance element region 2c is as thin as several hundreds of .mu.m. Impurity ions are implanted into 2c.

After the formation of the diffusion layer region is completed,
In the same manner as before, a silicide layer and a wiring are formed and FIG.
A semiconductor device having the form shown in FIG. 1F is formed, and a series of manufacturing processes is completed.

When the side wall material is etched in two stages, when the upper side wall material 4 is etched, the upper side wall material 4 is completely etched and at the same time the entire lower layer side wall material 3 is etched. You have to make sure you don't do it. Therefore, the lower side wall material 3
Is desirably about 200 °. If the side wall material 3 has such a thickness, the resistance element region 2c
It is possible to perform the ion implantation process to the substrate sufficiently (originally, since the ions are implanted to a depth of 800 to 1000 °, there is no problem even if the depth is reduced to about 200 °).

As shown in FIGS. 3A and 3B,
As shown in FIG. 3C, if the ion implantation process for forming the source / drain is not performed in the resistive element region (only by changing the pattern of the mask for distinguishing between N-type and P-type), as shown in FIG. This is a resistance element using the same extension region impurity layer as the conventional example shown in FIGS. Therefore, according to this manufacturing method, the plurality of resistive element regions (2c, 2f) can be formed without requiring additional masks and steps.
Can be formed.

<< Effect of Embodiment >> As described above, according to the method of manufacturing a semiconductor device of this embodiment, the side wall material 3 covering the resistance element region 2c is thin, and Since impurity ions can be implanted into the element region 2c, the impurity concentration of the resistance element region 2c can be set to an optimum impurity concentration as a resistance element. Further, there is no additional process except that the sidewall material has a two-layer structure. This makes it possible to optimize the impurity concentration of the resistance element region 2c and form a high-performance resistance element region without increasing the number of steps.

[0024]

According to the method of manufacturing a semiconductor device of the present invention, it is possible to optimize the impurity concentration of the resistance element region and form a high-performance resistance element region without increasing the number of steps.

[Brief description of the drawings]

FIG. 1 is a sectional process view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional process view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional process view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a sectional process view showing a conventional method for manufacturing a semiconductor device.

FIG. 5 is a sectional process view showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a sectional process view showing a conventional method for manufacturing a semiconductor device.

FIG. 7 is a sectional process view showing a conventional method for manufacturing a semiconductor device.

FIG. 8 is a sectional process view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2a, 2b, 2c, 2d, 2e, 2f extension region 3, 4 sidewall material 5 resist material 6a, 6b, 7a, 7b source / drain region 8a, 8b, 8c, 8d, 8e, 8f, 8g silicide layer Reference Signs List 9 resist material 10 metal layer 11 interlayer film 12, 13 wiring layer 14 protective film 15 insulating material

Claims (6)

[Claims] 1. A semiconductor device comprising a semiconductor substrate having a plurality of device regions and a device isolation region, comprising: a gate electrode formed in a predetermined device region in the plurality of device regions; A first insulating layer covering a side wall surface; and a second insulating layer covering a surface of the first insulating layer, wherein the element region where the gate electrode is not formed is the first region.
A semiconductor device, which is covered with an insulating layer. 2. The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are a silicon oxide film layer and a silicon nitride film layer, respectively. A step of forming first and second element regions and an element isolation region on the semiconductor substrate; a step of forming a gate electrode on the first element region; and implanting impurities into the semiconductor substrate. Forming a diffusion layer region having a shallow junction depth in the first element region; depositing a first insulating layer on the semiconductor substrate surface; and forming a second insulating layer on the first insulating layer. Depositing the second insulating layer while leaving the second insulating layer deposited on the side wall portion of the gate electrode; at least near the side wall of the gate electrode formed in the first element region Removing the first insulating layer while leaving the first insulating film formed in a portion and a predetermined portion of the second element region; and a semiconductor in the first element region in which the gate electrode is formed. Inject impurities into the substrate Forming a semiconductor region, depositing a predetermined metal layer on the semiconductor substrate, and heating the semiconductor substrate to form a silicide layer at an interface between the semiconductor substrate material and the metal layer. A method for manufacturing a semiconductor device. 4. The method according to claim 3, wherein the impurity concentration of the source / drain region is set such that the temperature coefficient of the resistance is minimized. 5. The method according to claim 3, wherein the first insulating layer and the second insulating layer are a silicon oxide film layer and a silicon nitride film layer, respectively. 6. The step of forming a source / drain region in the first element region is performed by ion implantation. At this time, ions of the same type are also implanted under the first insulating film in the second element region. The method of manufacturing a semiconductor device according to claim 3, wherein the method is performed.