JP2727557B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which an insulating layer covers a gate electrode.

[Summary of the Invention]

The present invention provides a method for manufacturing a semiconductor device as described above, in which a conductive layer, an insulating layer, and an etching stopper layer for the insulating layer are sequentially laminated, and these are processed into a pattern of a gate electrode, and the conductive layer containing impurities is formed. And the etching stopper layer are simultaneously processed into a source / drain electrode pattern, so that the source / drain electrodes and the source / drain regions can be in contact with self-line while securely insulating the gate electrode by a simple process. It was made possible.

[Conventional technology]

If the source / drain electrodes of the MOS-FET can be in contact with the source / drain regions by self-alignment, the degree of integration of the MOS-FET can be improved.

As one method for this, JP-A-61-123181 discloses a method in which a gate electrode is covered with an insulating layer and impurities are solid-phase-solid diffused from an impurity-containing layer into a semiconductor substrate. A method is disclosed in which a drain region is formed and the impurity-containing layer is also used as a source / drain electrode.

[Problems to be solved by the invention]

However, in this method, when the insulating layer covering the gate electrode is etched to expose the surface of the semiconductor substrate, the insulating layer is likely to be excessively etched, particularly at the shoulder of the gate electrode. For this reason, in the semiconductor device manufactured by this method, insulation failure of the gate electrode is likely to occur.

One method for solving such a problem is disclosed in
Although disclosed in JP-A-154049, the method is extremely complicated and impractical.

[Means for solving the problem]

The method of manufacturing a semiconductor device according to the present invention includes the first conductive layer
A step of sequentially laminating 15, a first insulating layer 16, and an etching stopper layer 17 for the insulating layers 16, 21 on the semiconductor substrate 11;
Processing the 16 and the first conductive layer 15 into a gate electrode pattern; forming a second insulating layer 21 on the semiconductor substrate 11 so as to cover the gate electrode pattern; The second insulating layer 21 is subjected to anisotropic etching, so that the second side wall of the gate electrode pattern is formed.
Forming an exposed portion in the semiconductor substrate 11 with the insulating layer 21 remaining, and forming a second conductive layer 22 containing impurities and in contact with the exposed portion on the semiconductor substrate 11; Forming the source / drain regions 23a and 23b by diffusing the impurity from the second conductive layer 22 into the semiconductor substrate 11 through the exposed portion; and forming the second conductive layer 22 and the Simultaneously processing the etching stopper layer 17 into patterns of the source / drain electrodes 22a and 22b.

[Action]

In the method for manufacturing a semiconductor device according to the present invention, the etching stopper layer 17 for the insulating layers 16 and 21 is formed on the first insulating layer 16.
Are laminated and processed into a gate electrode pattern including the etching stopper layer 17, so that the second insulating layer
The first insulating layer 16 is not etched during the anisotropic etching for 21.

Moreover, the steps required to prevent the etching of the first insulating layer 16 are only the lamination and patterning of the etching stopper layer 17, so that the steps are simple. Further, since the etching stopper layer 17 is later processed into the pattern of the source / drain electrodes 22a and 22b simultaneously with the second conductive layer 22, the process is further simplified.

Then, a second insulating layer is formed on the side wall of the gate electrode pattern.
An exposed portion is formed in the semiconductor substrate 11 with the portion 21 left, and source / drain regions 23a and 23b are formed by solid-phase diffusion from the second conductive layer 22 containing impurities and in contact with the exposed portion. In addition, the second conductive layer 22 is
Since they are also used as a and 22b, the source / drain electrodes 22a and 22b and the source / drain regions 23a and 23b can be in contact with each other by self-alignment.

Further, since the etching stopper layer 17 is processed into the pattern of the gate electrode and further processed into the pattern of the source / drain electrodes 22a and 22b, the etching stopper layer 17 hardly remains and the influence of the remaining etching stopper layer 17 is reduced. Can be suppressed.

〔Example〕

Hereinafter, an embodiment of the present invention applied to the manufacture of a MOS-FET will be described with reference to FIG.

In this embodiment, as shown in FIG. 1A, an element formation region 13 is defined by forming a SiO ₂ film 12 as a field oxide film on the surface of a P-type Si substrate 11, and the surface of the element formation region 13 is formed. An SiO ₂ film 14, which is a gate oxide film, is formed.

Thereafter, on the Si substrate 11, a polycrystalline Si layer 15 for forming a gate electrode, an SiO ₂ layer 16, and a thin polycrystalline S
The i-layer 17 is sequentially laminated by CVD. Then, a resist layer (not shown) is further formed on polycrystalline Si layer 17.

Next, by patterning the resist layer,
An etching mask 18 is formed as shown in FIG. 1B.

Then, by using this etching mask 18 in common and performing the three-stage RIE by sequentially changing the etching gas, as shown in FIG. 1B, the polycrystalline Si layer 17, the SiO ₂ layer 16 and the
The Si layer 15 is etched into a gate electrode pattern.

Thereafter, the etching mask 18 is removed. At this point, the polycrystalline Si layer 15, the SiO ₂ layer 16, the polycrystalline Si layer 17, and the SiO ₂ film are removed.
Using 12 as a mask, ion implantation for forming the N ⁻ region of the LDD may be performed.

Next, an SiO ₂ layer is formed on the Si substrate 11 by CVD, and RIE is performed on the entire surface of the SiO ₂ layer, and as shown in FIG. 1C, a polycrystalline Si layer 15 and an SiO ₂ layer 16 are formed. The surface of the Si substrate 11 is exposed with the SiO ₂ layer 21 left on the side wall of the substrate.

At this time, there are polycrystalline Si layer 17 on the SiO ₂ layer 16, the etching characteristics and the SiO ₂ layer 16 and the polycrystalline Si layer 17 are different from each other. Therefore, in order to expose the surface of the Si substrate 11,
Even if over-etching is performed on the SiO ₂ layer 21, the SiO ₂ layer
16 is not etched away.

Next, as shown in FIG. 1D, a polycrystalline Si layer 22 is formed on the Si substrate 11 by CVD. At this time, the polycrystalline Si layer 22 and the polycrystalline Si layer 17 are integrated with each other. Thereafter, impurities are ion-implanted into the polycrystalline Si layer 22 and the polycrystalline Si layer 17.

Next, impurities are solid-phased into the Si substrate 11 from the polycrystalline Si layer 22.
By solid-phase diffusion, source / drain regions 23a and 23b are formed as shown in FIG. 1E. Then polycrystalline
The Si layer 22 is etched into a pattern of the source / drain electrodes 22a and 22b.

Next, an SiO ₂ film (not shown) which is an interlayer insulating film is formed by CVD, an electrode window (not shown) is formed in the SiO ₂ film, and the source / drain electrodes 22a and 22a are formed through the electrode window. 22b is connected to an Al wiring (not shown).

〔The invention's effect〕

In the method of manufacturing a semiconductor device according to the present invention, the first insulating layer is not etched during the anisotropic etching of the second insulating layer. It is possible to make the source / drain electrode and the source / drain region contact with each other with a self-aligned line while suppressing the influence of the residual.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing one embodiment of the present invention. In the reference numerals used in the drawings, 11: Si substrate 15: polycrystalline Si layer 16: SiO ₂ layer 17: polycrystalline Si layer 21: SiO ₂ layer 22: polycrystalline Si layers 22a, 22b ... Source / drain electrodes 23a, 23b ... Source / drain regions.

Claims (1)

(57) [Claims] 1. A method for manufacturing a semiconductor device in which an insulating layer covers a gate electrode, wherein a first conductive layer, the first insulating layer, and an etching stopper layer for the insulating layer are sequentially laminated on a semiconductor substrate. Forming the etching stopper layer, the first insulating layer, and the first conductive layer into a pattern of the gate electrode; and forming a second pattern on the semiconductor substrate over the pattern of the gate electrode. Forming the insulating layer, and performing anisotropic etching on the second insulating layer to form the second insulating layer on the side wall of the pattern of the gate electrode.
Forming an exposed portion on the semiconductor substrate with the insulating layer remaining, forming a second conductive layer containing impurities and in contact with the exposed portion on the semiconductor substrate; Forming a source / drain region by diffusing the impurity from the conductive layer into the semiconductor substrate through the exposed portion; and forming a pattern of the source / drain electrode using the second conductive layer and the etching stopper layer. And a step of simultaneously processing the semiconductor device.