JP2000074988A - Production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a plane package containable IGBT(insulation gate type bipolar transistor) chips of which turn off destruction resistance quantity is large. SOLUTION: Switching characteristics of each IGBT chip are measured in a switching characteristic measuring process and the IGBT chips within a reference value is selected. Among the selected IGBT chips in a td(off) (delay time in turn off operation) selection process, those with scattering of the td(off) within 10% are selected. The static characteristics of the selected IGBT chips are measured in a static characteristic process and the IGBT chips within a reference value are selected. In a combining process, the IGBT chips having switching characteristics and static characteristics within reference values and the scattering of td(off) within 10% are combined. In an assembling process, a plurality of combined IGBT chips are contained in a plane package.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a first main electrode and a control electrode on a first main surface such as an insulated gate bipolar transistor (hereinafter referred to as IGBT), and a second main electrode on a second main surface. The present invention relates to a method of manufacturing a semiconductor device having a pressure contact structure in which a plurality of semiconductor chips having the following are arranged in a flat package.

[0002]

2. Description of the Related Art IGBTs have been applied in a wide range of fields as power switching devices. In addition, since it is a voltage drive element, it is easy to control and easy to use, and the safe operation area is wide. For this reason, a module in which a plurality of IGBT chips are integrated in the same package for the purpose of application in the field of large capacity devices. The structure is adopted to increase the element capacitance.

[0003] However, the module structure has the disadvantage that the number of bonding wires increases as the number of chips in the package increases and the internal inductance increases, and that heat can be dissipated only on one side. To solve these disadvantages, M
A flat IGBT has appeared as an OS device. Regarding the increase in the current of the semiconductor device, a plurality of IGBs are used in the flat type IGBT in the same manner as the module type IGBT.
A large current is achieved by incorporating a T chip.

The combination of a plurality of IGBT chips to be incorporated in a flat package is based on the static characteristic check data in the state of the wafer after the process, and the variation of the threshold voltage and the saturation voltage (VCE (sat)). And a plurality of freewheeling diodes juxtaposed in the same package are also combined so as to reduce the variation in forward voltage drop (VF) of each diode.

[0005] This is based on a module assembling process. However, in a conventional module structure, wire-bonding is performed before mounting in a package.
For each IGBT chip, a dynamic test such as turn-off, turn-on, and reverse recovery corresponding to the rating could not be performed. FIG. 5 is a block diagram of a conventional manufacturing process. P-type diffusion, n-type diffusion, gate oxide coating on semiconductor wafers,
A static characteristic measuring step for measuring the static characteristics of each IGBT unit of a semiconductor wafer on which a large number of IGBT units are formed by performing various steps such as forming various electrodes, and cutting the semiconductor wafer to form an IGBT chip Wafer cutting step, static characteristic selection step of re-measuring and selecting static characteristics of IGBT chips, combination step of combining a plurality of IGBT chips with uniform characteristics, combined IGBT
The flat IGBT is completed through an assembly process of incorporating the chip into a flat package.

[0006]

As described above, even if the variation in static characteristics is reduced and a plurality of IGBT chips are combined, it cannot be determined whether the variation in switching characteristics of each IGBT chip is small. Actually, in the flat IGBT, in the device assembled in the above-described assembling process, the non-defective rate of the turn-off test in the test process is only about 50%. For this reason, as a result of investigating the cause of the turn-off breakdown, even if the variation in static characteristics is reduced and the IGBT chips are combined, the variation in the turn-off time between the IGBT chips is about 40% at the maximum, and the current due to the variation in the switching time is reduced. It turned out to be destroyed due to concentration. From these results, the flat IG
In a semiconductor device having a large current capacity such as a BT and having a large current capacity by increasing the number of built-in IGBT chips, the dynamic current sharing of a plurality of IGBT chips incorporated in a package at the time of assembly is made uniform. That is, unless the variation in the switching characteristics, especially the turn-off characteristics is reduced, there is a very high possibility that the current concentrates on a specific IGBT chip at the time of interrupting a large current to cause a turn-off breakdown.

An object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing a semiconductor device in which a plurality of IGBT chips are housed in a flat package having a large turn-off breakdown resistance.

[0008]

In order to achieve the above object, a semiconductor chip having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is provided. A semiconductor device incorporated in a flat package by juxtaposition with a pair of common electrode plates exposed on both sides and a semiconductor chip incorporated in a flat package consisting of an insulating case provided on both common electrode plates. The switching characteristic of each semiconductor chip is measured in a method of manufacturing a semiconductor device having a pressure contact structure having a contact terminal body serving also as a pressurizing, conducting, and radiating member between the semiconductor device and a first main electrode of each semiconductor chip. And a step of selecting a semiconductor chip having uniform characteristics, and a step of incorporating the selected semiconductor chip into a flat package.

Preferably, the method includes a step of selecting a semiconductor chip whose switching characteristic is a delay time (td (off)) at the time of a turn-off operation and the variation of the delay time is within 10%. The semiconductor chip may be any one of an insulated gate bipolar transistor, a MOS controlled thyristor, and a MOS transistor.

As described above, the switching characteristics of each semiconductor chip are measured before assembling, and the switching characteristics, in particular, the IG values are set so as to reduce variations in td (off).
BT chips are combined. If the variation of td (off) is small, the current sharing between the IGBT chips at the time of turn-off becomes uniform. As a result, it is possible to prevent the current from being concentrated on a specific IGBT chip and the element from being broken.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. An IGBT will be described as an example of a MOS device. FIG. 1 is a block diagram showing a manufacturing process according to one embodiment of the present invention. In a wafer cutting step, a silicon wafer on which IGBT chips that have undergone various diffusion steps are integrated is cut and separated into individual IGBT chips. In the switching characteristic measuring step, the switching characteristics (turn-off time, turn-on time, etc.) of each IGBT chip are measured, and IGBT chips within the standard value are selected. In the td (off) selection step, among the IGBT chips selected, the IGBT chips whose variation in td (off) is within 10% are selected. Next, the IGB selected in the static characteristic measurement step
The static characteristics (saturation voltage (VCE (sat)), collector-emitter breakdown voltage (VCEO), gate-emitter breakdown voltage (VGE), etc.) of the T chip are measured, and IGBT chips within the standard value are selected. In the combining step, IGBT chips whose switching characteristics and static characteristics are within specified values and whose variation in td (off) is within 10% are combined. In the assembling process, a plurality of IGBT chips combined are housed in a flat package. The details will be described below.

FIG. 2 shows an IGB for measuring switching characteristics.
It is principal part sectional drawing of a T element. IG on base plate 1
The BT chip 2 and the contact terminals 3 which play the role of pressurization, conduction and heat dissipation are stacked. These are accurately positioned by the positioning guide 4 and become the IGBT element 10. The positioning collar 6 is fixed to the contact terminal body 3 and positions the contact terminal body 4. After measuring and sorting the switching characteristics and static characteristics, the IGBT element 10 incorporating the IGBT chip 2 is housed in a flat package.

FIG. 3 is a diagram showing a state in which the switching characteristics and the static characteristics of the IGBT chip are measured. Said I
The GBT element 10 is vertically pressed by pressing electrodes 11 and 12.
And pressurizes the IGBT element 10. Further, a control signal is sent from the gate drive circuit 23 to the gate electrode (not shown) of the IGBT chip 2 via the gate probe 5. A switching characteristic measuring circuit 21 is connected to the press press 20. The switching characteristic measuring circuit 21 measures the turn-off time, the turn-on time, the reverse recovery characteristic of the diode, and the like. Further, the changeover switch 24 enables connection to the static characteristic measurement circuit 22. In the switching characteristic measurement, a large number of IGBT elements 10 are prepared, and the switching characteristics of all the IGBT elements 10 are measured. The measurement conditions were IG
The BT chip 2 is supplied with a current and a voltage under conditions that guarantee several times the rating.

FIG. 4 shows the definition of the turn-off time of the IGBT. FIG. 4A shows the gate-emitter voltage waveform, and FIG. 4B shows the collector current waveform. The switching characteristic measuring circuit 21 supplies a gate voltage and a collector current to the IGBT element 10. Turn-off time toff from gate voltage waveform and collector current waveform during turn-off operation
, Delay time td (off) and fall time tf. These are defined as follows:
(1) td (off) is the time from when the gate voltage becomes 90% of the maximum value to when the collector current becomes 90% of the maximum value. (2) tf is the time required for the collector current to change from 90% to 10% of the maximum value. (3) toff is td
This is the time obtained by adding (off) and tf.

Of these data, td (off) has the greatest influence on the current sharing during the turn-off operation.
IGBT elements are selected and combined so that the variation of d (off) is within 10%. In addition, by conducting a test to cut off the collector current several times the rated current,
It is checked whether the T chip 2 has a sufficient turn-off capability. The reason why the variation of td (off) was set within 10% was that the non-defective rate was 9% in the collector current cutoff test of several times.
This is because it is set to 0% or more.

After the measurement of the switching characteristics of all the IGBT chips 2 and the selection of td (off) are completed, the operation is switched to the static characteristic measuring circuit 22 to confirm that VCE (sat), VCEO, and VGE are normal. I do. When the freewheeling diode is incorporated in the same package, the static characteristics and the reverse recovery characteristics of the diode are measured, and those having these characteristics within the specified values are selected. (Reverse recovery time) and diode chips are selected and combined so that each variation of Irp (reverse recovery peak current) is within 10%. Of course, the diode is also confirmed to have a sufficient reverse recovery withstand voltage, and the anode-cathode breakdown voltage after the measurement of the reverse recovery characteristic is confirmed.

In the above process, the variation of td (off) is reduced by 1
The IGBT chip with the combination within 0% is sent to the next assembly process. In the case of incorporating a diode, after sorting, the diode chip is also sent to the assembling process.

[0018]

According to the present invention, for a MOS device having a plurality of pressure contact structures built in a flat package, semiconductor chips having the same switching characteristics can be combined, and current sharing between the semiconductor chips can be equalized. Not only can it cut off a current several times higher than the rated current of the semiconductor device without breaking it, and the non-defective product rate can be greatly improved. In addition, by measuring the switching characteristics of all the chips before assembly, semiconductor chips having poor switching characteristics can be removed before assembly, and the yield of semiconductor devices can be improved. Further, even when the freewheel diode is housed in the same package, the switching characteristics of the diode chips can be similarly adjusted and housed in a flat package, so that the yield of semiconductor devices having the freewheel diode can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of an IGBT element for measuring switching characteristics.

FIG. 3 is a diagram showing a state in which switching characteristics and static characteristics of an IGBT chip are measured.

FIG. 4 is a diagram showing a definition of a turn-off time of the IGBT.

FIG. 5 is a block diagram showing a conventional manufacturing process.

[Explanation of symbols]

 Reference Signs List 1 base plate 2 IGBT chip 3 contact terminal body 4 positioning guide 5 gate probe 6 positioning collar 10 IGBT element 11 lower press electrode 12 upper press electrode 20 press press 21 switching characteristic measuring circuit 22 static characteristic measuring circuit 23 gate driving circuit 24 Switch

Claims (3)

[Claims] 1. A semiconductor device comprising: a plurality of semiconductor chips having a first main electrode and a control electrode on a first main surface and a plurality of semiconductor chips having a second main electrode on a second main surface, which are incorporated in a flat package; A pair of common electrode plates exposed on both sides, and a semiconductor chip incorporated in a flat package consisting of an insulating case provided on both common electrode plates, between one common electrode plate and the first main electrode of each semiconductor chip. In a method of manufacturing a semiconductor device having a pressure contact structure having a contact terminal body also serving as a pressure, conduction, and heat radiator, a step of measuring switching characteristics of each semiconductor chip and a step of selecting semiconductor chips having uniform characteristics. A method for manufacturing a semiconductor device, comprising: a step of incorporating a selected semiconductor chip into a flat package. 2. The switching characteristic is a delay time (td (off)) at the time of turn-off operation, and the variation of the delay time is 1
2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of selecting a semiconductor chip that is within 0%. 3. The semiconductor chip according to claim 1, wherein said semiconductor chip is an insulated gate bipolar transistor, a MOS controlled thyristor and a MOS transistor.
The method according to claim 1, wherein the method is any one of a transistor.