CN222016532U - Charge pump and phase-locked loop circuit - Google Patents
Charge pump and phase-locked loop circuit Download PDFInfo
- Publication number
- CN222016532U CN222016532U CN202420282391.XU CN202420282391U CN222016532U CN 222016532 U CN222016532 U CN 222016532U CN 202420282391 U CN202420282391 U CN 202420282391U CN 222016532 U CN222016532 U CN 222016532U
- Authority
- CN
- China
- Prior art keywords
- circuit
- charge pump
- charge
- output
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001105 regulatory effect Effects 0.000 claims abstract description 17
- 238000005070 sampling Methods 0.000 claims description 27
- 230000003044 adaptive effect Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 12
- 238000007599 discharging Methods 0.000 description 12
- 238000004140 cleaning Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Abstract
The utility model describes a charge pump for a phase locked loop circuit, comprising: the current source is connected to the first power supply voltage and is used for providing reference current for the charge pump; the first charge and discharge branch circuit has one end grounded and is controlled by a pull-down pulse signal to output discharge current; the second charge-discharge branch is connected between the first charge-discharge branch and the second power supply voltage and is controlled by a pull-up pulse signal to output charging current; the loop filter is connected with the first charge-discharge branch circuit and the second charge-discharge branch circuit, and the voltage output end of the loop filter forms the output end of the charge pump; the self-adaptive adjusting circuit is connected between the output end of the charge pump and the second charge-discharge branch circuit and is used for outputting a second power supply voltage to the second charge-discharge branch circuit according to the output voltage signal of the charge pump so as to adjust the output voltage signal of the charge pump and output the second power supply voltage. According to the utility model, the self-adaptive regulating circuit is introduced to eliminate the problem of current mismatch of the charge-discharge circuit in the charge pump, so that the requirement of low output spurious of the charge pump is realized.
Description
Technical Field
The present utility model relates to the field of integrated circuit design, and more particularly, to a charge pump and a pll circuit including the same.
Background
Phase Locked Loop (PLL) circuits exist in a variety of high frequency applications, ranging from simple clock-cleaning circuits to local oscillators for high performance radio communication links, and ultra-fast switching frequency synthesizers in vector network analyzers. Fig. 1 is a schematic diagram of a typical charge pump phase-locked loop structure, which operates according to the following principles: after the oscillation signal generated by the voltage-controlled oscillator (VCO) passes through the frequency divider (/ N), the frequency is divided by N times, the phase and the frequency are compared with the reference clock through the Phase Frequency Detector (PFD), a pull-up signal up or a pull-down signal down is generated according to possible phase errors, a corresponding current is generated by the Charge Pump (CP), and the current is converted into voltage change through the loop filter (LPF) to drive the control voltage of the VCO to rise or fall, so that negative feedback adjustment is realized to output stable frequency multiplication clock signals.
Disclosure of utility model
In view of the above, the present utility model provides a charge pump and a phase locked loop circuit including the same.
The utility model provides a charge pump for a phase-locked loop circuit, which can output voltage signals based on discharge current and charge current, and comprises: the current source is connected to the first power supply voltage and is used for providing reference current for the first charge and discharge branch circuit and the second charge and discharge branch circuit; the first charge and discharge branch circuit has one end grounded and is controlled by a pull-down pulse signal to output discharge current; the second charge-discharge branch is connected between the first charge-discharge branch and the second power supply voltage and is controlled by a pull-up pulse signal to output charging current; the loop filter is connected with the first charge-discharge branch and the second charge-discharge branch, and the voltage output end of the loop filter forms the output end of the charge pump and is used for outputting an output voltage signal of the charge pump according to the charge current or the discharge current; the self-adaptive adjusting circuit is connected between the output end of the charge pump and the second charge-discharge branch circuit and is used for outputting a second power supply voltage to the second charge-discharge branch circuit according to the output voltage signal of the charge pump so as to adjust the output voltage signal of the charge pump and output the second power supply voltage.
Optionally, the first charge-discharge branch circuit comprises a discharge circuit and a first branch switch, the discharge circuit is connected with the current source, and the first branch switch is connected between the ground and the discharge circuit and is controlled by a pull-down pulse signal to discharge the discharge circuit; the second charging and discharging branch circuit comprises a charging circuit and a second branch switch, the charging circuit is connected with a current source, the second branch switch is connected between a second power voltage and the charging circuit, and is controlled by a pull-up pulse signal to charge the charging circuit.
Optionally, the discharging circuit comprises a first NMOS tube, a second NMOS tube and a third NMOS tube which are in common gate, wherein the drain electrode of the first NMOS tube is connected with the current source and the grid electrode of the first NMOS tube, and the drain electrodes of the second NMOS tube and the third NMOS tube are connected with the charging circuit; the first branch switch comprises a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the source electrode of the fourth NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the sixth NMOS tube receives a pull-down pulse signal, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the third NMOS tube.
Optionally, the charging circuit includes a first PMOS and a second PMOS that are co-gated, where a drain of the first PMOS is connected to a drain of the second NMOS and a gate of the first PMOS, and a drain of the second PMOS is connected to a drain of the third NMOS; the second branch switch comprises a third PMOS tube and a fourth PMOS tube, the sources of the third PMOS tube and the fourth PMOS tube are connected with a second power supply voltage, the drain electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube, the grid electrode of the third PMOS tube is grounded, the grid electrode of the fourth PMOS tube receives a pull-up pulse signal, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube.
Optionally, the charge pump further comprises: the first selection circuit comprises a first switching tube and a second switching tube; the first switch tube is connected to the output end of the charge pump and is used for being turned on or off according to a control signal so as to output an output voltage signal of the charge pump to the voltage-controlled oscillator; the second switch tube is connected between the output end of the charge pump and the self-adaptive regulating circuit and is used for being turned on or off according to a control signal so as to input an output voltage signal of the charge pump to the self-adaptive regulating circuit.
Optionally, the adaptive adjustment circuit includes: the boost circuit is used for outputting a reference voltage; the power switch is connected with the boost circuit, and the voltage of the output end of the power switch changes along with the voltage change of the controlled end; the comparison circuit is connected with the boost circuit and the power switch and is used for receiving an output voltage signal of the charge pump and feeding back and regulating the voltage of the output end of the power switch according to the voltage of the output end of the power switch and the output voltage signal of the charge pump; and one end of the second selection circuit is connected with the first power supply voltage, and the other end of the second selection circuit is connected with the output end of the power switch and is used for selectively outputting the first power supply voltage or the voltage of the output end of the power switch according to the control signal to serve as the second power supply voltage.
Optionally, the comparing circuit includes: the voltage sampling circuit comprises a first sampling resistor and a second sampling resistor, wherein the first end of the first sampling resistor is connected with the output end of the power switch, the second end of the first sampling resistor and the first end of the second sampling resistor are commonly connected to form a signal output end of the voltage sampling circuit, and the second end of the second sampling resistor is grounded; the non-inverting input end of the comparator receives the output voltage signal of the charge pump, the inverting input end of the comparator is connected with the output end of the voltage sampling circuit, and the output end of the comparator outputs comparison voltage to the controlled end of the power switch.
Optionally, the second selection circuit includes a third switching tube and a fourth switching tube, one end of the third switching tube is connected with the first power supply voltage, the other end is used as an output end to output the first power supply voltage as the second power supply voltage in a conducting state, one end of the fourth switching tube is connected with an output end of the power switch, the other end is used as an output end to output the output voltage of the output end of the power switch as the second power supply voltage in the conducting state.
Optionally, the power switch is an NMOS tube; or the power switch is a PMOS tube.
The utility model also provides a phase-locked loop circuit comprising: the phase frequency detector outputs a pull-up pulse signal and a pull-down pulse signal based on the phase difference and the frequency difference of the reference clock signal and the feedback clock signal; the charge pump is connected with the phase frequency detector, outputs corresponding charging current or discharging current based on the pull-up pulse signal or the pull-down pulse signal, and outputs an output voltage signal of the charge pump based on the charging current or the discharging current; the voltage-controlled oscillator is connected with the charge pump and outputs a clock signal based on an output voltage signal of the charge pump; and one end of the frequency divider is connected with the voltage-controlled oscillator, and the other end of the frequency divider is connected with the phase frequency detector so as to divide the clock signal output by the voltage-controlled oscillator and then output a feedback clock signal to the phase frequency detector.
Compared with the prior art, the utility model has at least the following outstanding advantages:
According to the application, the output voltage signal of the charge pump is introduced into the self-adaptive regulating circuit, and the self-adaptive regulating circuit outputs the second power supply voltage which is in a certain proportion with the output voltage signal value of the charge pump to the second charge-discharge branch circuit so as to regulate the charge current and the discharge current, thereby eliminating the current mismatch problem of the charge-discharge circuit in the charge pump, and further realizing the requirement of low output spurious of the charge pump.
Drawings
FIG. 1 is a schematic diagram of a typical charge pump phase locked loop structure of the prior art;
FIG. 2 is a schematic diagram of a conventional charge pump;
FIG. 3 is a loop lock critical node waveform for the charge pump current mismatch of FIG. 2;
Fig. 4 is a schematic circuit diagram of a charge pump according to the present application;
FIG. 5 is a schematic diagram of another charge pump circuit according to the present application;
FIG. 6 is a schematic diagram of a circuit configuration of another charge pump according to the present application;
FIG. 7 is a schematic diagram of an adaptive adjustment circuit according to the present application;
FIG. 8 is a schematic diagram of a specific structure of an adaptive adjustment circuit according to the present application;
Fig. 9 is a schematic diagram of a control signal of a switch tube in a charge pump according to the present application.
Detailed Description
In order that the above objects, features and advantages of the utility model will be readily understood, a further description of the utility model will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present utility model. The present utility model may be embodied in many other forms than those herein described, and those skilled in the art may readily devise numerous other arrangements that do not depart from the spirit of the utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.
Fig. 2 is a schematic diagram of a conventional charge pump, in which the up and down signals are pulses of equal width when the loop is locked, so that the magnitude of the output voltage Vcont is not changed. In fig. 2, the CP current is mainly determined by M3 and M5, and specifically, may be expressed as the following formula:
As can be seen from fig. 2, the output voltage Vcont is uncertain, especially for different output frequencies, and when Vcont varies, vds of M3 and M5 is affected, resulting in mismatch of pull-up and pull-down currents. Fig. 3 shows waveforms of the loop lock key nodes when the charge pump currents shown in fig. 2 are mismatched, as shown in the figure, when Vcont is low, the current M5 is greater than the current M3, and as can be seen from the figure, due to the mismatch of the currents, the up and down signal pulse widths are unequal, the Vcont nodes are finally dithered, and spurious output signals are caused.
Based on the above technical problems, the present application provides a schematic structural diagram of a charge pump, as shown in fig. 4, the charge pump can output a voltage signal based on a discharging current and a charging current, wherein the charge pump includes: a current source 10 connected to the first power voltage AVDD for providing a reference current for the first charging/discharging branch 21 and the second charging/discharging branch 22;
The first charge-discharge branch 21 has one end grounded and is controlled by a pull-down pulse signal down to output a discharge current I down; the second charge-discharge branch 22 is connected between the first charge-discharge branch 21 and the second power supply voltage AVDD2 and controlled by the pull-up pulse signal up to output a charging current I up;
The loop filter 40 is connected to the first charge-discharge branch 21 and the second charge-discharge branch 22, and the voltage output end thereof forms an output end of the charge pump, and is configured to output an output voltage signal Vcont of the charge pump according to the charge current I up or the discharge current I down;
The adaptive adjusting circuit 30 is connected between the output end of the charge pump and the second charge-discharge branch 22, and is configured to output a second power voltage AVDD2 to the second charge-discharge branch 22 according to the output voltage signal Vcont of the charge pump, so as to adjust the magnitude of the output voltage signal Vcont of the charge pump and output the same.
In the embodiment of the application, the output voltage signal Vcont of the charge pump is introduced into the adaptive regulating circuit 30, and the adaptive regulating circuit 30 outputs the second power voltage AVDD2 in a certain proportion to the Vcont value to the second charge-discharge branch 22 according to the Vcont value, so as to regulate the charge current and the discharge current, thereby eliminating the problem of current mismatch of the charge-discharge circuit in the charge pump, and further realizing the requirement of low spurious output of the charge pump.
Optionally, in some embodiments, as shown in fig. 5, the first charge-discharge branch 21 includes a discharge circuit 211 and a first branch switch 213, the discharge circuit 211 is connected to the current source 10, and the first branch switch 213 is connected between ground and the discharge circuit 211 and is controlled by a pull-down pulse signal down to discharge the discharge circuit 211;
Further alternatively, as shown in fig. 6, the discharging circuit 211 includes a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 that are co-gated, where the drain of the first NMOS transistor N1 is connected to the current source 10 and the gate of the first NMOS transistor N1, and the drains of the second NMOS transistor N2 and the third NMOS transistor N3 are connected to the charging circuit 222, that is, the discharging circuit 211 adopts a current mirror structure to copy the reference current output by the current source 10 into the discharging circuit 211; the first branch switch 213 includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6, where the source is grounded, the drain of the fourth NMOS transistor N4 is connected to the source of the first NMOS transistor N1, the gate of the fourth NMOS transistor N4 is connected to the gate of the fifth NMOS transistor N5, the drain of the fifth NMOS transistor N5 is connected to the source of the second NMOS transistor N2, the gate of the sixth NMOS transistor N6 receives the pull-down pulse signal down, and the drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3, where both the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are normally-on switches to ensure symmetry of the first charge-discharge branch 21, and the sixth NMOS transistor N6 is a control switch that controls whether the discharge circuit 211 is turned on or not by the pull-down pulse signal down.
With continued reference to fig. 5, the second charge-discharge branch 22 includes a charging circuit 222 and a second branch switch 224, the charging circuit 222 is connected to the current source 10, and the second branch switch 224 is connected between the second power voltage AVDD2 and the charging circuit 222 and is controlled by the pull-up pulse signal up to charge the charging circuit 222.
Further alternatively, as shown in fig. 6, the charging circuit 222 includes a first PMOS transistor P1 and a second PMOS transistor P2 that are co-gated, where a drain of the first PMOS transistor P1 is connected to a drain of the second NMOS transistor N2 and a gate of the first PMOS transistor P1, and a drain of the second PMOS transistor P2 is connected to a drain of the third NMOS transistor N3, that is, the charging circuit 222 adopts a current mirror structure to copy the reference current output by the current source 10 into the charging circuit 222; the second branch switch 224 includes a third PMOS transistor and a fourth PMOS transistor, sources of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the second power voltage AVDD2, a drain of the third PMOS transistor P3 is connected to a source of the first PMOS transistor P1, a gate of the third PMOS transistor P3 is grounded, a gate of the fourth PMOS transistor P4 receives the pull-up pulse signal up, a drain of the fourth PMOS transistor P4 is connected to a source of the second PMOS transistor P2, wherein the third PMOS transistor P3 is a normally-on switch to ensure symmetry of the second charge and discharge branch 22, and the fourth PMOS transistor P4 is a control switch to control whether the charging circuit 222 is turned on or not by the pull-up pulse signal up.
In some embodiments, as shown in fig. 5 and 6, the charge pump further comprises:
The first selection circuit 50, the first selection circuit 50 includes a first switching tube S1 and a second switching tube S2;
The first switch tube S1 is connected to the output end of the charge pump and is used for being turned on or off according to a control signal so as to control the output signal Vcont of the charge pump to the voltage-controlled oscillator;
The second switching tube S2 is connected between the output terminal of the charge pump and the adaptive adjusting circuit 30, and is used for being turned on or turned off according to the control signal, so as to input the output voltage signal Vcont of the charge pump to the adaptive adjusting circuit 30.
In the embodiment of the present application, the first selection circuit 50 is configured to input the output voltage signal Vcont of the charge pump to the adaptive adjustment circuit 30 in a specific stage, so that the adaptive adjustment circuit 30 feedback adjusts the output of the charge pump to eliminate the current mismatch problem of the charge pump, thereby realizing the requirement of low spurious output of the charge pump.
In some embodiments, referring to fig. 6 and 7, adaptive adjustment circuit 30 includes:
A booster circuit 31, the booster circuit 31 being configured to output a reference voltage VH; it is understood that the reference voltage VH and the first power supply voltage AVDD exhibit a proportional relationship, for example, VH is twice AVDD.
A power switch 32 connected to the booster circuit 31, the voltage of the output terminal of which varies with the voltage variation of the controlled terminal; optionally, the power switch 32 may be an NMOS or PMOS, and in the embodiment of the present application, the power switch 32 is an NMOS, that is, the voltage at the output end and the voltage at the controlled end of the power switch are regularly changed in positive correlation;
The comparison circuit 33 is connected with the boost circuit 31 and the power switch 32, and receives an output voltage signal Vcont of the charge pump, and is used for feedback regulating the voltage of the output end of the power switch 32 according to the voltage of the output end of the power switch 32 and the output voltage signal Vcont of the charge pump;
The second selection circuit 34 has one end connected to the first power voltage AVDD and the other end connected to the output end of the power switch 32, and is configured to selectively output the first power voltage AVDD or the voltage at the output end of the power switch 32 as the second power voltage AVDD2 according to the control signal.
Specifically, as shown in fig. 8, the comparison circuit 33 includes:
The voltage sampling circuit 331 includes a first sampling resistor R1 and a second sampling resistor R2, where a first end of the first sampling resistor R1 is connected to an output end of the power switch 32, a second end of the first sampling resistor R1 and a first end of the second sampling resistor R2 are commonly connected to form a signal output end of the voltage sampling circuit 331, and a second end of the second sampling resistor R2 is grounded;
The comparator 332 receives the output voltage signal Vcont of the charge pump at its non-inverting input, and outputs a comparison voltage to the power switch 32 at its inverting input connected to the output of the voltage sampling circuit 331.
In the embodiment of the application, the comparator 332 is used for comparing the output voltage signal Vcont of the charge pump with the voltage of the output end of the power switch 32, feeding back the comparison voltage to the controlled end of the power switch 32, further regulating the voltage of the output end of the power switch 32, and outputting the regulated voltage of the output end of the power switch 32 as the second power supply voltage AVDD2 in a specific stage, wherein in the circuit design, the voltage value of the second power supply voltage AVDD2 is 2 times of the output voltage signal Vcont of the charge pump, so that the second PMOS transistor P2 is ensured to be identical with the Vds of the third NMOS transistor N3, and on the basis, the MOS transistor size of the current mirror in the charge pump is designed, so that the lambda coefficient is ensured to be identical, thereby the problem of current mismatch of the charge pump can be eliminated, and the requirement of low output spurious of the charge pump is realized.
In some embodiments, as shown in fig. 8, the second selection circuit 34 includes a third switching tube S3 and a fourth switching tube S4, where one end of the third switching tube S3 is connected to the first power voltage AVDD, and the other end is used as an output end to output the first power voltage AVDD as the second power voltage AVDD2 in the on state, and one end of the fourth switching tube S4 is connected to the output end of the power switch 32, and the other end is used as an output end to output the output voltage of the output end of the power switch 32 as the second power voltage AVDD2 in the on state. In other embodiments, the second selection circuit 34 may be a data selector, a first input terminal thereof is connected to the first power voltage AVDD, a second input terminal thereof is connected to the output terminal of the power switch 32, and a control terminal thereof receives the data selection signal to output the first power voltage AVDD or the output terminal voltage of the power switch 32 as the second power voltage AVDD 2. In the present application, the second selection circuit 34 may be designed according to practical situations, and is not limited herein.
Referring to fig. 6, 8 and 9, fig. 9 is a schematic diagram of a switch tube control signal in a charge pump; wherein the charge pump comprises three control phases;
in a first control stage T1, a first switching tube S1 and a third switching tube S3 are conducted, a second switching tube S2 and a fourth switching tube S4 are disconnected, a loop of a charge pump is pre-locked, and output frequency is stable;
In the second control stage T2, the second switching tube S2 and the third switching tube S3 are turned on, the first switching tube S1 and the fourth switching tube S4 are turned off to introduce the output voltage signal Vcont of the charge pump to the comparison circuit 33, and the comparison circuit 33 feedback-adjusts the voltage of the output end of the power switch 32 according to the voltage of the output end of the power switch 32 and the output voltage signal Vcont of the charge pump;
in the third control stage T3, the first switching tube S1 and the fourth switching tube S4 are turned on, the second switching tube S2 and the third switching tube S3 are turned off, so that the adaptive adjustment circuit 30 uses the voltage at the output end of the power switch 32 as the second power voltage AVDD2, and at this time, the second power voltage AVDD2 is twice the output voltage signal Vcont value of the charge pump, and outputs the second power voltage AVDD2 to the second charge-discharge branch 22 to adjust the charge current and the discharge current of the charge pump, and further adjusts and outputs the output voltage signal Vcont of the charge pump.
In the embodiment of the application, the voltage value of the second power supply voltage AVDD2 should be twice the output voltage signal Vcont of the charge pump, so as to ensure that Vds of the second PMOS transistor P2 and Vds of the third NMOS transistor N3 are the same, on the basis, the MOS transistor size of the current mirror in the charge pump is designed, so as to ensure that the lambda coefficient is the same, at the moment, the adaptive adjusting circuit 30 is used for supplying power to the charge and discharge branch, and adjusts and outputs the output voltage signal Vcont of the charge pump, thereby eliminating the problem of current mismatch of the charge pump, and realizing the requirement of low output spurious of the charge pump.
The application also provides a phase locked loop comprising:
The phase frequency detector outputs a pull-up pulse signal and a pull-down pulse signal based on the phase difference and the frequency difference of the reference clock signal and the feedback clock signal; the charge pump is connected with the phase frequency detector, an adaptive regulating circuit is arranged in the charge pump, corresponding charging current or discharging current is output based on a pull-up pulse signal or a pull-down pulse signal, and an output voltage signal of the charge pump is output based on the charging current or the discharging current; the voltage-controlled oscillator is connected with the charge pump and outputs a clock signal based on an output voltage signal of the charge pump; and one end of the frequency divider is connected with the voltage-controlled oscillator, and the other end of the frequency divider is connected with the phase frequency detector so as to divide the clock signal output by the voltage-controlled oscillator and then output a feedback clock signal to the phase frequency detector.
The phase-locked loop of the application arranges the self-adaptive regulating circuit in the charge pump, and introduces the output voltage signal of the charge pump into the self-adaptive regulating circuit, so as to regulate the charge current and the discharge current of the charge pump through the self-adaptive regulating circuit, thereby eliminating the current mismatch problem of the charge and discharge circuit in the charge pump, realizing the low spurious output requirement of the charge pump, and further improving the working efficiency of the phase-locked loop.
The foregoing is a further detailed description of the utility model in connection with the preferred embodiments, and it is not intended that the utility model be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the utility model, and these should be considered to be within the scope of the utility model.
Claims (10)
1. A charge pump for a phase locked loop circuit that outputs a voltage signal based on a discharge current and a charge current, the charge pump comprising:
the current source is connected to the first power supply voltage and is used for providing reference current for the first charge and discharge branch circuit and the second charge and discharge branch circuit;
One end of the first charge-discharge branch is grounded and controlled by a pull-down pulse signal to output the discharge current;
The second charge-discharge branch is connected between the first charge-discharge branch and the second power supply voltage and controlled by a pull-up pulse signal to output the charging current;
The loop filter is connected with the first charge-discharge branch circuit and the second charge-discharge branch circuit, and the voltage output end of the loop filter forms the output end of the charge pump and is used for outputting an output voltage signal of the charge pump according to the charge current or the discharge current;
The self-adaptive adjusting circuit is connected between the output end of the charge pump and the second charge-discharge branch circuit and is used for outputting the second power supply voltage to the second charge-discharge branch circuit according to the output voltage signal of the charge pump so as to adjust the output voltage signal of the charge pump and output the second power supply voltage.
2. The charge pump of claim 1, wherein,
The first charge and discharge branch circuit comprises a discharge circuit and a first branch switch, the discharge circuit is connected with the current source, and the first branch switch is connected between the ground and the discharge circuit and is controlled by the pull-down pulse signal to discharge the discharge circuit;
The second charge-discharge branch circuit comprises a charging circuit and a second branch switch, the charging circuit is connected with the current source, the second branch switch is connected between the second power supply voltage and the charging circuit, and is controlled by the pull-up pulse signal to charge the charging circuit.
3. The charge pump of claim 2, wherein the discharge circuit comprises a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor that are co-gated, a drain of the first NMOS transistor being connected to the current source and a gate of the first NMOS transistor, a drain of the second NMOS transistor and a drain of the third NMOS transistor being connected to the charge circuit;
The first branch switch comprises a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the source electrode of the fourth NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the sixth NMOS tube receives the pull-down pulse signal, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the third NMOS tube.
4. The charge pump of claim 3, wherein the charge circuit comprises a first PMOS transistor and a second PMOS transistor that are co-gated, a drain of the first PMOS transistor being connected to a drain of the second NMOS transistor and to a gate of the first PMOS transistor, a drain of the second PMOS transistor being connected to a drain of the third NMOS transistor;
The second branch switch comprises a third PMOS tube and a fourth PMOS tube, the sources of the third PMOS tube and the fourth PMOS tube are connected with the second power supply voltage, the drain electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube, the grid electrode of the third PMOS tube is grounded, the grid electrode of the fourth PMOS tube receives a pull-up pulse signal, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube.
5. The charge pump of claim 1, wherein the charge pump further comprises:
The first selection circuit comprises a first switching tube and a second switching tube;
The first switch tube is connected to the output end of the charge pump and is used for being turned on or off according to a control signal so as to output an output voltage signal of the charge pump to the voltage-controlled oscillator;
the second switch tube is connected between the output end of the charge pump and the self-adaptive regulating circuit and is used for being turned on or off according to a control signal so as to input an output voltage signal of the charge pump to the self-adaptive regulating circuit.
6. The charge pump of any of claims 1-5, wherein the adaptive regulation circuit comprises:
a booster circuit for outputting a reference voltage;
The power switch is connected with the boost circuit, and the voltage of the output end of the power switch changes along with the voltage change of the controlled end;
The comparison circuit is connected with the boost circuit and the power switch, receives the output voltage signal of the charge pump and is used for feeding back and adjusting the voltage of the output end of the power switch according to the voltage of the output end of the power switch and the output voltage signal of the charge pump;
And one end of the second selection circuit is connected with the first power supply voltage, and the other end of the second selection circuit is connected with the output end of the power switch and is used for selectively outputting the first power supply voltage or the voltage of the output end of the power switch according to a control signal so as to serve as the second power supply voltage.
7. The charge pump of claim 6, wherein the comparison circuit comprises:
the voltage sampling circuit comprises a first sampling resistor and a second sampling resistor, wherein the first end of the first sampling resistor is connected with the output end of the power switch, the second end of the first sampling resistor and the first end of the second sampling resistor are commonly connected to form the signal output end of the voltage sampling circuit, and the second end of the second sampling resistor is grounded;
And the non-inverting input end of the comparator receives the output voltage signal of the charge pump, the inverting input end of the comparator is connected with the output end of the voltage sampling circuit, and the output end of the comparator outputs comparison voltage to the controlled end of the power switch.
8. The charge pump of claim 6, wherein the second selection circuit comprises a third switching tube and a fourth switching tube, one end of the third switching tube is connected to the first power supply voltage, the other end of the third switching tube is used as an output end to output the first power supply voltage as the second power supply voltage in a conducting state, one end of the fourth switching tube is connected to the output end of the power switch, and the other end of the fourth switching tube is used as an output end to output the output voltage of the output end of the power switch as the second power supply voltage in the conducting state.
9. The charge pump of claim 6, wherein the power switch is an NMOS transistor; or the power switch is a PMOS tube.
10. A phase locked loop circuit comprising:
The phase frequency detector outputs a pull-up pulse signal and a pull-down pulse signal based on the phase difference and the frequency difference of the reference clock signal and the feedback clock signal;
The charge pump of any of claims 1-9, coupled to the phase frequency detector, outputting a respective charge current or discharge current based on the pull-up pulse signal or pull-down pulse signal, and outputting an output voltage signal of the charge pump based on the charge current or discharge current;
A voltage-controlled oscillator connected to the charge pump, and outputting a clock signal based on an output voltage signal of the charge pump;
and one end of the frequency divider is connected with the voltage-controlled oscillator, and the other end of the frequency divider is connected with the phase frequency detector so as to divide the frequency of the clock signal output by the voltage-controlled oscillator and then output the feedback clock signal to the phase frequency detector.
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN222016532U true CN222016532U (en) | 2024-11-15 |
Family
ID=
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6121805A (en) | Universal duty cycle adjustment circuit | |
| US6377129B1 (en) | Programmable relaxation oscillator | |
| US6147561A (en) | Phase/frequency detector with time-delayed inputs in a charge pump based phase locked loop and a method for enhancing the phase locked loop gain | |
| US7349514B2 (en) | Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector | |
| CN109639272B (en) | Self-adaptive broadband phase-locked loop circuit | |
| US20030042985A1 (en) | Phase synchronizing circuit | |
| EP0416840A2 (en) | Phase locked loop circuit with digital control | |
| US7443254B2 (en) | Relaxation oscillator with propagation delay compensation for improving the linearity and maximum frequency | |
| US6624706B2 (en) | Automatic bias adjustment circuit for use in PLL circuit | |
| US7292079B2 (en) | DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner | |
| JPH1168559A (en) | Phase-locked loop circuit | |
| JP5153789B2 (en) | Phase shift processing in delay locked loop / phase locked loop | |
| US6529084B1 (en) | Interleaved feedforward VCO and PLL | |
| US5710527A (en) | Complementary voltage to current conversion for voltage controlled oscillator | |
| US20070030081A1 (en) | Voltage controlled oscillator with duty correction | |
| CN222016532U (en) | Charge pump and phase-locked loop circuit | |
| CN108123715B (en) | Frequency multiplier circuit | |
| CN112953527B (en) | Quick locking phase-locked loop structure and electronic equipment | |
| CN116566387A (en) | Phase-locked loop circuit and clock generator | |
| US20040070458A1 (en) | Interleaved vco with balanced feedforward | |
| US7834666B2 (en) | Voltage divider having varied output levels depending on frequency and PLL including the same | |
| US7002382B2 (en) | Phase locked loop circuit | |
| KR102418077B1 (en) | Injection-locked PLL architecture using sub-sampling-based frequency tracking loop and delay locked loop | |
| Zhang et al. | A process compensated 3-GHz ring oscillator | |
| Bhardwaj et al. | A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant |