KR102418077B1 - Injection-locked PLL architecture using sub-sampling-based frequency tracking loop and delay locked loop - Google Patents

Abstract

In accordance with the present invention, disclosed is an injection-locked phase locked loop employing subsampling-based FTL and DLL. In accordance with the present invention, an injection-locked phase locked loop includes: a voltage control oscillator; a dual edge injection pulse generator supplying an injection pulse to the voltage control oscillator; a subsampling-based frequency tracking loop including a first subsampling charge pump and a divider-phase frequency detector/charge pump (PFD/CP) having a dead zone, and sampling a signal outputted from the voltage control oscillator with a reference signal and an injection pulse; and a subsampling-based delay fixed loop including a second subsampling charge pump and inputting a control voltage into the voltage control oscillator. Therefore, the present invention is capable of embodying excellent in-band noise characteristics.

Description

Injection-locked PLL architecture using sub-sampling-based frequency tracking loop and delay locked loop

The present invention relates to an injection-locked phase-locked loop to which subsampling-based FTL and DLL are applied, and more particularly, FTL (frequency tracking loop) and DLL operating based on subsampling in an injection-locked PLL (ILPLL) structure (delay-locked loop) is applied to the circuit.

Most SoCs, such as microprocessors and wireless communication systems, use multiple frequency synthesizers. PLL (Phase Locked Loop) is the most commonly used frequency synthesizer thanks to its characteristics that it can be easily implemented with low power and has a wide frequency range. However, since large power consumption or area is generally required for excellent noise performance, many studies are being conducted to solve this problem.

Sub-sampling PLL (SSPLL) and Injection-locked PLL (ILPLL) are the structures that have been studied the most recently.

First, the SSPLL can synthesize frequencies without a divider that divides the frequency by N in the feedback loop, unlike the conventional PLL having a phase frequency detector/charge pump (PFD/CP).

In the phase frequency detector/charge pump, the noise of the charge pump is amplified by N ² times due to the frequency divider and becomes a dominant component in the in-band noise, but since the SSPLL does not use a frequency divider, excellent in-band noise performance can be obtained. However, since there is a limitation that out-band noise cannot be improved, an inductor-based oscillator that requires a very large area has no choice but to use for excellent noise characteristics.

The ILPLL reduces the noise of the voltage-controlled oscillator by periodically initializing the accumulated jitter of the voltage-controlled oscillator (VCO) through the reference signal with the lowest noise characteristic in the system. Therefore, when ILPLL is used, excellent noise performance can be obtained even if a ring oscillator using only a small area is used.

However, ILPLL has excellent noise characteristics only when the frequency/phase difference between the injection pulse and the voltage-controlled oscillator is very small. There is a problem that it is very sensitive to change.

In order to utilize the excellent noise characteristics of the ILPLL, many studies are being conducted to solve the frequency/phase difference between the voltage-controlled oscillator and the injection pulse. A frequency tracking loop (FTL) with a PFD/CP PLL is commonly used to match the frequency, but the frequency divider present in the feedback loop limits the in-band noise performance. Additionally, since a technology having a structure different from that of the FTL such as a bang-bang phase detector is used to compensate for the phase, circuit complexity and power consumption increase.

Republic of Korea Patent Publication No. 10-2015-0089770

In order to solve the problems of the prior art, the present invention intends to propose an injection-locked phase-locked loop to which subsampling-based FTL and DLL are applied with excellent in-band noise characteristics and insensitive to external environment changes.

In order to achieve the above object, according to an embodiment of the present invention, a voltage controlled oscillator; a dual edge injection pulse generator for supplying injection pulses to the voltage controlled oscillator; Subsampling-based frequency tracking including a first subsampling charge pump and a divider-PFD/CP (phase frequency detector/charge pump) having a dead zone and sampling a signal output from the voltage controlled oscillator as a reference signal and an injection pulse loop; and a second subsampling charge pump, the injection-locked phase locked loop including a subsampling-based delay locked loop for inputting a control voltage to the voltage controlled oscillator is provided.

The voltage controlled oscillator includes a plurality of delay cells and a sampler, and each of the plurality of delay cells drives one sampler and two delay cells.

The voltage-controlled oscillator includes a plurality of dummy samplers operating in a phase opposite to that of each of the plurality of samplers.

The subsampling-based frequency tracking loop and the subsampling-based delay locked loop include an isolation buffer for separating a sampling capacitor included in a sampler of the voltage controlled oscillator.

An input capacitance of the first subsampling charge pump has twice the capacitance of the plurality of delay cells.

The dual edge injection pulse generator may further include a duty correction circuit configured to generate the injection pulse at rising and falling edges of the reference signal and disposed in front of the dual edge injection pulse generator to prevent a duty error.

An injection-locked phase-locked loop comprising: a voltage controlled oscillator comprising a plurality of delay cells, a plurality of samplers, and a plurality of dummy samplers; a dual edge injection pulse generator for supplying injection pulses to the voltage controlled oscillator; Subsampling-based frequency tracking including a first subsampling charge pump and a divider having a dead zone-PFD/CP (phase frequency detector/charge pump) and sampling a signal output from the voltage controlled oscillator as a reference signal and an injection pulse loop; and a subsampling-based delay locked loop including a second subsampling charge pump and inputting a control voltage to the voltage controlled oscillator, wherein each of the plurality of delay cells drives one sampler and two delay cells, and An injection-locked phase-locked loop is provided in which the plurality of dummy samplers operate out of phase with the plurality of samplers.

According to the present invention, there is an advantage in that excellent in-band noise characteristics can be implemented through the subsampling-based frequency tracking loop and the delay locked loop.

1 is a block diagram of an injection-locked phase-locked loop according to a preferred embodiment of the present invention.
2 is a diagram showing the configuration of a voltage controlled oscillator according to an embodiment of the present invention.
3 is a diagram showing a timing diagram of the voltage controlled oscillator according to the present embodiment.
4 is a diagram showing the configuration of the duty correction circuit and the dual edge injection pulse generator according to the present embodiment.
5 is a diagram illustrating a linear phase domain model of an ILPLL according to the present embodiment.
6 to 7 are diagrams illustrating simulation and measurement results of the ILPLL according to the present embodiment.

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail.

However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

1 is a block diagram of an injection-locked phase-locked loop according to a preferred embodiment of the present invention.

As shown in FIG. 1, the injection-locked phase-locked loop (hereinafter referred to as 'ILPLL') according to the present embodiment is a sub-sampling-based frequency tracking loop that is two loops. Tracking Loop 100, hereinafter referred to as 'SSFTL') and a sub-sampling-based Delay Locked Loop (102, hereinafter, referred to as 'SSDLL') may be included.

The SSFTL 100 includes a first pulse generator 110, a first sub-sampling charge pump 112, hereinafter referred to as a 'first SSCP'), a loop filter (Loop Filter, LF, 114), and A divider-PFD/CP 116 may be included.

According to this embodiment, since the first SSCP 112 of the SSFTL 100 samples the output signal of the voltage controlled oscillator as a reference signal, unlike the conventional PFD/CP, a frequency divider is not required, and the first SSCP ( 112) does not ^double by N.

However, at this time, since the output of the voltage controlled oscillator 104 , which is the input of the first SSCP 112 , is a sine wave, the input/output characteristics are not linear, and thus the frequency capture range is narrowed.

A divider-PFD/CP 116 having a dead zone (DZ) is included to overcome a narrow frequency capture ragne of the SSFTL 100 , which is deactivated after the frequency is fixed.

Also, the SSDLL 102 may include a pulse generator 120 , a second subsampling charge pump SSCP 122 , and a false delay cell 124 .

The first and second pulse generators 110/120 adjust the gains of the SSFTL 100 and the SSDLL 102 .

The variable delay cell 124 is controlled by the second subsampling charge pump 122 of the SSDLL 102 and adjusts the phase of the SSFTL 100 .

Three outputs having different phases of the voltage controlled oscillator 104 are input to the SSFTL 100 and the SSDLL 102 .

In the present invention, the SSFTL 100 is applied to the ILPLL to solve the problem that in-band noise is amplified, and the SSDLL 102 is also applied to solve the phase difference.

However, if the subsampling technique is used, accurate phase information cannot be obtained due to the delay of the sampler consisting of a buffer, a sampling switch, and a sampling capacitor.

Accordingly, the present invention provides a three-stage ring voltage controlled oscillator including a dummy sampler.

2 is a diagram showing the configuration of a voltage controlled oscillator according to an embodiment of the present invention.

Referring to FIG. 2 , in the voltage controlled oscillator 104 according to the present embodiment, a variable capacitor is used as a sampling capacitor and a sampling switch is also disposed inside the voltage controlled oscillator 104 .

Additionally, all delay cells drive one sampler and two delay cells to obtain accurate phase information. In addition, a dummy sampler operating in the opposite phase to the sampler is added to prevent modulation of the frequency of the voltage-controlled oscillator due to parasitic components.

The output of the voltage-controlled oscillator 104 is sampled by the reference Ref and the injection pulse Inj in order to mitigate the in-band noise and correct the phase offset.

When the sampling capacitor is periodically connected to the voltage controlled oscillator 104, the load capacitance of the delay cell is changed.

Since the output frequency f _VCO of the voltage controlled oscillator 104 is a delay function of the unit delay cell, f _VCO is modulated by the reference and injection pulses.

An isolation buffer is used to isolate the sampling capacitor from the voltage controlled oscillator 104 . Since the sampling capacitor still affects f _VCO due to the input and output parasitic coupling of the delay cell regardless of the isolation buffer, a dummy sampler, which operates opposite to the reference and injection pulses, is also incorporated into each stage of the voltage controlled oscillator 104 . The use of an isolation buffer can effectively prevent the periodic connection of the sampling capacitor, but the delay of the isolation buffer prevents the correct phase from being obtained.

In the voltage controlled oscillator 104, a variable capacitor is generally used to implement a frequency that varies depending on the control voltage VC. A sampling capacitor is used as a variable capacitor sharing the same VC and a sampling switch is placed in the voltage controlled oscillator 104 to match the delay of the isolation buffer and delay cell.

As described above, since all delay cells drive one sampler and two delay cells, the input capacitance of the first SSCP 112 should be designed to be twice the capacitance of the delay cell. Current mode logic with limited voltage range is also used as only PMOS sampling switches are used to minimize the load on the delay cell. According to the timing diagram of FIG. 3 , VCO _P and VCO _N are sampled by reference and injection pulses, and the phase difference is converted into a voltage difference between VCO _PS and VCO _NS . Thereafter, the first SSCP 112 charges or discharges VC and VC_DLL according to PUL _FTL and PUL _DLL . t _set and t _margin are also added to ensure settling time and isolate SSCP from track mode.

The ILPLL according to the present embodiment includes a duty compensation circuit (DCC, 130) and a dual edge injection pulse generator (DE Inj Gen. 132).

The dual edge injection pulse generator 132 generates short injection pulses Inj at the rising and falling edges of the reference.

If there is a duty error in the dual-edge injection, the phase error between the rise and fall will result in additional spur and noise performance degradation. In order to prevent such a duty error, a duty correction circuit 130 is provided at the front end of the dual edge injection pulse generator 132 .

The injection pulse initializes the accumulated jitter of the voltage controlled oscillator 104 and samples the phase difference between the injection pulse and the voltage controlled oscillator 104 output.

4 is a diagram showing the configuration of the duty correction circuit and the dual edge injection pulse generator according to the present embodiment.

As shown in Figure 4a, a 6-bit duty correction circuit can be used to prevent additional jitter and spurs from occurring due to duty cycle errors due to PVT fluctuations and the common mode voltage at Ref.

Here, the duty correction circuit 130 may include a self-bias inverter and a current source.

The input coupling capacitor of the duty correction circuit 130 is not affected by the common mode voltage of Ref. By adjusting the pull-up/down current source, the duty cycle is controlled with a 6-bit off-chip signal.

In the duty correction circuit 130, an XOR gate is typically used to generate short pulses on rising and falling. However, the output path of XOR depends on the combination of the two inputs, which can also degrade performance.

Accordingly, a multiplexer-based injection pulse generator may be used as shown in FIG. 4B.

Referring to Figure 4b, the single-ended Ref is converted to a differential signal. The NAND then generates short pulses on rising/falling. The pulse width of Inj is determined by the inverter delay before the NAND. The output of the NAND is selected by the transfer gate. The delay mismatch in the two different paths may be corrected by the duty correction circuit 130 .

5 is a diagram illustrating a linear phase domain model of an ILPLL according to the present embodiment.

의 전달함수(transfer function)을 살펴보면 기존의 ILPLL보다 우수한 노이즈 성능을 나타내는 것을 알 수 있다. 또한 SSDLL(102)의 대역폭이 상대적으로 느리게 설계되었기 때문에 SSDLL(102)에 제2 서브샘플링 전하펌프(122)가 추가되었음에도 불구하고 추가된 노이즈인

가 출력에 영향을 미치지 않는다는 것을 알 수 있다. As mentioned earlier, there is no frequency divider in the feedback loop. CP noise that has the greatest effect on in-band noise

Looking at the transfer function of , it can be seen that the noise performance is superior to that of the conventional ILPLL. In addition, since the bandwidth of the SSDLL 102 is designed to be relatively slow, the added noise is

It can be seen that does not affect the output.

In order to verify the superiority of the ILPLL structure according to this embodiment, a prototype operating at 3.2 GHz was manufactured using a 65 nm CMOS process.

6 to 7 are diagrams illustrating simulation and measurement results of the ILPLL according to the present embodiment.

6 to 7, compared to the conventional ILPLL using the PFD/CP FTL, the phase noise performance improvement effect of 8.6 dB at 10 kHz offset was improved, and the rms jitter was improved by 26.4% from 242 fs to 178 fs. In addition, to verify the performance of SSDLL, a total of 20 tenses were measured. When SSDLL is enabled, the average rms jitter is 186.1 fs, which is 17.4% better than 225.2 fs when SSDLL is disabled, confirming that SSDLL is successfully compensating for the phase difference.

The above-described embodiments of the present invention have been disclosed for purposes of illustration, and various modifications, changes, and additions will be possible within the spirit and scope of the present invention by those skilled in the art having ordinary knowledge of the present invention, and such modifications, changes and additions should be regarded as belonging to the following claims.

Claims (7)

An injection-locked phase-locked loop comprising:
voltage controlled oscillator;
a dual edge injection pulse generator for supplying an injection pulse to the voltage controlled oscillator;
Subsampling-based frequency tracking including a first subsampling charge pump and a divider-PFD/CP (phase frequency detector/charge pump) having a dead zone and sampling a signal output from the voltage controlled oscillator as a reference signal and an injection pulse loop; and
An injection-locked phase-locked loop comprising a second subsampling charge pump and comprising a subsampling-based delay-locked loop for inputting a control voltage to the voltage-controlled oscillator. According to claim 1,
The voltage controlled oscillator includes a plurality of delay cells and a sampler,
An injection-locked phase-locked loop in which each of the plurality of delay cells drives one sampler and two delay cells. 3. The method of claim 2,
The voltage-controlled oscillator may include a plurality of dummy samplers operating in a phase opposite to that of each of the plurality of samplers. 4. The method of claim 3,
The subsampling-based frequency tracking loop and the subsampling-based delay-locked loop include an isolation buffer for separating a sampling capacitor included in a sampler of the voltage-controlled oscillator. 5. The method of claim 4,
and an input capacitance of the first subsampling charge pump is twice the capacitance of the plurality of delay cells. According to claim 1,
the dual edge injection pulse generator generates the injection pulse at rising and falling edges of the reference signal;
The injection-locked phase locked loop further comprising a duty correction circuit disposed in front of the dual edge injection pulse generator to prevent a duty error. An injection-locked phase-locked loop comprising:
a voltage controlled oscillator including a plurality of delay cells, a plurality of samplers, and a plurality of dummy samplers;
a dual edge injection pulse generator for supplying injection pulses to the voltage controlled oscillator;
Subsampling-based frequency tracking including a first subsampling charge pump and a divider having a dead zone-PFD/CP (phase frequency detector/charge pump) and sampling a signal output from the voltage controlled oscillator as a reference signal and an injection pulse loop; and
A subsampling-based delay lock loop comprising a second subsampling charge pump and inputting a control voltage to the voltage controlled oscillator,
wherein each of the plurality of delay cells drives one sampler and two delay cells, and the plurality of dummy samplers operate in an opposite phase to the plurality of samplers.

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