CN203340174U - Ultra-wide resolution VGA signal acquisition processing system - Google Patents

Abstract

The utility model discloses an ultra-wide resolution VGA signal acquisition processing system which is used for recording a computer screen content. The system comprises a VGA interface, an A/D converter, a FPGA conversion controller and an encoder, wherein the VGA interface is used for receiving an RGB simulation signal, a horizontal synchronizing signal and a field synchronizing signal and is connected with a computer; the A/D converter is used for analog-digital conversion and is connected with the VGA interface; the FPGA conversion controller is connected with the A/D converter through an I2C bus; the encoder is connected with the FPGA conversion controller. According to the utility model, the converter and the VGA encoder are used to carry out acquisition and processing on a VGA signal of the computer; a computer architecture is separated; the acquisition can be performed on a high definition video signal whose resolution can reach 2048*768 and 3072*768.

Description

A kind of super wide resolution VGA signal acquiring processing system

Technical field

The utility model relates to video recorded broadcast technical field, more specifically relates to a kind of super wide resolution VGA(Video Graphics Array, Video Graphics Array) signal acquiring processing system.

Background technology

Recording and broadcasting system finds broad application in middle and primary schools' teaching, and the process of Internet Transmission, broadcasting is recorded and synchronously carried out in recorded broadcast to teaching process.Usually need the computer screen displaying contents is gathered in the recorded broadcast process, usually can relate to the signals collecting of super wide resolution 2048 * 768 and 3072 * 768, picture materials such as the lecture notes of recording the speaker, video image and writing on the blackboard.Existing signal acquisition method generally includes following two kinds:

One, software screen capture mode

This mode is caught, is recorded by the computer screen content in teaching, image can store up into JPEG(Joint Photographic Experts Group, joint image expert group) the various forms such as, screen video can capture as AVI(Audio Video Interleaved, the Audio Video Interleaved form), WMV(Windows Media Video, a kind of stream media format that Microsoft releases) video file such as.The software screen mode of catching takies considerably less cpu resource, does not affect the operation of other programs, and picture is clear, and the record data amount is little, is applicable to Internet Transmission.Mainly the problem of existence is, the classroom computer need to be installed the seizure that recorded broadcast software is realized screen picture, therefore is limited to obtaining of this computer screen content, if classroom teaching is used notebook computer, DVD, exhibition booth, its signal can't carry out acquisition and recording.If the video file that utilizes computer playing video file or courseware to embed, catch the requirement that is difficult to reach the video frame number.

Two, hardware VGA acquisition mode

Use special-purpose recording player to realize that VGA gathers.Recording player is to utilize high-performance computer to insert video VGA capture card to form, and bears collection, the coding work of various types of signal, and classroom computer just teaching uses the recorded broadcast task of no longer bearing.Recording player is connected with the VGA output of classroom central controller, the content of synchronous recording projector demonstration, therefore, support the VGA signal such as computer, notebook computer, real object exhibition booth of access multi-media classroom and the collection of DVD vision signal, met the use of all kinds of media of whole course of teaching.The VGA capture card supports that 1024 * 768 record resolution, can obtain Phase Alternation Line system per second 25 frames, and the video pictures of NTSC～0 per second 30 frames, realize smooth videograph.Hardware mode has solved the problem that video acquisition and all kinds of media are used, but to compare data volume large with software screen capture mode, and definition is poor.

The utility model content

A kind of super wide resolution VGA signal acquiring processing system that the utility model provides, it carries out acquisition process by transducer and VGA encoder to the VGA signal of computer, broken away from computer architecture, can have been gathered up to 2048 * 768 and 3072 * 768 high-definition video signals resolution.

For reaching above purpose, the utility model provides a kind of super wide resolution VGA signal acquiring processing system, and for the computer screen content is recorded, described system comprises:

For receiving the VGA interface of RGB analog signal, line synchronizing signal and field sync signal, with described computer, be connected;

For analog-to-digital A/D converter, with described VGA interface, be connected;

The FPGA switching controller, pass through I ²the C bus is connected with described A/D converter;

Encoder, be connected with described FPGA switching controller.

According to signal acquiring processing system of the present utility model, described VGA interface comprises RGB tri-look analog signal input lines, for RGB tri-look ground wire and the timing signal lines of ground connection.

According to signal acquiring processing system of the present utility model, described A/D converter is the AD9883 chip.

According to signal acquiring processing system of the present utility model, the AD9883 chip mainly comprises A/D change-over circuit, clock and synchronous processing circuit, I ²c bus interface and register.

According to signal acquiring processing system of the present utility model, described FPGA switching controller is the EP1C3T144C8 chip.

According to signal acquiring processing system of the present utility model, described signal acquiring processing system also comprises the D/A converter be connected with described A/D converter and described FPGA switching controller.

According to signal acquiring processing system of the present utility model, described D/A converter is the ADV7123 chip.

According to signal acquiring processing system of the present utility model, described signal acquiring processing system also comprises the display be connected with described D/A converter, and described display also is connected with described A/D converter.

The utility model receives RGB analog signal, line synchronizing signal and field sync signal by the VGA interface from computer, determine line frequency and the field frequency of sampling according to row, field sync signal by A/D converter, then by line frequency and internal register, determine the pixel synchronised clock, then the phase-locked loop by configuration A/D converter inside produces synchronised clock, the digital video signal that is 8bit * 3 tunnels by the VGA analog signal conversion of input, and by the sample effect of a series of registers adjustment images; The FPGA switching controller, a square tube is crossed I ²the C bus to the register write control information of A/D converter to adjust the image sampling effect; On the other hand the rgb signal of input is converted to the YUV signal form that encoder is supported, give the encoder processing of encoding by vision signal, thereby realize the VGA signal of computer is carried out to acquisition process, and broken away from computer architecture, can have been gathered up to 2048 * 768 and 3072 * 768 high-definition video signals resolution.

The accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the utility model embodiment, in below describing embodiment, the accompanying drawing of required use is briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the system construction drawing of the super wide resolution VGA signal acquiring processing system of the utility model;

Fig. 2 is the digital video signal output timing diagram after the conversion of AD9883 chip in a kind of embodiment of the utility model;

Fig. 3 is the work block diagram that in a kind of embodiment of the utility model, the FPGA switching controller carries out color conversion;

Fig. 4 is that the VGA of FPGA switching controller in a kind of embodiment of the utility model is capable, field synchronization sequential schematic diagram.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making under the creative work prerequisite the every other embodiment obtained, and all belong to the scope of the utility model protection.

As shown in Figure 1, a kind of super wide resolution VGA signal acquiring processing system 100 of the utility model, for the computer screen content is recorded, system 100 comprises: VGA interface 10, A/D converter 20, FPGA(Field-Programmable Gate Array), field programmable gate array) switching controller 30, encoder 40, D/A converter 50 and display 60.

VGA interface 10, for receiving RGB analog signal, line synchronizing signal and field sync signal and being sent to A/D converter 20, be connected with computer and A/D converter 20.10, VGA interface is comprised of analog circuit, easily produces noise, and while therefore connecting up, interface device should be tried one's best near A/D converter 20.The VGA interface can transmit the picture formats such as VGA, SVGA, XGA, SXGA.The VGA interface has 15 lines, is divided into 3 groups, comprises RGB(Red Green Blue, RGB) three look analog signal input lines, for RGB tri-look ground wire and the timing signal lines of ground connection.Timing signal line is for being respectively line synchronizing signal line and field sync signal line, these two line traffic controls the display timing generator of VGA signal.

A/D converter 20, for the VGA signal is carried out to analog-to-digital conversion, be connected with VGA interface 10.Concrete, at first A/D converter 20 determines line frequency and the field frequency of sampling according to row, field sync signal, then by line frequency and internal register, determine the pixel synchronised clock, then the phase-locked loop by configuration A/D converter 20 inside produces synchronised clock.The digital video signal that this module can be 8bit * 3 tunnels by the VGA analog signal conversion of input, and by the sample effect of a series of registers adjustment images.

Preferably, this A/D converter 20 is the AD9883 chip, and this chip is specifically designed to and gathers simulation R, G, B signal, and its digitlization is shown or uses as the intermediate conversion device.It is 8bit * 3 paths that this chip has sampling precision, and high sampling rate is 140MSPS/s, the analog bandwidth of 300MB.While according to formula, calculating ultimate resolution 3072 * 768 times, maximum refresh rate is: maximum refresh rate=140000000/ (3072 * 768 * 1.34)=44.28, the native system acquisition refresh rate reaches 30fps and gets final product, and AD9883 satisfies the demands, thereby realizes the analog-to-digital conversion of HD video.Circuit based on the AD9883 chip can be HDTV (High-Definition Television) good interface is provided, or, as the front end scan converter of high-performance video equipment, it mainly comprises A/D change-over circuit, clock and synchronous processing circuit, register and I ²the C bus interface.After the conversion of AD9883 chip, the sequential of digital video signal output as shown in Figure 2.In sampling and the quantification of the trailing edge respective signal of data output clock DATACK, the output that the data of quantification are stable at rising edge clock; Interface circuit can latch view data exactly at the rising edge of DATACK, thereby realizes the collection of digitized image.It should be noted that the AD9883 chip has a data output channel, before the output data are effective, must empty passage, thereby cause exporting 4 groups of invalid data before every line output valid data, can avoid exporting these invalid datas by line synchronizing signal.

FPGA switching controller 30, pass through I ²the C bus is connected with A/D converter 20.Preferably, FPGA switching controller 30 is the EP1C3T144C8 chip, and it can be converted to YUV signal by the digitized rgb signal of input, gives encoder 40.FPGA switching controller 30 is usingd the pixel clock computer LK of A/D converter 20 output as the global synchronization clock.

RGB and YUV are two kinds of color spaces commonly used.Rgb color space is to adopt R, G, and tri-color components of B mean a pixel, common rgb format has RGB565, RGB555, RGB24, in native system, to change the data format of output be RGB24 to AD9883, i.e. each pixel 24 bit representations, and the RGB component is respectively used 8.Fig. 3 is the work block diagram that the FPGA switching controller carries out color conversion, and FPGA switching controller 30 is converted to the YUV signal of 16bit by the 8bit of input * 3 road rgb signals.Under the mode of operation of YUV16Bit, within a clock cycle, high eight-bit is for delivered spaced U component or V component, and least-significant byte is for transmitting the Y component.

Encoder 40, be connected with FPGA switching controller 30 for to being encoded and exporting of audio frequency and video, and its concrete implementation method describes in detail in subsequent content.

D/A converter 50, be connected with A/D converter 20 and FPGA switching controller 30.This D/A converter 50 is preferably the ADV7123 chip.It is for 8bit * 3 road RGB digital signals are reduced to analog signal, and combination is gone, field sync signal forms the VGA signal, for local display 60, shows and exports.

Display 60, be connected with D/A converter 50 and A/D converter 20.The RGB analog signal of this display is provided by D/A converter 50, and its row, field sync signal are provided by A/D converter 20.At body, display 60 being set is mainly used in this locality and watches and test.

The utility model receives RGB analog signal, line synchronizing signal and field sync signal by the VGA interface from computer, determine line frequency and the field frequency of sampling according to row, field sync signal by A/D converter, then by line frequency and internal register, determine the pixel synchronised clock, then the phase-locked loop by configuration A/D converter inside produces synchronised clock, the digital video signal that is 8bit * 3 tunnels by the VGA analog signal conversion of input, and by the sample effect of a series of registers adjustment images; The FPGA switching controller, a square tube is crossed I ²the C bus to the register write control information of A/D converter to adjust the image sampling effect; On the other hand the rgb signal of input is converted to the YUV signal form that encoder is supported, give the encoder processing of encoding by vision signal, thereby realize the VGA signal of computer is carried out to acquisition process, and broken away from computer architecture, can have been gathered up to 2048 * 768 and 3072 * 768 high-definition video signals resolution.

The Software for Design of native system mainly comprises FPGA Software for Design part and encoder Software for Design part.

The FPGA Software for Design

In the present embodiment, A/D converter 20 is that AD9883 chip, encoder 40 are the DM6447 chip.

The FPGA Software for Design is mainly realized the function of following 3 aspects:

1, I ²the C interface configuration

The register of AD9883 chip internal passes through I ²the C bus is fully able to programme, and this trifle will be told about FPGA and pass through I ²the concrete configuration of C interface to these registers.By the configuration of these design parameters, can realize the control to AD9883 video acquisition form, video conversion effect etc.

AD9883 inside is totally 25 registers, and wherein 00H and 14H are read-only register, and it is function register that 15～18H uses register, 01H～13H for test.Fpga chip is as shown in table 1 to the configuration of major function register:

Table 1

2, the conversion of RGB and YUV

Another function of FPGA switching controller 30 in native system is that rgb signal is converted to YUV signal, and the formula of the two conversion is (the RGB span is 0-255):

$\left\{\begin{array}{c}Y=0.299R+0.587G+0.114B\\ U=-0.147R-0.289G+0.436B\\ V=0.615R-0.515G-0.100B\end{array}\right.$ (formula 1)

While due to fpga chip, carrying out floating-point operation, calculation step is loaded down with trivial details and hardware resource consumption is larger, therefore round after the parameter in formula 1 all is multiplied by 256, changes as follows:

$\left\{\begin{array}{c}{Y}^{\′}=77R+150G+29B\\ U^{\′}=-38R-74G+112B\\ V^{\′}=157R-132G-26B\end{array}\right.$ (formula 2)

After computing, obtain the Y ' in formula 2, U ', after V ' component, the high eight-bit fetched data respectively is Y, U, the actual value of V component.

3, the realization of VPFE interface sequence

Due to the synchronizing signal of AD9883 chip output and the input sync signal format mismatching of DM6447 requirement, therefore synchronizing signal need to be changed.The synchronous signal cycle of AD9883 chip output comprises horizontal blanking crop, horizontal blanking back porch, synchronizing signal and four parts of view data, and actual transmissions only comprises synchronizing signal and two parts of view data to the signal of the Video processing front end of DM6447, therefore need to be changed the signal period, as shown in Figure 4.

(2) Software for Design of encoder (take the DM6447 chip as example)

This design mainly realizes modification and the video signal collective programming of Video processing front-end driven

1) modification of Video processing front-end driven

For the YUV signal after Collect conversion, native system is revised the driving of the Video processing front end of DM6447, and the mode of operation of configuration video capture device is the YUV input pattern.The main driving file of revising is DM6447_vpfe.c, and partial code is resolved as follows:

2) video signal collective programming

In the application programming of DM6447 chip, the collection of audio, video data, coding, output realize by Capture Thread, Video Thread, Writer Thread separate threads respectively.Wherein, the Main Function of video acquisition thread is that collecting device is carried out to initialization, opens up buffering area, take frame as the past wherein data writing of unit, for Video Thread prepares.

The video acquisition program is by calling V4L2(Video For Linux2) realize, V4L2 is the kernel-driven about video equipment provided in Linux, it provides a series of interface function for the application program for video equipment becomes.As VIDIOC_REQBUFS, storage allocation; VIDIOC_QUERYBUF, convert the data buffer storage distributed in VIDIOC_REQBUFS to physical address; VIDIOC_QUERYCAP, inquiry collecting device function; VIDIOC_S_FMT, arrange the Video Capture form when front wheel driving; VIDIOC_STREAMON, start video acquisition etc.Concrete methods of realizing is no longer given an example.

In sum, the utility model receives RGB analog signal, line synchronizing signal and field sync signal by the VGA interface from computer, determine line frequency and the field frequency of sampling according to row, field sync signal by A/D converter, then by line frequency and internal register, determine the pixel synchronised clock, then the phase-locked loop by configuration A/D converter inside produces synchronised clock, the digital video signal that is 8bit * 3 tunnels by the VGA analog signal conversion of input, and by the sample effect of a series of registers adjustment images; The FPGA switching controller, a square tube is crossed I ²the C bus to the register write control information of A/D converter to adjust the image sampling effect; On the other hand the rgb signal of input is converted to the YUV signal form that encoder is supported, give the encoder processing of encoding by vision signal, thereby realize the VGA signal of computer is carried out to acquisition process, and broken away from computer architecture, can have been gathered up to 2048 * 768 and 3072 * 768 high-definition video signals resolution.

Applied specific case herein principle of the present utility model and execution mode are set forth, the explanation of above embodiment is just for helping to understand core concept of the present utility model; , for one of ordinary skill in the art, according to thought of the present utility model, all will change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model simultaneously.

Claims (8)

1. a super wide resolution VGA signal acquiring processing system, for the computer screen content is recorded, is characterized in that, described system comprises:

For receiving the VGA interface of RGB analog signal, line synchronizing signal and field sync signal, with described computer, be connected;

For analog-to-digital A/D converter, with described VGA interface, be connected;

The FPGA switching controller, pass through I ²the C bus is connected with described A/D converter;

Encoder, be connected with described FPGA switching controller.

2. signal acquiring processing system according to claim 1, is characterized in that, described VGA interface comprises RGB tri-look analog signal input lines, for RGB tri-look ground wire and the timing signal lines of ground connection.

3. signal acquiring processing system according to claim 1, is characterized in that, described A/D converter is the AD9883 chip.

4. signal acquiring processing system according to claim 1, is characterized in that, the AD9883 chip mainly comprises A/D change-over circuit, clock and synchronous processing circuit, I ²c bus interface and register.

5. signal acquiring processing system according to claim 1, is characterized in that,

Described FPGA switching controller is the EP1C3T144C8 chip.

6. signal acquiring processing system according to claim 1, is characterized in that, described signal acquiring processing system also comprises the D/A converter be connected with described A/D converter and described FPGA switching controller.

7. signal acquiring processing system according to claim 6, is characterized in that, described D/A converter is the ADV7123 chip.

8. signal acquiring processing system according to claim 6, is characterized in that, described signal acquiring processing system also comprises the display be connected with described D/A converter, and described display also is connected with described A/D converter.

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