CN118073204A - Method for forming semiconductor NMOS device with dislocation structure - Google Patents

Method for forming semiconductor NMOS device with dislocation structure Download PDF

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Publication number
CN118073204A
CN118073204A CN202410224493.0A CN202410224493A CN118073204A CN 118073204 A CN118073204 A CN 118073204A CN 202410224493 A CN202410224493 A CN 202410224493A CN 118073204 A CN118073204 A CN 118073204A
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forming
ion implantation
region
substrate
implantation
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张强强
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202410224493.0A priority Critical patent/CN118073204A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The invention provides a method for forming a semiconductor NMOS device with a dislocation structure, which comprises the steps of providing a substrate, wherein a grid structure or a pseudo grid structure is formed on the substrate; forming a first side wall on the side wall of the grid structure or the pseudo grid structure, and then forming a lightly doped drain by utilizing ion implantation; forming a second side wall on the first side wall, and then forming a source region and a drain region by utilizing ion implantation; performing a first preamorphization ion implantation on the NMOS region on the substrate to form a first amorphization region; performing a second preamorphization ion implantation at least once to the NMOS region on the substrate at a different ion implantation angle to form a second amorphized region such that the amorphous layer width of the (111) crystal plane increases; the first and second amorphized regions are recrystallized and dislocations formed by annealing. The invention can form a semiconductor device with more obvious dislocation structure, improve carrier mobility and improve device performance.

Description

Method for forming semiconductor NMOS device with dislocation structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor NMOS device with a dislocation structure.
Background
In the back gate process, removing the dummy gate eliminates the high stress applied by the gate to the channel, thus enhancing NMOS performance by enhancing the S/D SMT (source drain tombstoning) effect.
The current method is to implant high-energy heavy ions into the S/D region to form an amorphous layer, and to cover the oxide layer and the high-stress SIN by adopting the conventional stress memory technology to perform S/D activation. In the solid phase epitaxial growth process, the crystal face growth rate (001) > (110) > (111), and finally crystal face defects are formed in (111). The defect can enhance the tensile stress of the S/D region and the channel region, improve the carrier mobility and further improve the NMOS performance.
The process is extended to 22nm technology node, the applicability of the method is lower, mainly because the distance between polysilicon is obviously reduced, the formed PAI (preamorphization) area is reduced, dislocation is difficult to form, and the effect is not obvious.
In order to solve the above problems, a new method for forming a semiconductor NMOS device with dislocation structure is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for forming a semiconductor NMOS device with a dislocation structure, which is used to solve the problem that the formation of a PAI (pre-amorphization) region is reduced and the dislocation is difficult to form due to the significantly reduced distance between polysilicon in the prior art.
To achieve the above and other related objects, the present invention provides a method for forming a semiconductor NMOS device having a dislocation structure, comprising:
step one, providing a substrate, wherein a grid structure or a pseudo grid structure is formed on the substrate;
Forming a first side wall on the side wall of the grid structure or the pseudo grid structure, and then forming a lightly doped drain by utilizing ion implantation; forming a second side wall on the first side wall, and then forming a source region and a drain region by utilizing ion implantation;
Step three, performing first preamorphization ion implantation on the NMOS region on the substrate to form a first amorphization region;
Step four, performing at least one second preamorphization ion implantation to the NMOS region on the substrate at different ion implantation angles to form a second amorphization region, so that the width of the amorphous layer of the (111) crystal face is increased;
And fifthly, recrystallizing the first amorphized region and the second amorphized region by annealing and forming dislocation.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the ion implantation angle of the first pre-amorphization ion implantation in the third step is 0-7 °.
Preferably, the process conditions of the first pre-amorphization ion implantation in the third step further include: the implantation ions comprise at least one of Ge, si and Xe, the implantation energy is 10 KeV-60 KeV, the implantation dosage is 1E 13-1E 15/cm2, and the implantation temperature is-100-25 ℃.
Preferably, the ion implantation angle of the second preamorphization ion implantation in the fourth step is 7-45 °.
Preferably, the number of times of the second pre-amorphization ion implantation in the fourth step is one.
Preferably, the process conditions of the second pre-amorphization ion implantation in the fourth step further include: the implantation ions comprise at least one of Ge, si and Xe, the implantation energy is 30 KeV-90 KeV, the implantation dosage is 1E 13-1E 15/cm2, and the implantation temperature is-100 ℃ to 25 ℃.
Preferably, the annealing in the fifth step is a rapid thermal annealing, millisecond thermal annealing, microsecond thermal annealing, spike annealing or furnace tube annealing process.
Preferably, the annealing temperature in step five is 600-1100 ℃.
As described above, the method for forming the semiconductor NMOS device with the dislocation structure has the following beneficial effects:
the invention can form a semiconductor device with more obvious dislocation structure, improve carrier mobility and improve device performance.
Drawings
FIG. 1 is a schematic illustration of the process flow of the present invention;
FIG. 2 is a schematic view of forming a first amorphized region according to the present invention;
FIG. 3 is a schematic view of forming a second amorphized region according to the present invention;
Fig. 4 shows a schematic view of the dislocation structure according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a method for forming a semiconductor NMOS device having a dislocation structure, which includes:
step one, providing a substrate 101, wherein a gate structure 102 or a dummy gate structure 102 is formed on the substrate 101;
the gate structure 102 may be any well-known semiconductor gate, and the dummy gate structure 102 generally includes a gate dielectric layer, a dummy gate polysilicon layer, and a hard mask layer stacked in sequence from bottom to top, where the dummy gate polysilicon layer is used to remove and fill the gate structure 102 later.
In an alternative embodiment, the substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
Step two, forming a first side wall on the side wall of the gate structure 102 or the pseudo gate structure 102, and then forming a lightly doped drain by utilizing ion implantation; forming a second side wall on the first side wall, and then forming a source region and a drain region by utilizing ion implantation; the first side wall and the second side wall can be formed by a deposition and etching back method;
Step three, performing a first pre-amorphization ion implantation on the NMOS region on the substrate 101 to form a first amorphized region 103, forming the structure shown in fig. 2;
Typically, the substrate 101 further includes regions such as PMOS, and the substrate 101 may be covered with photoresist, after which the photoresist on the NMOS region is opened by photolithography and ion implantation is performed.
In an alternative embodiment, the ion implantation angle of the first preamorphization ion implantation in step three is 0-7 °.
In an alternative embodiment, the process conditions of the first preamorphization ion implantation in step three further comprise: the implantation ions comprise at least one of Ge, si and Xe, the implantation energy is 10 KeV-60 KeV, the implantation dosage is 1E 13-1E 15/cm2, and the implantation temperature is-100-25 ℃.
Step four, performing at least one second pre-amorphization ion implantation to the NMOS region on the substrate 101 at different ion implantation angles to form a second amorphized region 104, so that the width of the amorphous layer of the (111) crystal plane is increased, and the structure shown in fig. 3 is formed, thereby enhancing the defect formed by the (111) crystal plane, forming a semiconductor device with a more remarkable dislocation structure, improving the carrier mobility and improving the device performance;
In an alternative embodiment, the ion implantation angle of the second preamorphization ion implantation in step four is 7-45 °.
In an alternative embodiment, the number of second preamorphization ion implants in step four is one.
In an alternative embodiment, the process conditions of the second preamorphization ion implantation in step four further comprise: the implantation ions comprise at least one of Ge, si and Xe, the implantation energy is 30 KeV-90 KeV, the implantation dosage is 1E 13-1E 15/cm2, and the implantation temperature is-100 ℃ to 25 ℃.
And fifthly, recrystallizing the first amorphized region and the second amorphized region by annealing to form dislocation 105, thereby forming the structure shown in fig. 4.
In an alternative embodiment, the method of annealing in step five is a rapid thermal anneal, a millisecond thermal anneal, a microsecond thermal anneal, a spike anneal, or a furnace tube anneal process.
In an alternative embodiment, the temperature of the anneal in step five is 600-1100 ℃.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the invention can form a semiconductor device with more remarkable dislocation structure, improve carrier mobility and improve device performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A method for forming a semiconductor NMOS device having a dislocation structure, comprising:
step one, providing a substrate, wherein a grid structure or a pseudo grid structure is formed on the substrate;
Forming a first side wall on the side wall of the grid structure or the pseudo grid structure, and then forming a lightly doped drain by utilizing ion implantation; forming a second side wall on the first side wall, and then forming a source region and a drain region by utilizing ion implantation;
Step three, performing first preamorphization ion implantation on the NMOS region on the substrate to form a first amorphization region;
Step four, performing at least one second preamorphization ion implantation to the NMOS region on the substrate at different ion implantation angles to form a second amorphization region, so that the width of the amorphous layer of the (111) crystal face is increased;
And fifthly, recrystallizing the first amorphized region and the second amorphized region by annealing and forming dislocation.
2. The method for forming a semiconductor NMOS device having a dislocation structure of claim 1, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method for forming a semiconductor NMOS device having a dislocation structure of claim 1, wherein: the ion implantation angle of the first preamorphization ion implantation in the third step is 0-7 deg..
4. The method for forming a semiconductor NMOS device having a dislocation structure as recited in claim 3, wherein: the process conditions of the first preamorphization ion implantation in the third step further include: the implantation ions comprise at least one of Ge, si and Xe, the implantation energy is 10 KeV-60 KeV, the implantation dosage is 1E 13-1E 15/cm2, and the implantation temperature is-100-25 ℃.
5. The method for forming a semiconductor NMOS device having a dislocation structure of claim 1, wherein: the ion implantation angle of the second preamorphization ion implantation in the fourth step is 7-45 degrees.
6. The method for forming a semiconductor NMOS device having a dislocation structure of claim 5, wherein: the number of times of the second preamorphization ion implantation in the fourth step is one.
7. The method for forming a semiconductor NMOS device having a dislocation structure of claim 6, wherein: the process conditions of the second preamorphization ion implantation in the fourth step further include: the implantation ions comprise at least one of Ge, si and Xe, the implantation energy is 30 KeV-90 KeV, the implantation dosage is 1E 13-1E 15/cm2, and the implantation temperature is-100 ℃ to 25 ℃.
8. The method for forming a semiconductor NMOS device having a dislocation structure of claim 1, wherein: the annealing method in the fifth step is a rapid thermal annealing, millisecond thermal annealing, microsecond thermal annealing, spike annealing or furnace tube annealing process.
9. The method for forming a semiconductor NMOS device having a dislocation structure of claim 1, wherein: the annealing temperature in the fifth step is 600-1100 ℃.
CN202410224493.0A 2024-02-28 2024-02-28 Method for forming semiconductor NMOS device with dislocation structure Pending CN118073204A (en)

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