CN114124100B

CN114124100B - Noise shaping SAR ADC with background mismatch calibration

Info

Publication number: CN114124100B
Application number: CN202111457615.3A
Authority: CN
Inventors: 张翼; 高昊; 刘依桦; 刘雅琴; 庄宇航; 姚佳飞; 张瑛; 蔡志匡; 肖建; 郭宇锋
Original assignee: Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd; Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd; Nanjing University of Posts and Telecommunications
Priority date: 2021-12-01
Filing date: 2021-12-01
Publication date: 2024-03-22
Anticipated expiration: 2041-12-01
Also published as: CN114124100A

Abstract

The invention provides a noise shaping SAR ADC with background mismatch calibration, and belongs to the technical field of integrated circuits. The SAR ADC architecture adopted by the invention is similar to a general SAR ADC, and the structure comprises a sampling and holding (S/H) module, a binary weighted Capacitor DAC (CDAC), an SAR logic block, a comparator and a digital adder; the topology presented differs from a generic SAR ADC in that it embeds two additional modules: noise shaping and DAC calibration modules. The occasionally activated calibration module is capable of performing DAC mismatch calibration by a mechanism that uses a set of sub-DACs; the residual information Vresidue, which is normally discarded in a typical SAR conversion, is then reused by the NS block, so that the in-band comparator noise and quantization noise can be changed. The invention combines NS-SAR with new background calibration, combines the advantages of Sigma delta and SAR architecture, realizes high-precision low-power-consumption architecture, and overcomes the limitation of comparator noise and DAC mismatch error to the circuit.

Description

Noise shaping SAR ADC with background mismatch calibration

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a noise shaping SAR ADC with background mismatch calibration.

Background

Among the various types of ADCs, continuous time Delta Sigma (ΔΣ) modulators are widely used architecture in high resolution applications due to their special Noise Shaping (NS) function, which is achieved by changing the spectral shape of the errors in the architecture, so that the in-band signal-to-noise ratio (SNR) can be effectively improved, but such architecture typically requires an active integrator based on a high performance Operational Transconductance Amplifier (OTA), which makes it power consuming and less suitable for expansion; whereas for low power applications such as internet of things (IoT) sensors, successive approximation registers (SAR ADCs) are typically chosen to digitize the baseband signal into the digital domain, since SAR ADCs are known for their excellent power efficiency and flexible conversion rate (kS/s MS/s) as well as medium resolution (7-12 b). However, it is still difficult to extend these advantages to higher resolution designs due to the stringent requirements of comparator noise, non-linearity issues caused by digital-to-analog converter (DAC) capacitance mismatch.

Among these problems, the mismatch in capacitance caused by CMOS fabrication variations is a critical factor that must be considered, and these variations can cause non-linearity problems for the DAC, which in turn can lead to erroneous comparator decisions; these errors can create Harmonic Distortion (HD) in the spectrum, thereby reducing the overall performance of the ADC. Foreground calibration by post-processing is a common method of correcting DAC mismatch errors, but it is typically implemented off-chip due to power consumption and delay overhead. Dynamic Element Matching (DEM) technology is another method that can be used to eliminate mismatch errors, but DEM technology is costly to implement in high resolution designs because it requires thermometer coding of the calibration DAC, resulting in complex control logic. While DAC mismatch errors can also be shaped by Mismatch Error Shaping (MES) techniques, the cost is to sacrifice the 6dB dynamic range by applying reverse LSB operation.

In addition to DAC mismatch, due to supply voltage reduction and limited input signal swing, comparator noise is also a limiting factor for high resolution designs, which is currently mostly solved by two methods, one by averaging the comparator noise by making multiple decisions from over-sampling at the cost of extra cycles; another approach is to employ a two-stage pipelined SAR ADC that uses a residual amplifier to mitigate comparator noise during fine bit conversion; however, the design of the residual amplifier is not trivial, it also introduces pipeline delay between stages. A reconfigurable comparator is used to handle the conversion cycle in two modes. Although this comparator is able to compensate for 2-mode offset by a level shifter, it still faces the limitation of comparator noise when the architecture is extended to higher resolution designs.

Since the structure of the SAR ADC is simple and clear, the over-sampling and NS technology can be used in the SAR-based architecture to suppress the comparator noise, the ADC combines the advantages of the sigma delta and SAR architecture, and the high-precision low-power-consumption architecture is realized. The hybrid ADC employs NS technology by using an active FIR-IIR filter embedded in an oversampled SAR ADC, which demonstrates the way in which NS technology in SAR ADCs can effectively shape quantization noise and comparator noise into a high pass filter, thereby improving the effective in-band resolution of the ADC after filtering.

From the above, comparator noise and DAC mismatch are major problems limiting the signal-to-noise ratio (SNDR) of SAR ADCs; previous NS work proposed unique solutions, but their disadvantage is the power efficiency of DAC mismatch calibration. The present invention is therefore based on the study of designing a simpler SAR-based architecture with high SNDR and forefront efficiency to address both of these issues.

Disclosure of Invention

In order to solve the technical problems, the invention provides a noise shaping SAR ADC with background mismatch calibration, and the circuit architecture can realize the analog-to-digital conversion function of the SAR ADC and meet the index requirements of improving the comparator noise and DAC mismatch errors.

The invention relates to a noise shaping SAR ADC with background mismatch calibration, which comprises a sampling and holding module (i.e. an S/H module), a binary weighted capacitor DAC (i.e. CDAC), a comparator, SAR logic, a digital adder, a noise shaping module and a DAC calibration module; the sampling and holding module, the binary weighted capacitive DAC, the comparator, the SAR logic and the digital adder realize the analog-to-digital conversion function of the traditional SAR ADC, and the noise shaping module and the DAC calibration module are used for improving the noise of the comparator and the mismatch error of the DAC;

the integral clock input signal of the SAR ADC is phi clk, the input signal is differential signal, and the differential signal is input into the sampling and holding module;

the input signal of the sampling and holding module is a differential signal and a clock signal phi S/H, and the output signal is taken as the input signal to enter the comparator module for comparison;

the input signal of the comparator is partially from the sampling and holding module, partially from the clock signal phi cmp, and the output signal is used as the input signal of the SAR logic circuit;

the output signals of the SAR logic circuit are respectively input into a digital adder, a binary weighted capacitor DAC and a DAC calibration module;

the output result of the digital adder is the output signal of the SAR ADC, and the output signal of the binary weighted capacitor DAC is connected to the input end of the comparator again;

the structure of the noise shaping module is a gain unit and a passive FIR filter, wherein an input signal of the gain unit is residual information Vresidue and is connected to an input end of the comparator, an output signal of the gain unit is connected to the passive FIR filter, the input signal of the passive FIR filter further comprises clock signals phi gain, phi D2 and phi RST, the output signal of the passive FIR filter is an output signal of the noise shaping module and is connected to a switch controlled by a clock signal phi EF, and an output end of the switch is connected to an output end of the sampling and holding module;

the structure of the DAC calibration module comprises a calibration logic module and a sub-DAC module, wherein an input signal from SAR logic is input into the calibration logic module, an output signal of the calibration logic module is input into the sub-DAC module, and an output signal of the sub-DAC module is input into the binary weighted capacitive DAC.

Further, the binary weighted capacitive DAC is composed of 18 capacitors, including C15a, C15b, C14a, C14b, C13-C1, cres, the upper polar plates of the capacitors are all connected to the input end of the comparator, the input signals DN <15> -DN <0> are sequentially input to the bottom plates of C15a, C14a, C13-C1, cres through the inverters, and the input signals DP <15>, DP <14> are sequentially input to the bottom plates of C15b, C14b through the two inverters; binary weighted capacitive DACs and comparators controlled by SAR logic perform binary search algorithms with split monotonic switching schemes.

Further, the split monotonic switching scheme is that in a binary weighted capacitive DAC architecture, the first 2 MSBs (most significant bits) consist of four capacitors, namely C15a, C15b, C14a, C14b, whose bottom plates are controlled by two sets of complementary signals: DP <15>/DN <15> and DP <14>/DN <14>; the mismatch errors of the first 6 MSBs, i.e., C15-C10, can be calibrated by six sets of sub-DACs; two of the redundant bits, C8/C4, are used to mitigate DAC settling errors and trigger the 6 MSB calibration mechanism.

Further, for the noise shaping module, the component structure is a gain unit and a passive FIR filter, the component structure of the gain unit is an amplifier with gain G, and the component structure of the passive FIR filter is 3 switch capacitors Cres1, cres2 and Cdelay, which are respectively controlled by clock signals phi gain, phi D2 and phi RST; the input end of the amplifier is connected to the input end of the comparator, the output end of the amplifier is connected to two switches controlled by phi gain, the two switches are sequentially connected with the positive ends of Cres1 and Cres2, the positive end of Cres1 is connected to the output end of the sample and hold module, the positive end of Cres2 is connected to the switch controlled by phi D2, the switch controlled by phi D2 is connected to the positive end of Cdelay, and the positive end of Cdelay is connected to the switch controlled by phi RST and the output end of the sample and hold module.

Further, the clock includes Φclk, Φs/H, Φef, Φcmp, Φgain, Φd2 and Φrst, which together form a clock control in the SAR ADC architecture, which can be divided into three major parts in time sequence: residual processing, input tracking and NS-SAR conversion respectively represent three different working states of the SAR ADC, in a residual processing part, phiclk is 1, phiS/H, phiEF and phicmp are 0, initial states of phiRST, phiD 2 and phigain are 0, and after the initial states are changed to 1 for a period of time, the noise shaping module of the SAR ADC is in a working state, a comparator is not in operation, the SAR ADC does not perform analog-to-digital conversion, in an input tracking part, phiclk, phiEF, phicmp, phiRST, phiD 2 and phigain are 0, and phiS/H is 1, at this time, the SAR ADC is in a signal sampling state, in an NS-SAR conversion part, phiclk, phiEF is 1, phiRST, phiD 2 and phigain are 0, and phicmp is a square wave signal with 16 periods, at this time, the comparator is in a comparison state, and the SAR ADC is in a executing conversion state.

The beneficial effects of the invention are as follows: the invention uses traditional SAR ADC as basic structure, adds noise shaping module and DAC calibration module, and provides a structure combining NS-SAR with new background calibration, wherein NS-SAR is SAR ADC added with noise shaping module, background calibration is DAC calibration module, wherein noise shaping module adopts mode of shaping quantization noise and comparator noise into high-pass filter, effective in-band resolution of ADC can be improved after filtering, and comparator noise is improved, background calibration executes DAC mismatch calibration by using mechanism of a group of sub-DACs, thereby improving DAC mismatch error, the structure is suitable for high resolution design; in addition, a split monotonic switching scheme is adopted in the SAR ADC, and compared with the monotonic switching scheme, the split monotonic switching scheme can avoid bringing larger VCM changes to the system.

Drawings

In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments that are illustrated in the appended drawings.

FIG. 1 is a block diagram of a SAR ADC circuit of the present invention;

FIG. 2 is a circuit diagram of the CDAC of the SAR ADC circuitry of the present invention;

FIG. 3 is a clock signal diagram of the SAR ADC circuit of the present invention;

FIG. 4 is a complete conversion diagram of the SAR ADC circuit of the present invention;

FIG. 5 is an ENOB diagram of the SAR ADC circuitry of the present subject matter at different Ccalu;

fig. 6 is a graph comparing the performance of the SAR ADC circuit of the present invention.

Detailed Description

As shown in fig. 1, a noise shaping SAR ADC with background mismatch calibration includes a sample and hold (S/H) module, a binary weighted Capacitive DAC (CDAC), a comparator, SAR logic, a digital adder, a noise shaping module, and a DAC calibration module. The sampling and holding (S/H) module, the binary weighted Capacitor DAC (CDAC), the comparator, the SAR logic and the digital adder realize the analog-to-digital conversion function of the traditional SAR ADC, and the noise shaping module and the DAC calibration module are used for improving the noise of the comparator and the mismatch error of the DAC.

The SAR ADC operates as follows, first, a differential input signal is sampled to a binary weighted Capacitive DAC (CDAC) by a sample and hold (S/H) module, clocked at phi S/H. The CDAC and comparator controlled by the SAR logic would then perform a binary search algorithm with a split monotonic switching scheme. The original code generated for 16 comparison cycles is further processed by a digital adder, due to redundancy, ultimately giving the digital 14b output code Dout.

As shown in fig. 2, in the binary weighted capacitive DAC structure of the SAR ADC, although the monotonic switching scheme can effectively reduce the DAC size and save the switching power, it also brings a larger VCM change to the system; to avoid this, this work employs a split monotonic switching scheme. The binary weighted capacitor DAC consists of 18 capacitors, wherein the capacitors comprise C15a, C15b, C14a, C14b, C13-C1 and Cres, the upper polar plates of the capacitors are connected to the input end of a comparator, an input signal DN <15> -DN <0> is sequentially input to the bottom plates of the C15a, C14a, C13-C1 and Cres through inverters, and input signals DP <15>, DP <14> are sequentially input to the bottom plates of the C15b and C14b through two inverters; in a binary weighted capacitive DAC architecture, the first 2 MSBs consist of four capacitors (C15 a, C15b, C14a, C14 b), the bottom plates of which are controlled by two sets of complementary signals: DP <15>/DN <15> and DP <14>/DN <14>. In addition to the first 2 MSBs, capacitors with unique uses are also present in the DAC: the mismatch error of the first 6 MSBs (C15-C10) can be calibrated by six sets of sub-DACs, where the entirety of C15a, C15b is C15, and the entirety of C14a, C14b is C14; two of the redundant bits (C8/C4) are used to mitigate DAC settling errors and trigger the 6 MSB calibration mechanism.

In the SAR ADC shown in fig. 1, 2, comparator noise and DAC mismatch are major issues limiting the signal-to-noise ratio (SNDR) of the SAR ADC. For DAC calibration modules, the occasionally activated calibration module is able to perform DAC mismatch calibration by a mechanism using a set of sub-DACs. For the noise shaping module, the residual information Vresidue, which is normally discarded in a typical SAR conversion, is being reused by the NS block, so that the in-band comparator noise and quantization noise can be changed. Typically, in a monotonically switched SAR ADC, the DAC capacitor array is 1 bit lower than the actual ADC resolution, as the residual charge on the LSB capacitors is discarded after switching. However, in this work, the residual information needs to be processed by the loop filter and added back to the DAC before the next conversion starts, so an extra Cres is used to hold the residual charge from each end of the SAR conversion. Wherein, the NS module comprises a gain unit and a passive FIR filter, and comprises 3 switch capacitors: cres1, cres2 and Cdelay, which are controlled by phigain, phiD 2 and phiRST, respectively. Together with an amplifier with a gain of G, these capacitors will be able to create a second order Noise Transfer Function (NTF) to filter Vresidue. Here, the-1 gain in the FIR filter is not the actual amplifier, which is generated by the cross-coupled differential setup.

The clocking of SAR ADC architecture can be divided into three major parts: residual processing, input tracking, and NS-SAR conversion. It is important to keep the clock signals isolated from each other, which helps to prevent unwanted artifacts caused by switching problems in the simulation.

In an embodiment, as shown in FIG. 1, a 14b NS-SAR ADC is shown, it being noted that 14b is not an arbitrarily set number. The use of such a high resolution oversampling architecture for only 12ENOB appears to be over-designed, but the implicit value of this architecture is that it can also operate in SAR-only mode by disabling the oversampling and NS blocks, which provides a dual solution to the problem in the circuit, a design that makes the architecture more reliable.

As shown in fig. 3, the SAR ADC architecture employs clocks including Φclk, Φs/H, Φef, Φcmp, Φgain, Φd2, and Φrst, which together form the clocking in the SAR ADC architecture; clocking of SAR ADC architecture can be divided into three major parts: residual processing, input tracking and NS-SAR conversion respectively represent three different working states of the SAR ADC, and all the parts are combined to jointly complete the conversion process of the circuit. In the residual processing part, phiclk is 1, phiS/H, phiEF, phicmp is 0, the initial states of phiRST, phiD 2 and phigain are 0, the noise shaping module of the SAR ADC is in an operating state and does not operate, the SAR ADC does not perform analog-to-digital conversion, in the input tracking part, phiclk, phiEF, phicmp, phiRST, phiD 2 and phigain are 0, phiS/H is 1, at this time, the SAR ADC is in a signal sampling state, in the NS-SAR conversion part, phiclk, phiEF is 1, phiS/H, phiD 2 and phigain are 0, and phicmp is a square wave signal of 16 periods, at this time, the comparator is in a comparison state, and the SAR ADC is in an SAR conversion execution state.

As shown in fig. 4, a complete conversion process of the ADC is shown, where 16 cycles are used to perform the SAR conversion, and Vresidue will feed the NS block after the 16 th cycle. Marked by the dashed line is the calibration mechanism for DAC mismatch that is occasionally activated by the 17 th cycle. In general, these 16 cycles consist of 14 normal cycles and two redundant cycles (8 th cycle and 12 th cycle). Although the digital adder will ultimately give a 14b output code by removing the redundancy bits, these redundancy periods can still be used for SAR conversion to mitigate DAC settling errors; more importantly, the first redundancy bit also implements a calibration scheme so that the first 6 MSB capacitors can be calibrated through a set of sub-DACs.

The model of the EF loop is composed of a gain unit and a charge sharing block, and can be represented by a second-order Noise Transfer Function (NTF), as follows:

NTF(z)＝1-K EF(z-1-0.5z-2)

where KEF is the EF coefficient.

In SAR ADC architecture, the background calibration topology can be divided into two parts: error detection and error correction; due to redundancy, error detection can be used to check if DNL errors do exist on the MSB; while the MSB will have a coherent sub-DAC, which is a binary weighted capacitor array with unit capacitors Ccalu, which sub-DAC will compensate for DNL losses from the MSB; thus, like Cu, the size of Ccalu is also an important parameter to be determined, since the size affects the calibration of the MSB. In principle, smaller Ccalu is better calibrated, which results in better performance of the overall ADC, as can be demonstrated in FIG. 5. In fig. 5, the calibration is best when Ccalu is 1/16Cu, and it is apparent that all cases shown in fig. 5 are substantially improved after the main DAC calibration is enabled.

As shown in fig. 6, by combining the above, the overall performance of the circuit is improved, and the SFDR average value is changed from 83.32dB to 95.27dB.

In summary, compared with the conventional ΣΔ and SAR architecture, the noise shaping SAR ADC architecture with background mismatch calibration proposed by the present invention embeds two additional modules in the circuit: the noise shaping and DAC calibration module creatively combines NS-SAR with new background calibration, combines the advantages of Sigma delta and SAR architectures, realizes a high-precision low-power-consumption architecture, and overcomes the limitation of comparator noise and DAC mismatch errors on circuits.

The foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations using the description and drawings of the present invention are within the scope of the present invention.

Claims

1. A noise shaping SAR ADC with background mismatch calibration, wherein the SAR ADC comprises a sample and hold module, a binary weighted capacitive DAC, a comparator, SAR logic, a digital adder, a noise shaping module, a DAC calibration module;

2. A noise shaping SAR ADC with background mismatch calibration according to claim 1, wherein the binary weighted capacitive DAC consists of 18 capacitors, comprising C15a, C15b, C14a, C14b, C13-C1, cres, the upper plates of which are all connected to the input of the comparator, the input signal DN <15> -DN <0> being sequentially input to the bottom plates of C15a, C14a, C13-C1, cres via inverters, the input signals DP <15>, DP <14> being sequentially input to the bottom plates of C15b, C14b via two inverters; binary weighted capacitive DACs and comparators controlled by SAR logic perform binary search algorithms with split monotonic switching schemes.

3. A noise shaping SAR ADC with background mismatch calibration according to claim 2, wherein the split monotonic switching scheme is such that in a binary weighted capacitive DAC structure the first 2 MSBs consist of four capacitors, C15a, C15b, C14a, C14b, whose bottom plates are controlled by two sets of complementary signals: DP <15>/DN <15> and DP <14>/DN <14>; the mismatch errors of the first 6 MSBs, i.e., C15-C10, can be calibrated by six sets of sub-DACs; two of the redundant bits, C8/C4, are used to mitigate DAC settling errors and trigger the 6 MSB calibration mechanism.

4. A noise shaping SAR ADC with background mismatch calibration according to claim 1, wherein for the noise shaping module, the gain element is an amplifier with gain G and the passive FIR filter is a 3 switched capacitors Cres1, cres2 and Cdelay, controlled by clock signals phigain, phid 2 and phirst, respectively; the input end of the amplifier is connected to the input end of the comparator, the output end of the amplifier is connected to two switches controlled by phi gain, the two switches are sequentially connected with the positive ends of Cres1 and Cres2, the positive end of Cres1 is connected to the output end of the sample and hold module, the positive end of Cres2 is connected to the switch controlled by phi D2, the switch controlled by phi D2 is connected to the positive end of Cdelay, and the positive end of Cdelay is connected to the switch controlled by phi RST and the output end of the sample and hold module.

5. A noise-shaping SAR ADC with background mismatch calibration according to claim 1, wherein: the clock comprises phi clk, phi S/H, phi EF, phi cmp, phi gain, phi D2 and phi RST, and the clocks jointly form clock control in the SAR ADC architecture, and the clock control can be divided into three major parts according to time sequence: residual processing, input tracking and NS-SAR conversion respectively represent three different working states of the SAR ADC, in a residual processing part, phiclk is 1, phiS/H, phiEF and phicmp are 0, initial states of phiRST, phiD 2 and phigain are 0, and after the initial states are changed to 1 for a period of time, the noise shaping module of the SAR ADC is in a working state, a comparator is not in operation, the SAR ADC does not perform analog-to-digital conversion, in an input tracking part, phiclk, phiEF, phicmp, phiRST, phiD 2 and phigain are 0, and phiS/H is 1, at this time, the SAR ADC is in a signal sampling state, in an NS-SAR conversion part, phiclk, phiEF is 1, phiRST, phiD 2 and phigain are 0, and phicmp is a square wave signal with 16 periods, at this time, the comparator is in a comparison state, and the SAR ADC is in a executing conversion state.