CN110868218A - Successive approximation type analog-to-digital converter adopting capacitor array - Google Patents
Successive approximation type analog-to-digital converter adopting capacitor array Download PDFInfo
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract
The invention provides a successive approximation type analog-to-digital converter adopting a capacitor array, which can meet the requirements of high speed, medium and high precision and low power consumption and greatly improve the speed and precision of the converter; the SAR digital calibration circuit comprises a bootstrap switch circuit, a DAC capacitor array, a comparator circuit, an SAR logic control circuit and a digital calibration circuit which are connected in sequence, wherein the DAC capacitor array is connected with the SAR logic control circuit, and the input end of the bootstrap switch circuit is connected with a differential input voltage; the bootstrap switch circuit is used for sampling the differential input voltage and keeping the differential input voltage in the DAC capacitor array; the DAC capacitor array is used for transmitting the maintained differential input voltage to the comparator circuit for comparison; the comparator circuit is used for comparing the differential input voltage and transmitting a comparison result to the SAR logic control circuit; the SAR logic control circuit is used for converting the digital code of the comparison result and generating a digital signal; and the digital calibration circuit is used for converting the obtained digital signal into a final digital output signal.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a successive approximation type analog-to-digital converter adopting a capacitor array.
Background
The a/D converter is an important bridge for connecting an Analog system and a digital signal processing system, and with the wide application of the ADC in the digital signal processing technology and the wireless communication field, the demand for an ADC (Analog-to-digital converter) based on a CMOS process is increasing day by day, but the existing converter cannot meet the requirements of high speed, medium and high precision, and low power consumption, and thus cannot improve the speed and precision of the ADC.
Disclosure of Invention
In view of the above problems, the present invention provides a successive approximation type analog-to-digital converter using a capacitor array, which can meet the requirements of high speed, medium and high precision, and low power consumption, and greatly improve the speed and precision of the converter.
The technical scheme is as follows: the method is characterized in that: the SAR analog-digital conversion circuit comprises a bootstrap switch circuit, a DAC capacitor array, a comparator circuit, an SAR logic control circuit and a digital calibration circuit which are connected in sequence, wherein the DAC capacitor array is connected with the SAR logic control circuit, and the input end of the bootstrap switch circuit is connected with a differential input voltage;
the bootstrap switch circuit is used for sampling the differential input voltage and holding the differential input voltage in the DAC capacitor array;
the DAC capacitor array is used for transmitting the maintained differential input voltage to the comparator circuit for comparison;
the comparator circuit is used for comparing the differential input voltage and transmitting a comparison result to the SAR logic control circuit;
the SAR logic control circuit is used for converting the comparison result compared by the comparator circuit into a digital code and generating a digital signal;
and the digital calibration circuit is used for converting the obtained digital signal into a final digital output signal through logic operation.
It is further characterized in that:
an input end IN1 and an input end IN2 of the bootstrap switch circuit are respectively and correspondingly connected with differential input voltage Vip and Vin, the bootstrap switch circuit comprises MOS tubes M1-M11 and a capacitor C24, gates of the MOS tubes M1 and M7 are both connected with an external clock signal clk, gates of the MOS tubes M2 and M11 are connected with an external clock signal clkb, a source of the MOS tube M1 is connected with a drain of the MOS tube M3 and then connected with a voltage Vdd, a drain of the MOS tube M1 is connected with a drain of the MOS tube M7, a drain of the MOS tube M8 and a gate of the MOS tube M4, a source of the MOS tube M3 is connected with a drain of the MOS tube M4 and one end of the capacitor C24, the other end of the capacitor C24 is connected with a drain of the MOS tube M24, a source of the MOS tube M24 and a source of the MOS tube M24 are connected with a drain of the MOS tube M24, and a drain of the MOS tube M24 are connected with the drain of the MOS tube M24, the drain of the MOS transistor M10 is connected with the gates of the MOS transistors M6, M8 and M11 and the source of the MOS transistor M4, the source of the MOS transistor M9 is connected with the drain of the MOS transistor M6, the source of the MOS transistor M6 is connected with the drain of the MOS transistor M5, the substrates of the MOS transistors M5, M6, M7, M8 and M10 and the gate of the MOS transistor M5 are connected with a voltage Vss, and the gate of the MOS transistor M10 is connected with a voltage Vdd;
the DAC capacitor array comprises capacitors C0-C11, C12-C23, selection switches S0-S11 and S11-S23, one ends of the capacitors C0-C11 are connected with the differential input voltage Vip, the other ends of the capacitors C0-C11 are correspondingly connected with the first ends of the selection switches S0-S11, the second ends of the selection switches S0-S11 are connected with a reference voltage Vref, and the third ends of the selection switches S0-S11 are grounded; one ends of the capacitors C12-C23 are all connected with the differential input voltage Vin, the other ends of the capacitors C12-C23 are respectively correspondingly connected with the first ends of the selector switches S12-S23, the second ends of the selector switches S12-S23 are all connected with the reference voltage Vref, and the third ends are all grounded;
the comparator circuit comprises MOS tubes MP-MP, MOS tubes MN-MN, a phase inverter T and T, wherein the grids of the MOS tubes MP, MN and MN are all connected with an external clock signal clkc, the drain electrodes of the MOS tubes MP, MP and MP are connected with a voltage Vdd, the source electrode of the MOS tube MP, the drain electrodes of the MOS tube MP and MP are connected, the source electrode of the MOS tube MP is connected with the grid electrode of the MOS tube MP, the drain electrode of the MN and the input end of the phase inverter T, the source electrodes of the MOS tube MN and MN are grounded, the output end of the phase inverter T is connected with the drain electrode of the MOS tube MN, the source electrode of the MOS tube MP, the grid electrode of the MN, the grid electrode of the MP, the source electrode of the MN and the drain electrode of the MP are connected, and the source electrode of the MOS tube MP, the source electrode of, The grid of MN2, the grid of MP4, the source of MN1 and the drain of MP3 are all connected, the drain of MOS pipe MP3 and the source of MP4 are connected and then connected with a voltage Vdd, and the grid ends of MOS pipes MP6 and MP7 are both connected with the output end OUT of the bootstrap switch circuit;
the SAR logic control circuit comprises a plurality of bit control modules, wherein the clksb input end of the bit control module at the front stage is connected with an external clock signal, the output ends outp and outn of the comparator circuit are both connected with the input end of the bit control module, the bit control module at the rear stage is connected with the clock control signal end clkn generated by the bit control module at the front stage, so that the bit control modules are connected, and n is 0, 1 and 2. . . . . . The control output end of the bit control module is correspondingly connected with one end of a selection switch of the DAC capacitor array;
the bit control module comprises MOS tubes MP 8-MP 11, MOS tubes MN 5-MN 9 and a D trigger DD10, the gates of the MOS tubes MP8 and MP9 are connected, the gate terminal of the MOS tube MN9 is used as a clock control signal terminal clkn of the bit control module, the drains of the MOS tubes MP 9-MP 9 are connected with a voltage Vdd after being connected, the source of the MOS tube MP9, the gate of the MOS tube MN9, the source of the MP9, the gate of the MP9, the drain of the MN9 and the drain of the MN9 are connected, the source of the MOS tube MP9, the gate of the MP9, the drain of the MN9 and the input terminal of the D trigger DD9 are connected, the sources of the MOS tubes MN9 and the output terminal of the MOS tubes MN9 are connected, the output terminal of the MOS tube MN9 is connected with the MOS tube MN9, the output terminal of the MOS tube MN9, the MOS tube 9 is connected with the source 9, the output terminal of the MOS tube MN9, the output end of the D flip-flop DD10 generates a digital code Bi, where i is 0, 1, 2. . . . . . (ii) a
The digital calibration circuit comprises full adders FA-FA and D triggers DD-DD, an SU carry end of the full adder FA is connected with an A input end of the full adder FA, an A input end of the full adder FA is connected with an A input end of the full adder FA, an SU carry end of the full adder FA is connected with an A input end of the full adder FA, an A input end of the full adder FA is connected with the A input ends of the full adder FA and the FA, an A input end of the full adder FA is connected with the SU carry end of the full adder FA, the SU carry end of the full adder FA is connected with the A input end of the full adder FA, an A input end of the full adder FA is connected with the A input end of the full adder FA, a carry end of the full adder FA is connected with the A input end of the full adder FA, and the SU carry end of the full adder FA is connected with the A input end of the full adder FA, an SU carry terminal of full adder FA7 is connected to an a1 input terminal of full adder FA8, an SU carry terminal of full adder FA8 is connected to an a1 input terminal of full adder FA9, an SU carry terminal of full adder FA9 is connected to an a1 input terminal of full adder FA10, a2 input terminals of full adders FA8, FA9 and FA10 are all connected, an SU carry terminal of full adder FA2 is connected to an input terminal of D flip-flop DD2, a CO output terminal of full adder FA2 is connected to an a2 input terminal of full adder FA2, a CO output terminal of full adder FA2 is connected to an input terminal of D flip-flop FA2, a CO output terminal of full adder FA2 is connected to a DD2 input terminal of D flip-flop FA2, a DD output terminal of full adder FA2 is connected to a DD2, and a DD output terminal of full adder FA2 is connected to a DD2, the CO output end of the full adder FA7 is connected to the input end of the D flip-flop DD5, the CO output end of the full adder FA8 is connected to the input end of the D flip-flop DD6, the CO output end of the full adder FA9 is connected to the input end of the D flip-flop DD7, the CO output end of the full adder FA10 is connected to the input end of the D flip-flop DD8, the clock input ends of the D flip-flops DD0 to DD9 are connected to the gate of the MOS transistor MN7, and the input end of the D flip-flop DD0 is connected to the output end of the D flip-flop DD10 of the previous stage of the bit control module.
The SAR logic control circuit has the advantages that the differential input voltages Vip and Vin are sampled and held on the DAC capacitor array through the bootstrap switch circuit, the DAC capacitor array transmits the held differential input voltages Vip and Vin to the comparator circuit for first comparison, the comparison result is transmitted to the SAR logic control circuit to generate a digital code, a control signal is generated and fed back to the DAC capacitor array, the comparator circuit enters second comparison under the action of the control signal generated by the SAR logic control circuit, the analogy is carried out in sequence until the SAR logic control circuit sequentially generates the digital code, and the digital code is converted into a final digital output result through logic operation through the digital calibration circuit; the method not only reduces the establishing time of the circuit, but also improves the overall speed of the circuit, thereby meeting the requirements of high speed, medium and high precision and low power consumption, and greatly improving the speed and precision of the converter.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a DAC capacitor array circuit of the present invention;
FIG. 3 is a diagram illustrating DAC capacitor array weight redistribution according to the present invention;
FIG. 4 is a schematic diagram of a bootstrap switch circuit of the present invention;
FIG. 5 is a schematic diagram of a comparator circuit of the present invention;
FIG. 6 is a schematic diagram of the SAR logic control circuit structure of the present invention;
FIG. 7 is a circuit schematic of the bit control module of the present invention;
FIG. 8 is a logic calculation diagram of the digital calibration circuit of the present invention;
FIG. 9 is a schematic diagram of the digital calibration circuit of the present invention.
Detailed Description
As shown in fig. 1 to 9, a successive approximation type analog-to-digital converter using a capacitor array includes a bootstrap switch circuit, a DAC capacitor array, a comparator circuit, an SAR logic control circuit, and a digital calibration circuit, which are connected in sequence, where the DAC capacitor array is connected to the SAR logic control circuit, and an input end of the bootstrap switch circuit is connected to a differential input voltage;
the bootstrap switch circuit is used for sampling the differential input voltage and keeping the differential input voltage in the DAC capacitor array;
the DAC capacitor array is used for transmitting the maintained differential input voltage to the comparator circuit for comparison;
the comparator circuit is used for comparing the differential input voltage and transmitting a comparison result to the SAR logic control circuit;
the SAR logic control circuit is used for converting the comparison result compared by the comparator circuit into a digital code and generating a digital signal;
and the digital calibration circuit is used for converting the obtained digital signal into a final digital output signal through logic operation.
As shown IN fig. 4, an input terminal IN1 and an input terminal IN2 of the bootstrap switch circuit are respectively and correspondingly connected to differential input voltages Vip and Vin, the bootstrap switch circuit includes MOS transistors M1 to M11 and a capacitor C24, gates of the MOS transistors M1 and M7 are both connected to an external clock signal clk, gates of the MOS transistors M2 and M11 are connected to an external clock signal clkb, and the external clock signal clk and the external clock signal clkb are a pair of inverted clock input signals; the source of MOS tube M1 is connected with the drain of MOS tube M3 and then connected with voltage Vdd, the drain of MOS tube M1 is connected with the drain of MOS tube M7, the drain of MOS tube M8 and the gate of MOS tube M4, the source of MOS tube M3 is connected with the drain of MOS tube M4 and one end of capacitor C24, the other end of capacitor C24 is connected with the drain of MOS tube M2, the source of MOS tube M7, the source of MOS tube M8 and the drain of MOS tube M9, the source of MOS tube M2 and the source of MOS tube M11 are connected with voltage Vss, the drain of MOS tube M11 is connected with the source of MOS tube M10, the drain of MOS tube M10 is connected with MOS tube M6, the gates of the M8 and M11 and the source of the MOS transistor M4 are connected, the source of the MOS transistor M9 is connected with the drain of the MOS transistor M6, the source of the MOS transistor M6 is connected with the drain of the MOS transistor M5, the substrates of the MOS transistors M5, M6, M7, M8 and M10 and the gate of the MOS transistor M5 are connected with a voltage Vss, and the gate of the MOS transistor M10 is connected with the voltage Vdd;
when the external clock signal clk is low, the MOS transistors M1 and M2 are turned on to precharge the capacitor C1, the voltage difference across the capacitor C1 gradually changes to Vdd, and at this time, the output terminal OUT maintains the instantaneous voltage value of the input terminal IN1 before the MOS transistor M6 is turned off; when the external clock signal clk is high, the MOS transistors M3 and M4 are turned on, so that the MOS transistor M6 is turned on, and the circuit enters a sampling phase. The size of the MOS transistor M5 is the same as that of the MOS transistor M6, and the MOS transistor M5 can be matched with various parasitic parameters of the MOS transistor M6, so that the linearity of the circuit is improved.
As shown in fig. 2, the DAC capacitor array includes capacitors C0-C11, C12-C23, selection switches S0-S11, and S11-S23, wherein one ends of the capacitors C0-C11 are all connected to a differential input voltage Vip, the other ends of the capacitors C0-C11 are respectively connected to first ends of the selection switches S0-S11, second ends of the selection switches S0-S11 are all connected to a reference voltage Vref, and third ends are all grounded; one ends of capacitors C12-C23 are all connected with the differential input voltage Vin, the other ends of the capacitors C12-C23 are respectively correspondingly connected with the first ends of selector switches S12-S23, the second ends of the selector switches S12-S23 are all connected with the reference voltage Vref, and the third ends are all grounded;
if the differential input voltage Vip is greater than Vin, the selection switch of the highest-order capacitor connected with the DAC capacitor array and the differential input voltage Vip is closed, the lower-level plate voltage of the DAC capacitor array is changed from reference voltage Vref to 0, and according to the principle of charge conservation, the upper-level plate voltage value of the DAC capacitor array connected with the differential input voltage Vip is changed to Vip-Vref/2; on the contrary, if the differential input voltage Vip is less than Vin, the selection switch of the highest-order capacitor connected with the DAC capacitor array and the differential input voltage Vin is closed, the lower-level plate voltage of the DAC capacitor array is changed from the reference voltage Vref to 0, and at this time, the upper-level plate voltage value of the DAC capacitor array connected with the differential input voltage Vin is changed to Vin-Vref/2.
As shown in fig. 5, the comparator circuit includes MOS transistors MP1 to MP7, MOS transistors MN1 to MN4, inverters T1 and T2, gates of MOS transistors MP5, MOS transistors MN3 and MN4 are all connected to an external clock signal clkc, drains of MOS transistors MP1, MP2 and MP5 are connected to a voltage Vdd, sources of MOS transistors MP5 and MP6 and MP7 are connected to a drain, a source of MOS transistor MP6 is connected to a gate of MOS transistor MP1, a drain of MN3 and an input of inverter T1, a source of MOS transistor MP7 is connected to a gate of MOS transistor MP2, a drain of MOS transistor MN4 and an input of inverter T4, sources of MOS transistors MN4 and MN4 are all connected to ground, an output of inverter T4 is connected to a drain of MOS transistor MN4, a source of MOS transistor MP4, a source of MOS transistors MP4 and MP4 are connected to a drain of MOS transistors MN4, a drain of MOS transistors MN4 and a drain of MOS transistors MP4, a gate 4 and a drain of MOS transistors MN4, the drain of the MOS tube MP3 and the source of the MP4 are connected and then connected with a voltage Vdd, and the grid ends of the MOS tubes MP6 and MP7 are both connected with the output end OUT of the bootstrap switch circuit;
when an external clock signal clkc is at a high level, the comparator circuit sets the output high through the MOS tube MP1 and the MOS tube MP2, and at the moment, the comparator circuit is in a reset state; when the external clock signal clkc is low, the comparator circuit compares the magnitude of the input voltage and pulls the output up to Vdd on one side and down to ground on the other side through the positive feedback action of the latch. And after the output of the comparator circuit is effective, triggering the SAR logic control circuit to start working.
As shown in fig. 6, the SAR logic control circuit includes 12 bit control modules, the clksb input terminal of the previous bit control module is connected to an external clock signal, the output terminals outp and outn of the comparator circuit are both connected to the input terminal of the bit control module, and the subsequent bit control module is connected to the clock control signal terminal clkn generated by the previous bit control module, so that a plurality of bit control modules are connected, where n is 0, 1, and 2. . . . . . 11, namely the clock control signal terminal clk0 of the first bit control module is connected to the input terminal of the second bit control module, the clock control signal terminal clk1 of the second bit control module is connected to the input terminal of the third bit control module, and the clock control signal terminals clk10 of the eleventh bit control module are sequentially connected until the clock control signal terminal clk10 of the eleventh bit control module is connected to the input terminal of the twelfth bit control module; control output ends ctr 0-ctr 23 of the SAR logic control circuit are respectively and correspondingly connected with one ends of selection switches S0-S23 of the DAC capacitor array;
the bit control module generates a bit digital code under the control of an input external clock signal and output signals outp and outn of the comparator circuit, and generates a clock control signal of a post-stage bit control module and a DAC capacitor array control signal.
As shown in fig. 7, each bit control module includes MOS transistors MP8 to MP11, MOS transistors MN5 to MN9, and a D flip-flop DD9, gates of the MOS transistors MP9 and MP9 are connected, a gate terminal of the MOS transistor MN9 is used as a clock control signal terminal clkn of the bit control module, drains of the MOS transistors MP9 to MP9 are connected to a voltage Vdd, a source of the MOS transistor MP9, a gate of the MOS transistor MN9, a source of the MP9, a drain of the MOS transistor MN9, a drain of the MN9, and a drain of the MN9 are connected, sources of the MOS transistors MP9, a gate of the MOS transistor MN9, a source of the MP9, a gate of the MP9, a drain of the MP9, and an input terminal of the D flip-flop DD9 are connected, sources of the MOS transistors MN9, a source of the MN9 and a source of the MN9 are connected to a ground, a source of the MOS transistor MN9, a gate of the output terminal of the MOS transistor MN9 is connected to an output terminal of the MN9, and a digital comparator 9, the output terminal of, wherein i is 0, 1, 2. . . . . . . 11;
in fig. 6 and 7, clkin is used as the output clock of the previous stage bit control module, the external clock signal input by the first bit control module is clksb, clkin is logically processed by the D flip-flop DD10 to generate the clock signal clk as the input of the next stage bit control module, and clks is the external clock signal.
As shown in fig. 9, the digital calibration circuit includes full-adder FA 1-FA 10 and D flip-flop DD 0-DD 9, the SU carry of full-adder FA1 is connected to the a1 input of full-adder FA2, the A3 input of full-adder FA1 is connected to the a2 input of full-adder FA2, the SU carry of full-adder FA2 is connected to the a1 input of full-adder FA3, the a2 input of full-adder FA3 is connected to both the a4 and the a7 inputs of full-adder FA7, the a7 input of full-adder FA7 is connected to the SU carry of full-adder FA7, the SU carry of full-adder FA7 is connected to the a7 input of full-adder FA7, the a FA7 input of full-adder FA7 is connected to the a7 input of full-adder FA7, the FA7 is connected to the FA7 input of full-adder FA7, an SU carry end of a full adder FA8 is connected with an A1 input end of a full adder FA9, an SU carry end of the full adder FA9 is connected with an A9 input end of the full adder FA9, input ends of the full adder FA9, the FA9 and the FA9 are all connected, an SU carry end of the full adder FA9 is connected with an input end of a D flip-flop DD9, a CO output end of the full adder FA9 is connected with an input end of the D flip-flop DD9, a CO output end of the full adder FA9 is connected with an A9 input end of the full adder FA9, a CO output end of the full adder FA9 is connected with an input end of the D flip-flop DD9, a CO output end of the DD flip-flop DD9 is connected with an input end of the D flip-flop DD9, and a CO output end of the DD flip-flop DD9 is connected with an input end of the full adder FA9, a CO output end of the full adder FA9 is connected with an input, the CO output end of a full adder FA10 is connected with the input end of a D flip-flop DD8, the clock input ends of the D flip-flops DD 0-DD 9 are connected and then connected with the grid of an MOS transistor MN7, and the input end of the D flip-flop DD0 is connected with the output end of a D flip-flop DD10 of a front-stage bit control module.
In fig. 2, the monotonic capacitor switch array is adopted in the invention, and compared with the traditional capacitor array, the structure reduces a highest-order capacitor, so that the total capacitance is reduced to half of the original capacitance, therefore, the area of the capacitor array is also reduced to half of the original capacitance, and the power consumption is reduced by 81% compared with the traditional capacitor array; meanwhile, the number of the selection switches of the lower electrode plate of the DAC capacitor array capacitor is reduced, so that the establishing time of the circuit is shortened, and the integral speed of the circuit is improved.
In fig. 3, the present invention also redistributes the weights of capacitors in the capacitor array based on the monotonic capacitor switch array, the highest-order capacitor of the DAC capacitor array is divided into two parts, namely 240C and 16C (C is a unit capacitor), then 16C is divided into a plurality of small parts and added to the corresponding low-order bits of the DAC capacitor array, two redundant bits are added at the same time, and finally the weights of the 4-bit capacitors behind the DAC capacitor array are doubled, so that the redistribution of the weights of the capacitor array is favorable for further shortening the circuit setup time, and simultaneously, the influence of the parasitic capacitors on the low-order capacitors is reduced, thereby avoiding the occurrence of messy codes in the output result, and improving the precision and speed of the converter.
In the invention, 12-bit control modules are adopted to generate 12-bit digital codes: B0-B11, obtaining the final 10-bit digital codes D0-D9 through the logic operation of a digital calibration circuit; as shown in fig. 8 and 9, the digital code B0 is directly provided to the input terminal of the D flip-flop DD0 to obtain the digital code D0; the home value obtained by the sum of the digital codes B1, B2 and B4 is assigned to D1 bits; the carry value and the home value obtained by the sum of the digital codes B3, B4, B5 and B6 are endowed with D2 bits; the carry value and the home value obtained by the sum of the digital codes B5, B7 and B8 are endowed with D3 bits; the carry value and the local value obtained by the sum of the digital code B6 are endowed with D4 bits; the carry value and the home value obtained by the sum of the digital codes B7 and B11 are endowed with D5 bits; the carry value and the home value obtained by the sum of the digital codes B8 and B11 are endowed with D6 bits; the carry value and the home value obtained by the sum of the digital codes B9 and B11 are endowed with D7 bits; the carry value and the home value obtained by the sum of the digital codes B10 and B11 are endowed with D8 bits; the carry value is assigned to D9 bit; thereby converting 12-bit digital codes B0-B11 output by the SAR logic control circuit into 10-bit digital codes D0-D9.
It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention. The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (7)
1. A successive approximation type analog-to-digital converter adopting a capacitor array is characterized in that: the SAR analog-digital conversion circuit comprises a bootstrap switch circuit, a DAC capacitor array, a comparator circuit, an SAR logic control circuit and a digital calibration circuit which are connected in sequence, wherein the DAC capacitor array is connected with the SAR logic control circuit, and the input end of the bootstrap switch circuit is connected with a differential input voltage;
the bootstrap switch circuit is used for sampling the differential input voltage and holding the differential input voltage in the DAC capacitor array;
the DAC capacitor array is used for transmitting the maintained differential input voltage to the comparator circuit for comparison;
the comparator circuit is used for comparing the differential input voltage and transmitting a comparison result to the SAR logic control circuit;
the SAR logic control circuit is used for converting the comparison result compared by the comparator circuit into a digital code and generating a digital signal;
and the digital calibration circuit is used for converting the obtained digital signal into a final digital output signal through logic operation.
2. A successive approximation analog-to-digital converter using a capacitor array according to claim 1, wherein: an input end IN1 and an input end IN2 of the bootstrap switch circuit are respectively and correspondingly connected with differential input voltage Vip and Vin, the bootstrap switch circuit comprises MOS tubes M1-M11 and a capacitor C24, gates of the MOS tubes M1 and M7 are both connected with an external clock signal clk, gates of the MOS tubes M2 and M11 are connected with an external clock signal clkb, a source of the MOS tube M1 is connected with a drain of the MOS tube M3 and then connected with a voltage Vdd, a drain of the MOS tube M1 is connected with a drain of the MOS tube M7, a drain of the MOS tube M8 and a gate of the MOS tube M4, a source of the MOS tube M3 is connected with a drain of the MOS tube M4 and one end of the capacitor C24, the other end of the capacitor C24 is connected with a drain of the MOS tube M24, a source of the MOS tube M24 and a source of the MOS tube M24 are connected with a drain of the MOS tube M24, and a drain of the MOS tube M24 are connected with the drain of the MOS tube M24, the drain of the MOS transistor M10 is connected to the gates of the MOS transistors M6, M8 and M11 and the source of the MOS transistor M4, the source of the MOS transistor M9 is connected to the drain of the MOS transistor M6, the source of the MOS transistor M6 is connected to the drain of the MOS transistor M5, the substrates of the MOS transistors M5, M6, M7, M8 and M10 and the gate of the MOS transistor M5 are connected to a voltage Vss, and the gate of the MOS transistor M10 is connected to a voltage Vdd.
3. A successive approximation analog-to-digital converter using a capacitor array according to claim 2, wherein: the DAC capacitor array comprises capacitors C0-C11, C12-C23, selection switches S0-S11 and S11-S23, one ends of the capacitors C0-C11 are connected with the differential input voltage Vip, the other ends of the capacitors C0-C11 are correspondingly connected with the first ends of the selection switches S0-S11, the second ends of the selection switches S0-S11 are connected with a reference voltage Vref, and the third ends of the selection switches S0-S11 are grounded; one ends of the capacitors C12-C23 are all connected with the differential input voltage Vin, the other ends of the capacitors C12-C23 are respectively correspondingly connected with the first ends of the selector switches S12-S23, the second ends of the selector switches S12-S23 are all connected with the reference voltage Vref, and the third ends are all grounded.
4. A successive approximation analog-to-digital converter using a capacitor array according to claim 2, wherein: the comparator circuit comprises MOS tubes MP-MP, MOS tubes MN-MN, a phase inverter T and T, wherein the grids of the MOS tubes MP, MN and MN are all connected with an external clock signal clkc, the drain electrodes of the MOS tubes MP, MP and MP are connected with a voltage Vdd, the source electrode of the MOS tube MP, the drain electrodes of the MOS tube MP and MP are connected, the source electrode of the MOS tube MP is connected with the grid electrode of the MOS tube MP, the drain electrode of the MN and the input end of the phase inverter T, the source electrodes of the MOS tube MN and MN are grounded, the output end of the phase inverter T is connected with the drain electrode of the MOS tube MN, the source electrode of the MOS tube MP, the grid electrode of the MN, the grid electrode of the MP, the source electrode of the MN and the drain electrode of the MP are connected, and the source electrode of the MOS tube MP, the source electrode of, The grid of MN2, the grid of MP4, the source of MN1, the drain of MP3 are all connected, the drain of MOS pipe MP3, the source of MP4 are connected and then connected with voltage Vdd, the grid ends of MOS pipe MP6, MP7 are all connected to the output end OUT of the bootstrap switch circuit.
5. A successive approximation analog-to-digital converter using a capacitor array according to claim 3, wherein: the SAR logic control circuit comprises a plurality of bit control modules, wherein the clksb input end of the bit control module at the front stage is connected with an external clock signal, the output ends outp and outn of the comparator circuit are both connected with the input end of the bit control module, the bit control module at the rear stage is connected with the clock control signal end clkn generated by the bit control module at the front stage, so that the bit control modules are connected, and n is 0, 1 and 2. . . . . . And the control output end of the bit control module is correspondingly connected with one end of the selection switch of the DAC capacitor array.
6. The successive approximation analog-to-digital converter using the capacitor array as claimed in claim 5, wherein: the bit control module comprises MOS tubes MP 8-MP 11, MOS tubes MN 5-MN 9 and a D trigger DD10, the gates of the MOS tubes MP8 and MP9 are connected, the gate terminal of the MOS tube MN9 is used as a clock control signal terminal clkn of the bit control module, the drains of the MOS tubes MP 9-MP 9 are connected with a voltage Vdd after being connected, the source of the MOS tube MP9, the gate of the MOS tube MN9, the source of the MP9, the gate of the MP9, the drain of the MN9 and the drain of the MN9 are connected, the source of the MOS tube MP9, the gate of the MP9, the drain of the MN9 and the input terminal of the D trigger DD9 are connected, the sources of the MOS tubes MN9 and the output terminal of the MOS tubes MN9 are connected, the output terminal of the MOS tube MN9 is connected with the MOS tube MN9, the output terminal of the MOS tube MN9, the MOS tube 9 is connected with the source 9, the output terminal of the MOS tube MN9, the output end of the D flip-flop DD10 generates a digital code Bi, where i is 0, 1, 2. . . . . . .
7. The successive approximation analog-to-digital converter adopting the capacitor array as claimed in claim 6, wherein: the digital calibration circuit comprises full adders FA-FA and D triggers DD-DD, an SU carry end of the full adder FA is connected with an A input end of the full adder FA, an A input end of the full adder FA is connected with an A input end of the full adder FA, an SU carry end of the full adder FA is connected with an A input end of the full adder FA, an A input end of the full adder FA is connected with the A input ends of the full adder FA and the FA, an A input end of the full adder FA is connected with the SU carry end of the full adder FA, the SU carry end of the full adder FA is connected with the A input end of the full adder FA, an A input end of the full adder FA is connected with the A input end of the full adder FA, a carry end of the full adder FA is connected with the A input end of the full adder FA, and the SU carry end of the full adder FA is connected with the A input end of the full adder FA, an SU carry terminal of full adder FA7 is connected to an a1 input terminal of full adder FA8, an SU carry terminal of full adder FA8 is connected to an a1 input terminal of full adder FA9, an SU carry terminal of full adder FA9 is connected to an a1 input terminal of full adder FA10, a2 input terminals of full adders FA8, FA9 and FA10 are all connected, an SU carry terminal of full adder FA2 is connected to an input terminal of D flip-flop DD2, a CO output terminal of full adder FA2 is connected to an a2 input terminal of full adder FA2, a CO output terminal of full adder FA2 is connected to an input terminal of D flip-flop FA2, a CO output terminal of full adder FA2 is connected to a DD2 input terminal of D flip-flop FA2, a DD output terminal of full adder FA2 is connected to a DD2, and a DD output terminal of full adder FA2 is connected to a DD2, the CO output end of the full adder FA7 is connected to the input end of the D flip-flop DD5, the CO output end of the full adder FA8 is connected to the input end of the D flip-flop DD6, the CO output end of the full adder FA9 is connected to the input end of the D flip-flop DD7, the CO output end of the full adder FA10 is connected to the input end of the D flip-flop DD8, the clock input ends of the D flip-flops DD0 to DD9 are connected to the gate of the MOS transistor MN7, and the input end of the D flip-flop DD0 is connected to the output end of the D flip-flop DD10 of the previous stage of the bit control module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112290945A (en) * | 2020-09-30 | 2021-01-29 | 西安电子科技大学 | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC |
| CN114124100A (en) * | 2021-12-01 | 2022-03-01 | 南京邮电大学 | Noise-shaped SAR ADC with background mismatch calibration |
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2019
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112290945A (en) * | 2020-09-30 | 2021-01-29 | 西安电子科技大学 | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC |
| CN112290945B (en) * | 2020-09-30 | 2023-03-28 | 西安电子科技大学 | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC |
| CN114124100A (en) * | 2021-12-01 | 2022-03-01 | 南京邮电大学 | Noise-shaped SAR ADC with background mismatch calibration |
| CN114124100B (en) * | 2021-12-01 | 2024-03-22 | 南京邮电大学 | Noise shaping SAR ADC with background mismatch calibration |
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