CN113740713B - Test board for detecting whether PCB is incomplete in glue removal and test method thereof - Google Patents
Test board for detecting whether PCB is incomplete in glue removal and test method thereof Download PDFInfo
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- CN113740713B CN113740713B CN202111055227.2A CN202111055227A CN113740713B CN 113740713 B CN113740713 B CN 113740713B CN 202111055227 A CN202111055227 A CN 202111055227A CN 113740713 B CN113740713 B CN 113740713B
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- 238000012360 testing method Methods 0.000 title claims abstract description 157
- 239000003292 glue Substances 0.000 title claims abstract description 43
- 238000010998 test method Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 114
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 150000003071 polychlorinated biphenyls Chemical class 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000013329 compounding Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 230000002950 deficient Effects 0.000 claims 2
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000012795 verification Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02W—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO WASTEWATER TREATMENT OR WASTE MANAGEMENT
- Y02W30/00—Technologies for solid waste management
- Y02W30/50—Reuse, recycling or recovery technologies
- Y02W30/82—Recycling of waste of electrical or electronic equipment [WEEE]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a test board for detecting whether a PCB is incomplete in glue removal and a test method thereof, and provides a scheme for solving the problem that the incomplete glue removal test is inconvenient in the prior art. A plurality of through test holes are arranged in the test board, and then the test holes are connected on the upper, middle and lower inner layers in the laminated structure. And acquiring the three-dimensional position where the glue is not removed completely by using the open-close loops of different test holes. The method has the advantages that the designed test board is placed in the plasma process and is conducted for verification, so that the problem that a large number of new products are scrapped in the later period due to poor plasma parameter setting in the new product manufacturing process is greatly reduced. And slice observation is not needed, and the feedback speed is obviously improved.
Description
Technical Field
The invention relates to a front-end process for PCB production, in particular to a test board for detecting whether PCB is not completely removed, and a test method using the test board.
Background
As technology advances, existing PCBs, namely printed circuit boards, all use multi-layer board composite structures. The dielectric layer (prepreg) itself after lamination of the multilayer board contains a certain amount of resin, i.e. glue that the present technology method needs to remove.
The heat of the cutting tape due to the high speed rotation of the drill bit softens the resin during the drilling of the PCB. After the drill bit finishes drilling, the softened resin is pulled out and simultaneously is adhered to the inner layer ring, and the temperature is reduced. The resin hardens again.
The purpose of the removal is to remove the resin adhering to the inner ring (also known as removal). If the resin on the ring is not removed, the subsequent copper feeding can cause the copper on the hole wall and the inner ring to have normal conduction due to the blocking of the resin attached to the inner ring.
Most of the high-speed materials in the industry adopt plasma photoresist removal, and as the manufacturing of new products (especially new materials) of the high-speed materials is not experienced enough, the photoresist removal is often incomplete due to inaccurate plasma parameter setting in actual production, so that the whole batch of products are scrapped. Plasma removes glues and the wet process in the past removes glues differently, because equipment self exists the homogeneity problem, causes big aperture to remove glues the asynchronous problem of speed. The glue removal parameter setting of the equipment is not matched, so that the glue removal condition of a large aperture is ideal, but the glue removal is incomplete in a small aperture, so that the problem (ICD) of open circuit caused by incomplete glue removal of a product is caused.
In a production batch, at least ten times or more than twenty times of machine passing (glue removing through a plasma device) are needed, and each time of machine passing, dozens of PCBs are arranged, and the total quantity is up to more than hundred. For a PCB with thousands of holes, it is inefficient and impractical to drill a slice for each hole (e.g., CN105823704 a). Because the adhesive is removed, no good detection means is available, and the ICD is always found to have an open circuit when the ICD goes to the last electrical measurement procedure before delivery. This will bring a huge loss to the company and delay the delivery period. The detection means of the plasma process becomes key, and if ICDs exist in the process or after the completion of the process, the ICDs can be detected, so that the PCB can be remedied, and the loss is avoided.
Disclosure of Invention
The invention aims to provide a test board for detecting whether the PCB is not completely removed and a test method thereof, so as to solve the problems in the prior art.
The invention relates to a test board for detecting whether a PCB is not completely removed from glue, which comprises a board body, wherein more than one test module is arranged in the board body, and the test module is of a laminated structure formed by compounding and pressing multiple layers of resin;
the middle part of the test module is provided with a wiring area, and a plurality of first test holes are arranged in the wiring area; the outer side of the wiring area is also provided with a second test hole, a third test hole, a fourth test hole, a fifth test hole, a sixth test hole and a seventh test hole;
all the test holes longitudinally penetrate through the test module;
the inner layer board close to the top layer is provided with a first lead, one end of the first lead is connected with the second test holes, and the other end of the first lead is communicated with each first test hole one by one and finally connected with the third test holes;
the middle-bit inner layer plate is provided with a second lead, one end of the second lead is connected with the sixth test hole, and the other end of the second lead is communicated with each first test hole one by one and finally connected with the seventh test hole;
and a third lead is arranged on the inner layer board close to the bottom layer, one end of the third lead is connected with the fourth test hole, and the other end of the third lead is communicated with each first test hole one by one and finally connected with the fifth test hole.
The first wires are sequentially and longitudinally staggered and connected in the two layers of inner laminates close to the top layer to form a first linkage layer structure;
the second wires are sequentially and longitudinally staggered and connected in the middle two-layer laminated plate to form a second linkage layer structure;
and the third wires are sequentially and longitudinally connected in a staggered manner in the two layers of inner laminates close to the bottom layer to form a third interlayer structure.
The two layers of inner laminates close to the top layer are respectively a second layer and a third layer from top to bottom;
the two layers of inner laminates close to the bottom layer are respectively a second layer and a third layer which are the reciprocal layers from bottom to top;
if the total number of layers N of the laminated structure is even, the two middle-layer laminated plates are respectively an N/2 layer and an N/2+1 layer; if the total number of layers N of the laminated structure is an odd number, the two middle-layer inner laminates are respectively an (N+1)/2 th layer and an (N+1)/2+/-1 th layer.
All the joints of the test holes and each layer in the laminated structure are set as bonding pads.
In the wiring area, each first test hole is arranged in a two-row and multi-column mode; each wire forms a U-shaped wiring in the wiring region.
The first test holes are arranged in two rows and seven columns, and the intervals among the columns are equal.
The test modules are arranged in a matrix in the board body.
The aperture of each test hole in any test module is the same and is different from the apertures of other test modules in the same row and the same column.
The invention discloses a test method for detecting whether a PCB is not completely removed, which comprises the following steps:
s1, manufacturing the test board according to the total number of layers of the PCB to be glued in the same batch, so that the total number of layers of the laminated structure of the test board is the same as the total number of layers of the PCB;
s2, adjusting the working parameters of removing the adhesive; placing the test board and a plurality of PCBs to be subjected to glue removal on a station for machine passing; the test board is positioned in the middle of the station;
s3, obtaining a test board after removing the glue;
s4, carrying out a copper coating process on the test board after the photoresist is removed, so that copper is coated in each test hole;
s5, respectively testing electric loops corresponding to the first wire, the second wire and the third wire in each test module;
s6, if all the circuit loops are closed, judging that the glue removing working parameters of the step S2 are correct, and enabling the Printed Circuit Boards (PCB) which are on machine and waiting for machine to remove glue correctly, and entering the step S7; if any circuit has an open circuit, judging that the glue removing working parameters of the step S2 are incorrect, and returning to the step S1;
s7, sequentially passing the PCB to be subjected to glue removal through a machine to remove the glue.
And (5) auxiliary positioning of the test hole with incomplete photoresist removal by using the wiring area.
The test board for detecting whether the PCB is not completely removed and the test method thereof have the advantages that the designed test board is placed in the plasma process and is conducted for verification, so that the problem of large scrapping in the later period caused by poor plasma parameter setting in the new product manufacturing process is greatly reduced. From the previous situation that no specific quantitative index exists, the situation of the whole batch of plates can be judged by means of the conduction situation of the test plate. And slice observation is not needed, and the feedback speed is obviously improved.
Drawings
Fig. 1 is a schematic structural diagram of a test board for detecting whether a PCB is incompletely removed according to the present invention.
FIG. 2 is a schematic view of the structure of the module of the present invention with wiring hidden;
fig. 3 is a view in the direction K of fig. 2.
FIG. 4 is a schematic view of the structure of the module of the present invention when wired in the second and third layers;
fig. 5 is the view in the direction K of fig. 4, and other pad displays are simplified and fifth test hole displays are omitted.
FIG. 6 is a schematic view of the structure of the module of the present invention in the ninth and tenth layers of wiring;
fig. 7 is the view in the direction K of fig. 6, and other pad displays are simplified and the fifth test hole display is omitted.
FIG. 8 is a schematic view of the structure of the module of the present invention in the sixteenth and seventeenth layers of wiring;
fig. 9 is a view in the direction K of fig. 8 and simplifies the presentation of other pads.
FIG. 10 is a schematic view of the structure of the module of the present invention when the wiring of FIGS. 4, 6 and 8 is combined;
fig. 11 is a view in the direction K of fig. 10 and simplifies the presentation of other pads.
Reference numerals:
10-plate body, 11-test module;
20-wiring area, 21-first test hole, 22-second test hole, 23-third test hole, 24-fourth test hole, 25-fifth test hole, 26-sixth test hole, and 27-seventh test hole.
Detailed Description
As shown in fig. 1 to 3 and fig. 10 and 11, the test board for detecting whether the PCB is completely removed from the glue according to the present invention includes a board body 10, wherein 4*4 test modules 11 arranged in a matrix are disposed in the board body 10, and the test modules 11 are laminated structures formed by laminating multiple layers of resin. In the present embodiment, the total number of layers of the laminated structure n=18.
The test modules 11 have the same structure, and the difference is that the apertures of the built-in test holes are different, for example, in fig. 2 of the present embodiment: the aperture of all test holes of the No. 1 module is 0.25mm; the aperture of all test holes of the No. 2 module is 0.3mm; the aperture of all test holes of the No. 3 module is 0.35mm; the aperture of all test holes of the No. 4 module is 0.45mm. The arrangement mode adopts an orthogonal mode, and each row and each column contains No. 1, 2, 3 and 4 modules.
The middle part of the test module 11 is provided with a wiring area 20, and two rows and seven columns of first test holes 21 are arranged in the wiring area 20; the hole wall spacing of all the first test holes 21 was 0.3mm.
A second test hole 22, a third test hole 23, a fourth test hole 24, a fifth test hole 25, a sixth test hole 26 and a seventh test hole 27 are further arranged on the outer side of the wiring area 20.
All test holes longitudinally penetrate through the test module 11, and the joints of the test holes and each layer in the laminated structure are all arranged as bonding pads.
As shown in fig. 4 and 5, the inner layer board of the second layer and the third layer is provided with a first wire, one end of the first wire is connected to the second test hole 22, and the other end of the first wire is connected to each first test hole 21 one by one and finally is connected to the third test hole 23. The first wires are sequentially and longitudinally connected in a staggered manner in the second layer and the third layer to form a first linkage layer structure.
As shown in fig. 6 and 7, the inner layer board of the ninth layer and the tenth layer is provided with a second wire, one end of the second wire is connected to the sixth test hole 26, and the other end of the second wire is connected to each first test hole 21 one by one and finally connected to the seventh test hole 27. And the second wires are sequentially and longitudinally staggered and connected in the ninth layer and the tenth layer to form a second linkage layer structure.
If the total number of layers N of the laminated structure is even, the two middle-layer laminated plates are respectively an N/2 layer and an N/2+1 layer; if the total number of layers N of the laminated structure is an odd number, the two middle-layer inner laminates are respectively an (N+1)/2 th layer and an (N+1)/2+/-1 th layer. In this embodiment, n=18, and thus the two layers of the median are the ninth layer and the tenth layer, respectively. If n=19, the median two layers may be the ninth layer and the tenth layer, or may be the tenth layer and the eleventh layer. The purpose is to detect the gumming condition at the middle part, so that the specific layer number is not strictly limited, and the person skilled in the art can properly adjust the layer to other approximate layers in actual operation.
As shown in fig. 8 and 9, a third wire is provided on the inner layer board of the sixteenth layer and the seventeenth layer, and one end of the third wire is connected to the fourth test hole 24, and the other end of the third wire is connected to each of the first test holes 21 one by one and finally connected to the fifth test hole 25. And the third wires are sequentially and longitudinally staggered and connected in the sixteenth layer and the seventeenth layer to form a third layer structure.
Each wire forms a U-shaped wiring in the wiring region 20.
The testing method by using the testing board comprises the following specific steps:
s1, manufacturing the test board according to the total number of layers of the PCB to be glued in the same batch, so that the total number of layers of the laminated structure of the test board is the same as the total number of layers of the PCB;
s2, adjusting the working parameters of removing the adhesive; placing the test board and a plurality of PCBs to be subjected to glue removal on a station for machine passing; the test board is positioned in the middle of the station;
s3, obtaining a test board after removing the glue;
s4, carrying out a copper coating process on the test board after the photoresist is removed, so that copper is coated in each test hole;
s5, respectively testing electric loops corresponding to the first wire, the second wire and the third wire in each test module 11;
s6, if all the circuit loops are closed, judging that the glue removing working parameters of the step S2 are correct, and enabling the Printed Circuit Boards (PCB) which are on machine and waiting for machine to remove glue correctly, and entering the step S7; if any circuit has an open circuit, judging that the glue removing working parameters of the step S2 are incorrect, and returning to the step S1;
s7, sequentially passing the PCB to be subjected to glue removal through a machine to remove the glue.
The specific procedure of the test in step S6 is as follows: the loop condition of the first wire is tested by using the universal meter to contact the second test hole 22 and the third test hole 23 respectively, if a short circuit occurs, the auxiliary positioning of the wiring area 20 is utilized, the second test hole 22 is connected with the universal meter unchanged, the other end of the universal meter tries to contact the first test hole 21 one by one, and the test hole with incomplete glue removal can be obtained. And then testing the second wire and the third wire one by using a similar method, so that the three-dimensional position of the position where the glue is not removed in the test board in the test module 11 can be known. After all the test modules 11 are tested, the three-dimensional positions of the positions where the glue is not removed in the board body 10 can be obtained. The three-dimensional position with incomplete glue removal is known to be greatly beneficial to the subsequent plasma parameter adjustment work, so that the parameter can obtain the maximum benefit.
It will be apparent to those skilled in the art from this disclosure that various other changes and modifications can be made which are within the scope of the invention as defined in the appended claims.
Claims (9)
1. A test method for detecting whether the PCB is incomplete in glue removal is characterized by comprising the following steps:
s1, manufacturing a test board according to the total number of layers of a PCB to be glued in the same batch, so that the total number of layers of a laminated structure of the test board is the same as the total number of layers of the PCB;
s2, adjusting the working parameters of removing the adhesive; placing the test board and a plurality of PCBs to be subjected to glue removal on a station for machine passing; the test board is positioned in the middle of the station;
s3, obtaining a test board after removing the glue;
s4, carrying out a copper coating process on the test board after the photoresist is removed, so that copper is coated in each test hole;
s5, respectively testing electric loops corresponding to the first wire, the second wire and the third wire in each test module (11);
s6, if all the circuit loops are closed, judging that the glue removing working parameters of the step S2 are correct, and enabling the Printed Circuit Boards (PCB) which are on machine and waiting for machine to remove glue correctly, and entering the step S7; if any circuit has an open circuit, judging that the glue removing working parameters of the step S2 are incorrect, and returning to the step S1;
s7, sequentially passing the PCB to be subjected to glue removal through a machine to remove the glue;
the test board comprises a board body (10); more than one test module (11) is arranged in the plate body (10), and the test modules (11) are of a laminated structure formed by compounding and pressing multiple layers of resin;
the middle part of the test module (11) is provided with a wiring area (20), and a plurality of first test holes (21) are arranged in the wiring area (20); the outer side of the wiring area (20) is also provided with a second test hole (22), a third test hole (23), a fourth test hole (24), a fifth test hole (25), a sixth test hole (26) and a seventh test hole (27);
all the test holes longitudinally penetrate through the test module (11);
the inner layer board close to the top layer is provided with a first lead, one end of the first lead is connected with the second test holes (22), and the other end of the first lead is communicated with each first test hole (21) one by one and finally connected with the third test hole (23);
the middle-number inner layer plate is provided with a second lead, one end of the second lead is connected with a sixth test hole (26), and the other end of the second lead is communicated with each first test hole (21) one by one and finally connected with a seventh test hole (27);
and a third lead is arranged on the inner layer plate close to the bottom layer, one end of the third lead is connected with the fourth test holes (24), and the other end of the third lead is communicated with each first test hole (21) one by one and finally connected with the fifth test hole (25).
2. The test method for detecting whether the PCB is incomplete in photoresist removal according to claim 1, wherein the first wires are sequentially and longitudinally connected in a staggered manner in the two-layer laminated board close to the top layer to form a first linkage layer structure;
the second wires are sequentially and longitudinally staggered and connected in the middle two-layer laminated plate to form a second linkage layer structure;
and the third wires are sequentially and longitudinally connected in a staggered manner in the two layers of inner laminates close to the bottom layer to form a third interlayer structure.
3. The test method for detecting whether the PCB is defective in removing glue according to claim 2, wherein the two layers of the inner laminate close to the top layer are respectively a second layer and a third layer from top to bottom;
the two layers of inner laminates close to the bottom layer are respectively a second layer and a third layer which are the reciprocal layers from bottom to top;
if the total number of layers N of the laminated structure is even, the two middle-layer laminated plates are respectively an N/2 layer and an N/2+1 layer; if the total number of layers N of the laminated structure is an odd number, the two middle-layer inner laminates are respectively an (N+1)/2 th layer and an (N+1)/2+/-1 th layer.
4. The test method for detecting whether the PCB is defective in removing the paste according to claim 1, wherein the connection portions of all the test holes and the layers in the laminated structure are each provided as a bonding pad.
5. The testing method for detecting whether the PCB is not completely removed according to claim 1, wherein each first testing hole (21) is arranged in two rows and a plurality of columns in the wiring area (20); each wire forms a U-shaped wiring in the wiring region (20).
6. The method according to claim 5, wherein the first test holes (21) are arranged in seven rows and seven columns with equal spacing therebetween.
7. Test method for detecting whether a PCB is not completely gummed according to claim 1, characterized in that the test modules (11) are arranged in a matrix in the board body (10).
8. The method according to claim 7, wherein the apertures of the test holes in any test module (11) are the same as the apertures of the other test modules (11) in the same row and column.
9. The method for testing whether the PCB is not completely removed according to claim 1, wherein the wiring area (20) is used for assisting in positioning the test hole which is not completely removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111055227.2A CN113740713B (en) | 2021-09-09 | 2021-09-09 | Test board for detecting whether PCB is incomplete in glue removal and test method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111055227.2A CN113740713B (en) | 2021-09-09 | 2021-09-09 | Test board for detecting whether PCB is incomplete in glue removal and test method thereof |
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| Publication Number | Publication Date |
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| CN113740713A CN113740713A (en) | 2021-12-03 |
| CN113740713B true CN113740713B (en) | 2024-02-13 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020023889A (en) * | 2001-12-27 | 2002-03-29 | 박종선 | BGA printed circuit board and the manufacturing method |
| CN201859193U (en) * | 2010-09-30 | 2011-06-08 | 嘉联益科技股份有限公司 | Testing plate for singular or synchronous detection of through holes and blind holes |
| JP2016025227A (en) * | 2014-07-22 | 2016-02-08 | ウシオ電機株式会社 | Evaluation method of desmear treatment |
| CN105823704A (en) * | 2016-03-21 | 2016-08-03 | 东莞美维电路有限公司 | Method for testing PCB adhesive removing uniformity |
| CN107509302A (en) * | 2017-07-28 | 2017-12-22 | 胜宏科技（惠州）股份有限公司 | A kind of multi-functional wiring board detection module and detection method |
| CN207215006U (en) * | 2017-09-30 | 2018-04-10 | 定颖电子（昆山）有限公司 | A kind of four layers of PCB copper thickness test modules |
| CN108107342A (en) * | 2017-11-07 | 2018-06-01 | 广州兴森快捷电路科技有限公司 | Test module wiring method and test module |
-
2021
- 2021-09-09 CN CN202111055227.2A patent/CN113740713B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020023889A (en) * | 2001-12-27 | 2002-03-29 | 박종선 | BGA printed circuit board and the manufacturing method |
| CN201859193U (en) * | 2010-09-30 | 2011-06-08 | 嘉联益科技股份有限公司 | Testing plate for singular or synchronous detection of through holes and blind holes |
| JP2016025227A (en) * | 2014-07-22 | 2016-02-08 | ウシオ電機株式会社 | Evaluation method of desmear treatment |
| CN105823704A (en) * | 2016-03-21 | 2016-08-03 | 东莞美维电路有限公司 | Method for testing PCB adhesive removing uniformity |
| CN107509302A (en) * | 2017-07-28 | 2017-12-22 | 胜宏科技（惠州）股份有限公司 | A kind of multi-functional wiring board detection module and detection method |
| WO2019019339A1 (en) * | 2017-07-28 | 2019-01-31 | 胜宏科技（惠州）股份有限公司 | Multi-functional circuit board detection module and detection method |
| CN207215006U (en) * | 2017-09-30 | 2018-04-10 | 定颖电子（昆山）有限公司 | A kind of four layers of PCB copper thickness test modules |
| CN108107342A (en) * | 2017-11-07 | 2018-06-01 | 广州兴森快捷电路科技有限公司 | Test module wiring method and test module |
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| CN113740713A (en) | 2021-12-03 |
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