CN1126022C - Signal processor - Google Patents
Signal processor Download PDFInfo
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- CN1126022C CN1126022C CN99813027A CN99813027A CN1126022C CN 1126022 C CN1126022 C CN 1126022C CN 99813027 A CN99813027 A CN 99813027A CN 99813027 A CN99813027 A CN 99813027A CN 1126022 C CN1126022 C CN 1126022C
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- 238000000034 method Methods 0.000 claims description 31
- 230000003139 buffering effect Effects 0.000 claims description 13
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 241001269238 Data Species 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 230000001172 regenerating effect Effects 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Detection And Correction Of Errors (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The bus width of a data bus 18 used among data transmission parts of memory control parts 15, error correction parts 16, main I/F parts 17, etc. has 32 bits, and the bus width of a memory data bus 19 for data transmission among a buffer memory 12 and the memory control parts 15 has 64 bits so that the present invention can access data from the buffer memory 12 by using 64 bits as a unit and treat each part by using the 32 bits as a unit. Thus, the data of 32 bits transmitted by the data bus 18 among the parts is always effective so as to achieve the purpose of high access speed from each part in a system to the buffer memory 12.
Description
Technical field
Signal processing apparatus when the present invention relates to obtain to be applicable to the record regenerating of external memory storage etc. of computing machine, particularly, in order to realize storer is carried out the high-level efficiency of access.
Background technology
With the 5th figure, the 6th figure illustrates the CD-ROM (Compact Disc-Read Only Memory) that occurs as the signal Processing LSI (large scale integrated circuit) that comprises storer etc.In the 5th figure, the 11st, the recording medium of CD-ROM etc., the 12nd, the memory buffer of storage data, the 13rd, principal computer, the 14th, obtain the decoding parts of data from recording medium 11, the 15th, by the storage access from each parts being required the memory control unit of enforcement access on storer, the 16th, if be collected in the wrong then error correction component that corrects of data in the memory buffer 12, the 17th, the data that are used for being collected in memory buffer 12 are sent to main I/F (interface) parts of principal computer 13, the 18th, being used at the width that transmits data between each parts and the memory control unit 15 is data bus between 16 the parts, the 19th, and the width that is used for transmitting data between memory buffer 12 and memory control unit 15 is 16 a memory data bus.
Secondly, we are divided into the buffered that is sent to memory buffer 12 from recording medium 11 with signal Processing, correction process, and the main transmission of the data after the correction is handled and is illustrated.
(1) buffered
On recording medium 11, use fixed data unit the CD-ROM data are interlocked handle postscript and record.1 frame is that the data by 1176 words (word=16) constitute, and will be input to decoding parts 14 as serial data from the data that recording medium 11 is read.After decoding detects frame synchronizing signal in the parts 14, this signal is carried out the serial conversion, be that the data that data bus 18 between 16 the parts will be removed 1170 words of frame synchronizing signal are sent to memory control unit 15 by width.Memory control unit 15, the memory data bus 19 that by width is 16 is with the data write buffering memory 12 that receives.
(2) correction process
Collected the data of 1 frame in memory buffer 12 after, error correction component 16, through the data bus 18 between the parts, memory control unit 15 and memory data bus 19, and, carry out the correction process of 1 frame by memory buffer 12 is carried out access.
(3) the main transmission handled
At least after the data of 1 frame being finished correction process, main I/F parts 17, by memory data bus 19, memory control unit 15, the data bus 18 between the parts from buffering storer 12 sense datas, is sent to principal computer 13 with these data.
By the 6th (a), (b), (c) streamline shown in the figure is controlled above-mentioned buffering for respectively, error correction, and main the transmission handled, buffering, correction process must be finished the processing of 1 frame in 1 frame time.But, transmit for main, not necessarily must in 1 frame time, finish the processing of 1 frame, the 6th (c) figure expression with the timing shown in scheming, can be carried out the transmission of suitable frame data when main transmission.
The 4th figure, because demonstrate the logical format of CD-ROM, so having represented to remove the data of 1 frame of frame synchronizing signal constitutes, again, in CD-ROM, will be in 2352 bytes of 1 frame, the data of removing 2340 bytes after the frame synchronizing signal of 6 * 2 bytes are divided into even bytes and odd bytes, to each independently the set of the data of 1170 bytes carry out correction process.
In the 4th figure, the data of 2340 bytes of 1 frame and 0～1169 font size sign indicating number (word=16) are showed accordingly.On CD-ROM, the P parity and the Q parity of additional error correction code are shown in the 4th figure, correction process with the P parity, as the 0th word, the 43rd word ... .. is like that, data with 43 words of being separated by are carried out, with the correction process of Q parity, as the 0th word, the 44th word, ... .. carries out with the data of 44 words of being separated by like that.
Like this, when using existing signal processing apparatus, when the width of the memory data bus by strengthening memory buffer 12 improves correction process speed, with existing method of in memory buffer 12, collecting data, exist the such problem of storage access that can not be used for error correction expeditiously.
As following will stating in detail, when the width of considering the memory data bus by strengthening memory buffer 12 here improves correction process speed, because will sequentially be collected in from the data that recording medium 11 is read the memory buffer 12, promptly collect with the CD-ROM logical format of the 4th figure, so the width of the memory data bus of memory buffer 12 is above 16, for example when becoming 64, can not be used for the storage access of error correction expeditiously.
We describe with the 4th figure, when carrying out correction process with the P parity, carry out access by 18 pairs of memory buffer of bus 12 with 32, with initial font size sign indicating number 0000 and 0001, next font size sign indicating number 0042 and 0043 such order, read and amount to 64 data, but because calculate, so only calculate the data of font size sign indicating number 0000,0043 with the data of 43 words of being separated by, and do not use 32 data of font size sign indicating number 0001,0042.When carrying out correction process with the Q parity, similarly, with initial font size sign indicating number 0000 and 0001, secondly font size sign indicating number 0044 and 0045 such order are read 64 data altogether, because calculate with the data of 44 words of being separated by, so only handle font size sign indicating number 0000,0044 data, and do not use 32 data of font size sign indicating number 0001,0045.
Announcement of the present invention
The feature of the signal processing apparatus of record is in the 1st of claims of the present invention, from a plurality of parts, pass through memory control unit, the memory buffer that is connected with the memory data bus that first highway width is arranged is carried out access, carry out in the signal processing apparatus that data read, have by above-mentioned memory data bus data are write above-mentioned memory buffer, with the memory of data control assembly that goes out to be stored in from the buffering memory read this memory buffer, with second highway width narrower than first above-mentioned highway width arranged, data bus between the parts that transmit above-mentioned data between above-mentioned a plurality of parts and the above-mentioned memory control unit, above-mentioned memory control unit, when from above-mentioned memory buffer sense data, data on the above-mentioned memory data bus are configured on the data bus between the above-mentioned parts again, when data are write above-mentioned memory buffer, data on the data bus between the above-mentioned parts are configured on the above-mentioned memory data bus again, this signal processing apparatus is by reducing the storage access number of times, carry out zero access to memory buffer, the high efficiency of storage access can be realized, and the scale of circuit can be suppressed.
Secondly, the feature of the signal processing apparatus of record is in the 2nd of claims, in the 1st the signal processing apparatus of claims, have by above-mentioned memory control unit and be connected with above-mentioned memory buffer, be kept at simultaneously in the above-mentioned memory buffer, the error correction component of the correction process of the data of at least 2 frames, this signal processing apparatus can reduce useless storage access by simultaneously the data that are kept at a plurality of frames in the memory buffer being carried out correction process.
Secondly, the feature of the signal processing apparatus of record is in the 3rd of claims, in the 1st the signal processing apparatus of claims, above-mentioned memory control unit, when will be from record medium, by the data of continuous N frame forming of fixed number of words when being collected in the memory buffer, with the 1st frame data, be collected in the above-mentioned memory buffer with being separated by the N-1 word, with the 2nd frame data, be separated by N-1 word ground and above-mentioned the 1st frame data are adjacent to be collected in the above-mentioned memory buffer, later in turn with N frame data, be separated by N-1 word ground and N-1 frame data are adjacent to be collected in the above-mentioned memory buffer, N digital data of different frame is collected in the above-mentioned memory buffer continuously, this signal processing apparatus reduces the storage access number of times by increasing to the highway width of memory buffer, can realize the high efficiency of buffer memory access.
The simple declaration of all figure
The 1st figure is the block scheme of the signal processing apparatus in example of the present invention.
The 2nd figure is the figure that is used for illustrating in the streamline control of the signal processing apparatus of example of the present invention.
The 3rd figure is used for the figure of pattern ground explanation at the data collection form of the memory buffer of the signal processing apparatus of example of the present invention.
The 4th figure is the figure that is used to illustrate existing CD-ROM logical format.
The 5th figure is the block scheme of existing signal processing apparatus.
The 6th figure is the figure that is used to illustrate the streamline control of existing signal processing apparatus.
Be used to implement optimal morphology of the present invention
(example 1)
Below, we illustrate the working of an invention form of record among the 1st of claims of the present invention with the 1st figure to the 3 figure.
In the 1st figure, basic comprising is identical with existing device, but be used at memory control unit 15 in order, error correction component 16, the highway width of the data bus 18 between each parts of main I/F parts 17 grades between the parts of transmission data has 32 width, again, 64 width this respect is arranged is different to the highway width that is used between memory buffer 12 and memory control unit 15 transmitting memory of data data bus 19.
Make the data of same number of frames number adjacent like that, the data of 2 continuous frames that will be shown in the 3rd figure (" even (idol) " frame and " odd (very) " frame) are collected in the memory buffer 12.According to such storer collection form, the good storage access of efficient in the time of can realizing error correction.Below our explanation as (1) buffered of signal processing apparatus, (2) correction process, (3) main transmits work of handling.
(1) buffered
To deposit decoding parts 14 from the serial data that recording medium 11 is read in.14 pairs of data that deposit in of decoding parts are carried out the serial conversion, and the data bus 18 by 32 bit widths between the parts is sent to memory control unit 15 with these data.Again, decoding parts 14 address information that also will carry out the memory buffer 12 of access is sent to memory control unit 15.On memory control unit 15, data with the address information that sends from decoding parts 14, are collected in the memory buffer 12 with the collection form as the 3rd figure.Particularly, by making from empty word between the word of two continuous digital data of the same frame that sends of decoding parts 14 and the word, collect the digital data of the same word number of other frame there, 32 bit data are configured in again on the memory data bus 19 of 64 bit widths, and write buffering memory 12.
(2) correction process
After being collected in the data (4680 byte) of 2 frames in the memory buffer 12, error correction component 16 will be used for being sent to memory control unit 15 from the address information of buffering storer 12 sense datas.Memory control unit 15, memory data bus 19 by 64 bit widths, with the address information that sends from error correction component 16, from buffering storer 12 sense datas, the data that add up to two words that " even (idol) " frame He " odd (the very) " frame of same word number shown in the 3rd figure will be arranged, be configured to again on the data bus 18 between the parts, and be sent to error correction component 16.On error correction component 16, be that unit carries out correction process with the byte.That is, will import 4 error calculators, handle side by side from the data that memory control unit 15 is read.From each mistake result of calculation, calculate wrong position and pattern, if wrong, then error correction component 16, by the data bus between the parts 18, with address information being sent to memory control unit 15, transmit wrong patterns information.Memory control unit 15, with the address information that receives from error correction component 16, from buffering storer 12 sense datas, data are carried out error correction by memory data bus 19 according to wrong patterns information, by memory data bus 19 with data write buffering memory 12.
The 2nd figure is the figure of the streamline control of explanation in this example, but because streamline control is that unit carries out with 2 frames in this example, so as respectively by the 2nd (b), (c) shown in the figure like that, after the buffered that finishes 2 frames shown in the 2nd (a) figure, carry out error correction, after correction process, lead transmission through 2 frames shown in the 2nd (b) figure.Like this, by being the processing that unit carries out each parts with 32, can improve the efficient of access to per 2 frames.
If state in more detail, then in the 3rd figure, when carrying out the correction process of P parity bit, for 64 of each per 2 words of the 0th continuous frame and the 1st frame, memory buffer 12 is carried out access, and wherein, only 32 to the 0th word of the 0th frame and the 1st frame carry out correction process, secondly, 32 to the 43rd word of the 0th frame and the 1st frame carry out correction process.
The correction process of Q parity bit similarly, for 64 of each per 2 words of the 0th continuous frame and the 1st frame, memory buffer 12 is carried out access, wherein, only 32 to the 0th word of the 0th frame and the 1st frame carry out correction process, secondly, 32 to the 44th word of the 0th frame and the 1st frame carry out correction process.That is, be the unit sense data from buffering storer 12 with 64, but wherein,, reduce the storage access number of times, reach the purpose that makes the access to store high efficiency by being that unit carries out correction process with 32.
In addition, in superincumbent the stating, we have illustrated the situation of carrying out 2 above-mentioned frame data are collected in with being separated by a word buffered in the memory buffer 12, in this case, the data of 2 frames are carried out correction process simultaneously, but as the frame number that is collected in the memory buffer 12, also can carry out buffered by N-1 the word of being separated by, the data of N frame of collection, in this case, it is clear and definite carrying out correction process simultaneously to the data of N frame.
(3) the main transmission handled
After the correction process that finishes each 2 frames, the address information that main I/F parts 17 will be used for access memory buffer 12 is sent to memory control unit 15.Memory control unit 15, with the address information that sends from main I/F parts 17, the memory data bus 19 by 64 bit widths is from buffering storer 12 sense datas.Memory control unit 15 in 4 digital data of reading, is configured to each of two digital data of the continuous font size sign indicating number of same frame again on the data bus 18 of 32 bit widths between the parts, and is sent to main I/F parts 17.Main I/F parts 17 are sent to principal computer 13 with the data that receive.
By such formation, with 64 is that unit carries out the access to memory buffer 12, but by being the processing that unit carries out each parts with wherein 32,32 bit data that on the data bus between the parts 18, transmit, because always become active data, so can not make the decrease in efficiency of correction process, can make access speed high speed from intrasystem each parts to memory buffer 12.
The possibility of industrially utilizing
When the present invention relates to obtain to be applicable to the record regenerating of external memory storage etc. of computer Signal processing apparatus, particularly, in order to realize improving the purpose to the access speed of memory, And realize improving the purpose of all processing speeds of signal processing apparatus.
Claims (3)
1. signal processing apparatus, its feature is
By memory control unit, from a plurality of parts, the memory buffer that is connected with the memory data bus that first highway width is arranged is carried out access, in the signal processing apparatus that the line data of going forward side by side is read, have
By above-mentioned memory data bus with data write above-mentioned memory buffer and from the buffering memory read go out to be stored in this memory buffer the memory of data control assembly and
Second highway width narrower than first above-mentioned highway width arranged, the data bus between the parts that transmit above-mentioned data between above-mentioned a plurality of parts and the above-mentioned memory control unit,
Above-mentioned memory control unit, when from above-mentioned memory buffer sense data, data on the above-mentioned memory data bus are configured on the data bus between the above-mentioned parts again, when data are write above-mentioned memory buffer, the data on the data bus between the above-mentioned parts are configured on the above-mentioned memory data bus again.
2. signal processing apparatus as claimed in claim 1 is characterized in that:
In this signal processing apparatus, have
Be connected with above-mentioned memory buffer by above-mentioned memory control unit, be kept at the error correction component of correction process of the data of at least 2 frames in the above-mentioned memory buffer simultaneously.
3. signal processing apparatus as claimed in claim 1 is characterized in that:
In this signal processing apparatus:
Above-mentioned memory control unit
When will from the record medium by the data of continuous N frame forming of fixed number of words when being collected in the memory buffer, the 1st frame data are collected in the above-mentioned memory buffer with being separated by N-1 word, be adjacent to be collected in be separated by N-1 word and above-mentioned the 1st frame data of the 2nd frame data in the above-mentioned memory buffer, later in turn N frame data are separated by N-1 word and N-1 frame data are adjacent to be collected in the above-mentioned memory buffer, and
N digital data of different frame is collected in the above-mentioned memory buffer continuously.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1999/004863 WO2001018639A1 (en) | 1999-09-08 | 1999-09-08 | Signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1325510A CN1325510A (en) | 2001-12-05 |
| CN1126022C true CN1126022C (en) | 2003-10-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99813027A Expired - Fee Related CN1126022C (en) | 1999-09-08 | 1999-09-08 | Signal processor |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100390120B1 (en) |
| CN (1) | CN1126022C (en) |
| WO (1) | WO2001018639A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013508885A (en) * | 2009-10-26 | 2013-03-07 | ウェアラブル・インコーポレイテッド | Simultaneous access to a memory pool shared between block access devices and graph access devices |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04195234A (en) * | 1990-11-22 | 1992-07-15 | Fujitsu Ltd | Data transfer system |
| JP2836321B2 (en) * | 1991-11-05 | 1998-12-14 | 三菱電機株式会社 | Data processing device |
| WO1993019424A1 (en) * | 1992-03-18 | 1993-09-30 | Seiko Epson Corporation | System and method for supporting a multiple width memory subsystem |
| KR100189531B1 (en) * | 1996-06-10 | 1999-06-01 | 윤종용 | Sector data decoding method and circuit in a cd-rom driver |
| US6393520B2 (en) * | 1997-04-17 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Data processor and data processing system with internal memories |
| KR20000065450A (en) * | 1999-04-03 | 2000-11-15 | 구자홍 | Bus Interface System and Bus Interface Method using the system |
| KR20000074477A (en) * | 1999-05-21 | 2000-12-15 | 윤종용 | Bus converter |
-
1999
- 1999-09-08 CN CN99813027A patent/CN1126022C/en not_active Expired - Fee Related
- 1999-09-08 KR KR10-2001-7005702A patent/KR100390120B1/en not_active IP Right Cessation
- 1999-09-08 WO PCT/JP1999/004863 patent/WO2001018639A1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR100390120B1 (en) | 2003-07-04 |
| WO2001018639A1 (en) | 2001-03-15 |
| KR20010107946A (en) | 2001-12-07 |
| CN1325510A (en) | 2001-12-05 |
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Granted publication date: 20031029 Termination date: 20110908 |