KR20000074477A - Bus converter - Google Patents

Abstract

PURPOSE: A bus converter is to provide a bus converter which can convert the width of buses simply. CONSTITUTION: A bus converter(100) is composed of a data valid signal converting circuit(10), a data width converting circuit(20) and a data converting buffer(30). The data valid signal converting circuit(10) inputs A-bus width information, B-bus width information, data direction information and a reference data valid signal and generates a converting data valid signal(B-bus data_valid). The data width converting circuit(20) inputs the A-bus width information, the B-bus width information and the data direction information and controls the operation of the data converting buffer(30). The data converting buffer(30), according to the control of the data width converting circuit(20), converts the width of a data(A-bus data_in or B-bus data_in) inputted through one bus and outputs it through the other bus.

Description

Bus converter

The present invention relates to a bus converter supporting variable data widths.

In the prior art, most memory management units (MMUs) support one memory and one bus. For example, if four 16M DRAM memories are attached externally, the bus is fixed at 16 bits or 32 bits.

As such, the conventional memory control apparatus supports only a unified memory, thereby reducing the flexibility of the system. In addition, even if a variable bus is supported, a logic and a buffer for converting the bus width are entered at every point where the width of the bus changes, which causes a complicated design and a high cost.

It is an object of the present invention to provide a bus converter that can easily convert the width of a bus, which is devised to solve the above problems.

1 is a block diagram shown to conceptually illustrate the operation of a bus converter.

2 is a block diagram showing the configuration of a bus converter according to the present invention.

FIG. 3 shows a case in which an external memory of m bits is connected to the A bus of the device shown in FIG. 2 and an n-bit memory user is connected to the B bus.

4A and 4B are timing diagrams showing the operation of the apparatus shown in FIG. 2 and show the case where m = 32 and n = 32.

5A and 5B are timing diagrams showing the operation of the apparatus shown in FIG. 2, in which m = 64 and n = 32.

6A and 6B are timing diagrams showing the operation of the apparatus shown in FIG. 2 and show the case where m = 32 and n = 64.

7A and 7B are timing diagrams showing the operation of the apparatus shown in FIG. 2 and show the case where m = 64 and n = 64.

The bus converter according to the present invention for achieving the above object in the apparatus for converting the data width between the two data bus, bus width information indicating the bus width of the two buses, data direction signal indicating the data transfer direction, data A data valid signal conversion circuit for generating data valid signals of a bus provided with data by introducing data valid signals of a bus providing a data; A data width conversion circuit for inputting bus width information to control an operation of a data conversion buffer; And a data conversion buffer for converting a width of data input through one of the buses under the control of the data width conversion circuit and outputting the data through the other bus in response to the conversion data valid signal. do. Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram shown to conceptually illustrate the operation of a bus converter. The bus converter shown in FIG. 1 controls the transfer of data in both directions between the A bus and the B bus based on the operating environment input signal. Here, the widths of the A and B buses are variable and may be the same or different.

The operating environment input signal includes bus width information of the A bus, bus width information of the B bus, and data direction information. The reference data valid signal is a signal provided from the data providing side and is a signal necessary for generating the converted data valid signal. The converted data valid signal is a signal for indicating a valid section of the converted data.

Most digital devices require memory. Unless it's a very simple system, there are many clients who want to use memory (called memory users), and you need a device to control the efficient use of memory among them. As such, a device for efficiently managing and controlling the memory between the memory and the memory user is a memory control device.

The memory control device reads and writes data through control of mounted memory, and is responsible for arbitration and data transfer between various memory users.

Previous digital devices have supported fixed memory types, sizes, and data bus widths. For example, some buses have limitations such as 16 bits of bus width and 16M bits of memory. This was due to the small change in memory capacity and the lack of support for various memories.

However, with the rapid development of electronic technology, especially semiconductor technology, many digital devices (ICs, systems, etc.) as well as memories require complex functions, and mass production is required to reduce costs. As a result, a single device can be implemented to support multiple levels (low cost, mid price, and high end). Therefore, it is necessary to support various kinds of memories in one digital signal processing apparatus.

In addition, as the width of the data bus increases, problems caused by large data buses moving around inside the digital signal processing apparatus (increasing the size and power of the device) also become serious.

To overcome this, memory users, who need to have a large bus width for fast memory access, use a wide bus, and memory users whose memory access speed is not very fast use a narrow bus.

Accordingly, digital signal processing apparatuses must solve the problem of a difference in bus width between memory and memory users.

2 is a block diagram showing the configuration of a bus converter according to the present invention. The device 100 shown in FIG. 1 includes a data valid signal conversion circuit 10 and a data width conversion circuit 20, and a data conversion buffer 30. ).

The data valid signal conversion circuit 10 introduces bus width information and a reference data valid signal to generate a converted data valid signal.

The data width conversion circuit 20 inputs bus width information to control the operation of the data conversion buffer 30. The data conversion buffer 30 converts the width of data input through one bus under the control of the data width conversion circuit 20 and outputs the data through the other bus.

The operation of the apparatus shown in FIG. 2 will be described in detail. FIG. 3 shows a case in which an external memory of m bits is connected to the A bus of the apparatus shown in FIG. 2 and an n-bit memory user is connected to the B bus.

1) When m = 32, n = 32

The memory bus (A bus) is 32 bits, and the system bus (B bus) is 32 bits. In this case, since the A and B buses have the same bus width, the bus converter 100 bypasses the data of each bus as it is.

a) READ operation

In this case, data valid signals and data inputs from the A bus connected to the external memory and the B bus connected to the memory user are accepted and exported.

4A is a timing diagram showing the timing of the read operation, the highest signal being a clock signal, the second being an A bus valid signal, the third being an A bus data, and the fourth being an B bus valid signal. And the fifth is the data of the B-bus.

Data input through the A bus connected to the memory is output through the B bus connected to the memory user after the B bus valid signal occurs.

b) Write operation (WRITE)

Fig. 4B is a timing diagram showing the timing of the write operation. The clock signal shown at the top is the A bus valid signal, the second is the data of the A bus, and the fourth is the B bus valid signal. And the fifth is the data of the B-bus.

Data input through the B bus connected to the memory user outputs the A bus connected to the external memory after the B bus valid signal occurs.

2) When m = 32, n = 64

The memory bus (A bus) is 32 bits and the system bus (B bus) is 64 bits. In this case, the bus converter 100 takes action to match the bus width.

a) READ operation

In this case, data is input in 32-bit units through the A-bus connected to the external memory, so the odd-numbered data is stored in the internal buffer, and when the even-numbered data comes in, the combination is made into 64-bit data and the B-bus connected to the memory user. Output through In addition, the B bus valid signal occurs only during the period in which the odd data is input from the A bus.

Fig. 5A is a timing diagram showing the timing of the read operation, the clock signal shown at the top, the A bus valid signal shown second, the data shown on the A bus shown the third, and the B bus valid signal shown the fourth. And the fifth is the data of the B-bus.

Data input through the A bus connected to the memory is output through the B bus connected to the memory user after the B bus valid signal occurs.

b) Write operation (WRITE)

In the write operation, since the data input through the B bus is 64 bits, the data is stored in the internal buffer and divided into 32 bits of data to be output through the A bus connected to the external memory twice. The B-bus valid signal is emitted once every two clocks.

Fig. 5B is a timing diagram showing the timing of the write operation, the highest one being a clock signal, the second one being the A bus valid signal, the third one being the data of the A bus, and the fourth one being the B bus valid signal. And the fifth is the data of the B-bus.

Data input through the B bus connected to the memory user outputs the A bus connected to the external memory after the B bus valid signal occurs.

3) when m = 64, n = 32

The memory bus (A bus) is 64 bits and the system bus (B bus) is 32 bits. In this case, the bus converter 100 takes action to match the bus width.

a) READ operation

In this case, data is input in 64-bit units through the B-bus connected to the memory user, so the data is stored in the internal buffer and divided into 32-bit data and output through the A-bus connected to the memory user twice.

Fig. 6A is a timing diagram showing the timing of the read operation, in which the uppermost part is a clock signal, the second one is the A bus valid signal, the third is the data of the A bus, and the fourth is the B bus valid signal. And the fifth is the data of the B-bus.

Data input through the A bus connected to the memory is output through the B bus connected to the memory user after the B bus valid signal occurs.

b) Write operation (WRITE)

In the write operation, the data input through the B bus is 32-bit, so the odd-numbered data is stored in the internal buffer, and when the even-numbered data comes in, the combination is made into 64-bit data and output through the A bus connected to the external memory. .

Data input through the B bus connected to the memory user is output through the A bus connected to the external memory after the A bus valid signal is generated.

Fig. 6B is a timing diagram showing the timing of the write operation. The clock signal shown at the top is the A bus valid signal, the second is the data of the A bus, and the fourth is the B bus valid signal. And the fifth is the data of the B-bus.

Data input through the B bus connected to the memory user outputs the A bus connected to the external memory after the A bus valid signal occurs.

4) When m = 64, n = 64

The memory bus (A bus) is 64-bit and the system bus (B bus) is 64-bit. In this case, since the A and B buses have the same bus width, the bus converter 100 bypasses the data of each bus as it is.

a) READ operation

In this case, data valid signals and data inputs from the A bus connected to the external memory and the B bus connected to the memory user are accepted and exported.

Fig. 7A is a timing diagram showing the timing of the read operation. The clock signal shown at the top is the A bus valid signal, the second is the data of the A bus, and the fourth is the B bus valid signal. And the fifth is the data of the B-bus.

Data input through the A bus connected to the memory is output through the B bus connected to the memory user after the B bus valid signal occurs.

b) Write operation (WRITE)

FIG. 7B is a timing diagram showing the timing of the write operation. The clock signal at the top is the A bus valid signal, the second is the A bus valid signal, the third is the data on the A bus, and the fourth is the B bus valid signal. And the fifth is the data of the B-bus.

Data input through the B bus connected to the memory user outputs the A bus connected to the external memory after the B bus valid signal occurs.

In the apparatus shown in FIG. 2, a process of controlling the data conversion buffer to convert the width of data input through one bus and output the data through the other bus is performed as follows.

1) A bus width information indicating bus widths of two buses, a data direction signal indicating a data transfer direction, and data valid signals of a bus providing data are introduced to generate a data valid signal of a bus to which data is provided.

2) The data conversion buffer is controlled to convert the width of data input through one bus in response to the conversion data valid signal and output the data through the other bus.

Accordingly, the data conversion buffer converts the data width by referring to the bus width information and outputs the converted result to the other data bus.

As described above, the bus converter according to the present invention has the effect of improving the flexibility of the system by converting the width of the data bus.

Claims (3)

In an apparatus for converting data width between two data buses, Bus valid information indicating bus width of two buses, data direction signal indicating data transfer direction, and data valid signals of buses providing data by injecting data valid signals of buses providing data. Conversion circuit; A data width conversion circuit for inputting bus width information to control an operation of a data conversion buffer; And And a data converting buffer for converting a width of data input through one bus under the control of the data width converting circuit and outputting the converted data through the other bus in response to the converted data valid signal. 2. The bus converter of claim 1, wherein one bus is connected to an external memory and the other busten memory user. A method of controlling a data conversion buffer for converting a width of data input through one bus and outputting the data through the other bus, Generating a data valid signal of a bus to which data is supplied by injecting bus width information indicating bus widths of two buses, a data direction signal indicating a data transfer direction, and data valid signals of a bus providing data; And And controlling the data conversion buffer so as to convert the width of data input through one bus in response to the conversion data valid signal and output the data through the other bus.