CN112600540B - High-precision comparator suitable for current demodulation in wireless charging - Google Patents

High-precision comparator suitable for current demodulation in wireless charging Download PDF

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CN112600540B
CN112600540B CN202110237621.1A CN202110237621A CN112600540B CN 112600540 B CN112600540 B CN 112600540B CN 202110237621 A CN202110237621 A CN 202110237621A CN 112600540 B CN112600540 B CN 112600540B
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switch
comparison unit
stage
comparator
input
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CN112600540A (en
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陈俊宇
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Shanghai Southchip Semiconductor Technology Co Ltd
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Southchip Semiconductor Technology Shanghai Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H02J7/00714—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery charging or discharging current

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A high-precision comparator suitable for current demodulation in wireless charging utilizes an input filtering module to filter out direct-current components and high-frequency overshoot components in signals input by the comparator, utilizes a hysteresis comparison module to complete comparison and input offset elimination, connects two blocking capacitors between the output of a first-stage comparison unit and the input of a second-stage comparison unit, and switches the input connection of the two-stage comparison units under the control of a logic module; in the offset elimination stage, the input of the two-stage comparison unit is controlled to be grounded, the output signal of the comparator is latched, and the input offset information is stored on the two blocking capacitors; the comparison stage controls a first positive input end of the first-stage comparison unit to be connected with the output of the input filter module, a second positive input end of the first-stage comparison unit to be connected with the first hysteresis comparison voltage or the second hysteresis comparison voltage according to the output signal of the comparator, the input of the second-stage comparison unit is connected with the two blocking capacitors, and the input offset of the comparator and offset information stored in the blocking capacitors are mutually offset, so that the offset of the comparator is eliminated.

Description

High-precision comparator suitable for current demodulation in wireless charging
Technical Field
The invention belongs to the technical field of wireless charging in an analog integrated circuit, and relates to a high-precision comparator suitable for current demodulation in wireless charging.
Background
In a wireless charging system, the switching frequency of a coil is generally above 100KHz, the current/voltage of the coil can be changed by adjusting the impedance of a load end, the process of coding and adjusting is called as modulation, and the modulation frequency is 1 KHz. The process of collecting, sensing the change of the coil current and converting the change into the digital code is called as demodulation.
The traditional demodulation method is to pass the input signal through a capacitor CHFAnd a resistor RHFAfter the high-pass filter is formed, the high-pass filter is compared in a hysteresis comparator, and the threshold value of the hysteresis comparator is hysteresis voltage VHYSand-VHYSSo that the comparator has 2VHYSThe noise margin of (2). As shown in fig. 1, it is a strip input heightThe truth table of the data selector MUX is shown in FIG. 2. when the comparator output voltage CMP _ OUT inputted from the S terminal, i.e. the selection terminal, of the data selector MUX is high, the data selector MUX outputs the signal of the B input terminal, i.e. outputs the hysteresis voltage + VHYS(ii) a When the comparator output voltage CMP _ OUT inputted to the S terminal of the data selector MUX is at a low level, the data selector MUX outputs a signal of the A input terminal thereof, i.e., outputs a hysteresis voltage-VHYS。
When the current modulation signal is good and the offset voltage of the comparator itself is low, the demodulation can be performed correctly, and the waveform diagram at this time is as shown in fig. 3. If the signal is poor, for example, the input signal rings too much, which may result in demodulation failure, the waveform diagram at this time is shown in fig. 4, and it can be seen that the waveform has large rings, and the demodulation error rate is increased. In addition, if the offset voltage ratio of the comparator itself is large, demodulation failure may also be caused, and a waveform diagram at this time is shown in fig. 5, it can be seen that the offset voltage ratio of the comparator itself is large, and the demodulation error rate may also increase.
Disclosure of Invention
Aiming at the problem that the traditional hysteresis comparator fails to demodulate due to overlarge ringing of an input signal or maladjustment of the comparator, the invention provides a high-precision comparator suitable for current demodulation in wireless charging, wherein an input filtering module is used for correcting a current waveform with larger overshoot, the current overshoot passing through the input filtering module is reduced, and the amplitude has certain loss; the hysteresis comparison module is then used to eliminate the offset of the comparator, thereby reducing the demodulation error rate of the circuit.
The technical scheme of the invention is as follows:
a high-precision comparator suitable for current demodulation in wireless charging comprises an input filter module and a hysteresis comparison module,
the input filtering module is used for filtering a direct current component and a high-frequency overshoot component in the input signal of the comparator and outputting the filtered direct current component and the filtered high-frequency overshoot component;
the hysteresis comparison module comprises a first-stage comparison unit, a second-stage comparison unit, two blocking capacitors and a logic unit,
the negative input end of the first-stage comparison unit is grounded, the first positive input end of the first-stage comparison unit is connected with the output signal of the input filter module or grounded under the control of the logic unit, the second positive input end of the first-stage comparison unit is connected with the first hysteresis comparison voltage, the second hysteresis comparison voltage or grounded under the control of the logic unit, the negative output end of the first-stage comparison unit is connected with the lower plate of the first DC blocking capacitor, and the positive output end of the first-stage comparison unit is connected with the lower plate of the second DC blocking capacitor;
a first input end of the second-stage comparison unit is connected with an upper polar plate of a first blocking capacitor or grounded under the control of the logic unit, a second input end of the second-stage comparison unit is connected with an upper polar plate of a second blocking capacitor or grounded under the control of the logic unit, and an output end of the second-stage comparison unit outputs a comparator output signal;
the logic unit comprises latch control and clock control, when a clock signal is in a first state, the logic unit is in an offset elimination stage, the logic unit controls a first positive input end and a second positive input end of the first-stage comparison unit and a first input end and a second input end of the second-stage comparison unit to be grounded, meanwhile, the logic unit latches an output signal of the comparator, and offset voltage is stored on the two blocking capacitors in the offset elimination stage;
when the clock signal is in a second state, the clock signal is in a comparison stage, the logic unit controls a first positive input end of the first-stage comparison unit to be connected with an output signal of the input filter module, and controls a first input end and a second input end of the second-stage comparison unit to be respectively connected with upper pole plates of a first blocking capacitor and a second blocking capacitor, meanwhile, the logic unit controls a second positive input end of the first-stage comparison unit to be connected with a first hysteresis comparison voltage or a second hysteresis comparison voltage according to an output signal of the comparator, the first hysteresis comparison voltage and the second hysteresis comparison voltage are opposite in phase, the first hysteresis comparison voltage is positive, and the second hysteresis comparison voltage is negative; in the comparison stage, the input offset voltage is offset from the offset information stored in the two blocking capacitors, when the comparator input signal is higher than the first hysteresis comparison voltage, the comparator output signal is inverted from the second state to the first state, when the comparator input signal is lower than the second hysteresis comparison voltage, the comparator output signal is inverted from the first state to the second state, and when the comparator input signal is between the second hysteresis comparison voltage and the first hysteresis comparison voltage, the state of the comparator output signal is kept unchanged.
Specifically, the input filtering module comprises a high-pass filtering capacitor, a high-pass filtering resistor, a low-pass filtering capacitor and a low-pass filtering resistor, wherein one end of the high-pass filtering capacitor is connected with the input signal of the comparator, and the other end of the high-pass filtering capacitor is connected with one end of the low-pass filtering resistor and is grounded after passing through the high-pass filtering resistor; the other end of the low-pass filter resistor is used as the output end of the input filter module and is grounded after passing through the low-pass filter capacitor.
Specifically, in the comparison stage, when the output signal of the comparator is in the first state, the logic unit controls the second positive input terminal of the first-stage comparison unit to be connected to the first hysteresis comparison voltage; when the output signal of the comparator is in a second state, the logic unit controls a second positive input end of the first-stage comparison unit to be connected with the second hysteresis comparison voltage.
Specifically, the first-stage comparison unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first current source, a second current source, a first resistor, a second resistor, a fifth switch, a sixth switch, a seventh switch and an eighth switch,
the grid electrode of the first PMOS tube is used as a first positive input end of the first-stage comparison unit, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a first current source, and the drain electrode of the first PMOS tube is used as a positive output end of the first-stage comparison unit and is grounded through a first resistor;
the grid electrode of the second PMOS tube is connected with the grid electrode of the third PMOS tube and is used as the negative input end of the first-stage comparison unit, and the drain electrode of the second PMOS tube is used as the negative output end of the first-stage comparison unit and is grounded after passing through the second resistor;
a grid electrode of the fourth PMOS tube is used as a second positive input end of the first-stage comparison unit, a source electrode of the fourth PMOS tube is connected with a source electrode of the third PMOS tube and is connected with a second current source, and a drain electrode of the fourth PMOS tube is connected with a negative output end of the first-stage comparison unit after passing through a sixth switch and is connected with a positive output end of the first-stage comparison unit after passing through an eighth switch respectively;
the drain electrode of the third PMOS tube is respectively connected with the negative output end of the first-stage comparison unit after passing through a seventh switch and connected with the positive output end of the first-stage comparison unit after passing through a fifth switch;
the second-stage comparison unit comprises a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third current source and a fourth current source,
a grid electrode of the fifth PMOS tube is used as a positive input end of the second-stage comparison unit and is connected with a positive output end of the first-stage comparison unit after passing through the first blocking capacitor, a source electrode of the fifth PMOS tube is connected with a source electrode of the sixth PMOS tube and is connected with a third current source, and a drain electrode of the fifth PMOS tube is connected with a grid electrode and a drain electrode of the first NMOS tube and a grid electrode of the second NMOS tube;
a grid electrode of the sixth PMOS tube is used as a negative input end of the second-stage comparison unit and is connected with a negative output end of the first-stage comparison unit after passing through the second blocking capacitor, and a drain electrode of the sixth PMOS tube is connected with a drain electrode of the second NMOS tube and a grid electrode of the third NMOS tube;
the drain electrode of the third NMOS tube is connected with a fourth current source and serves as the output end of the second-stage comparison unit, and the source electrode of the third NMOS tube is connected with the source electrodes of the first NMOS tube and the second NMOS tube and is grounded.
Specifically, the logic unit comprises a first switch, a second switch, a third switch, a fourth switch, a ninth switch and a tenth switch,
one end of the first switch is grounded, and the other end of the first switch is connected with the first positive input end of the first-stage comparison unit;
one end of the second switch is connected with the input filtering module, and the other end of the second switch is connected with the first positive input end of the first-stage comparison unit;
one end of the third switch is grounded, and the other end of the third switch is connected with the second positive input end of the first-stage comparison unit;
one end of the fourth switch is connected with the first hysteresis comparison voltage, and the other end of the fourth switch is connected with the second positive input end of the first-stage comparison unit;
one end of the ninth switch is grounded, and the other end of the ninth switch is connected with the first input end of the second-stage comparison unit;
one end of the tenth switch is grounded, and the other end of the tenth switch is connected with the second input end of the second-stage comparison unit;
when the clock signal is in a first state, the first switch, the ninth switch and the tenth switch are closed, and the second switch is opened; when the clock signal is in a second state, the first switch, the ninth switch and the tenth switch are opened, and the second switch is closed.
Specifically, the first state of the output signal of the comparator and the clock signal is a high level, and the second state is a low level;
the rising edge of the latch clock is aligned with the rising edge of the clock signal, and the falling edge of the latch clock is later than the falling edge of the clock signal; when the latch clock is at a high level, the output signal of the comparator is latched, when the latch clock is at a low level, the output signal of the comparator is directly used for controlling a second positive input end of the first-stage comparison unit to be connected with the first hysteresis comparison voltage or the second hysteresis comparison voltage, and if the output signal of the comparator is at the high level, the seventh switch and the eighth switch are turned off, and the fifth switch and the sixth switch are turned on; and if the output signal of the comparator is low level, the seventh switch and the eighth switch are switched on, and the fifth switch and the sixth switch are switched off.
The invention has the beneficial effects that: the comparator provided by the invention filters a direct current component and a high-frequency overshoot component in the input signal VIN of the comparator by using the input filtering module, so that the current waveform with larger overshoot in the input signal VIN is corrected, and the input overshoot is reduced; meanwhile, the hysteresis comparison module is used for completing comparison, and in combination with logic control, the input offset information is stored on the blocking capacitor in the offset elimination stage, so that the input offset of the comparator and the input offset information stored on the blocking capacitor are mutually offset in the comparison stage, the offset (offset) of the comparator is eliminated, the demodulation error rate of the circuit is reduced, and the demodulation decoding rate of the wireless charging current is improved.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a block diagram of a conventional hysteretic comparator with an input high-pass filter.
Fig. 2 is a truth table of a data selector MUX in a conventional hysteresis comparator.
Fig. 3 is a waveform diagram of a conventional hysteresis comparator under a condition of correct demodulation.
Fig. 4 is a waveform diagram of a conventional hysteresis comparator, which is caused by too large ringing of an input signal, and it can be seen that the waveform has large ringing and the demodulation error rate is increased.
Fig. 5 is a waveform diagram of demodulation failure of the conventional hysteresis comparator due to too large offset of the comparator, and it can be seen that the offset voltage ratio of the comparator is large, and the demodulation error rate is increased.
Fig. 6 is a block diagram of a high-precision comparator suitable for current demodulation in wireless charging according to the present invention.
Fig. 7 is a timing diagram of a high-precision comparator suitable for current demodulation in wireless charging according to the present invention.
Fig. 8 is a block diagram of a high-precision comparator suitable for current demodulation in wireless charging in an offset cancellation state according to the present invention.
Fig. 9 is a structural block diagram of a high-precision comparator suitable for current demodulation in wireless charging in a comparison state according to the present invention.
Fig. 10 is a waveform diagram of the comparator input signal VIN after passing through the input filter module.
Fig. 11 is a specific circuit diagram of a high-precision comparator suitable for current demodulation in wireless charging according to an embodiment of the present invention.
Fig. 12 is a specific circuit diagram of the demodulation comparator in the offset canceling state in the embodiment.
Fig. 13 is a specific circuit diagram of the demodulation comparator in the comparison state in the embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a high-precision comparator which can be suitable for current demodulation in wireless charging. As shown in fig. 6, the comparator provided by the present invention includes an input filter module and a hysteresis comparison module, wherein the input filter module is configured to filter a dc component and a high frequency overshoot component in an input signal VIN of the comparator and then output the filtered dc component and the filtered high frequency overshoot component, so that a current waveform with a large overshoot in the input signal VIN is corrected, and the overshoot is reduced; the hysteresis comparison module is used for completing comparison action and eliminating offset of the comparator, thereby reducing demodulation error rate of the circuit.
FIG. 6 shows a circuit diagram of an implementation of the input filter module, which includes a high-pass filter capacitor CHFHigh-pass filter resistor RHFLow pass filter capacitor CLFAnd a low-pass filter resistor RLFHigh-pass filter capacitor CHFOne end is connected with the input signal VIN of the comparator, and the other end is connected with the low-pass filter resistor RLFAnd through a high-pass filter resistor RHFThen grounding; low-pass filter resistor RLFThe other end of the filter is used as an input filter moduleThrough a low-pass filter capacitor CLFAnd then grounded.
The input filter module in the embodiment utilizes a high-pass filter capacitor CHFAnd a high-pass filter resistor RHFForming a high-pass filter using a low-pass filter capacitor CLFAnd a low-pass filter resistor RLFConstituting a low pass filter. The main function of the high-pass filter is to block, i.e. mask, the dc component of the signal. The low pass filtering filters out the high frequency overshoot component of the signal, leaving the low frequency component. The waveform through the low pass filter is shown in fig. 10, and it can be seen that ringing in the input signal is suppressed, but with a concomitant reduction in amplitude.
As shown in fig. 6, the hysteresis comparison module includes a first-stage comparison unit, a second-stage comparison unit, and two blocking capacitors CAZAnd the negative input end of the first-stage comparison unit is grounded, the first positive input end of the first-stage comparison unit is connected with the output signal of the input filter module or grounded under the control of the logic unit, and the second positive input end of the first-stage comparison unit is connected with the first hysteresis comparison voltage + V under the control of the logic unitHYSA second hysteresis comparison voltage-VHYSOr ground, first hysteresis comparison voltage + VHYSAnd a second hysteresis comparison voltage-VHYSAre in opposite phase with each other, and the first hysteresis comparison voltage + VHYSIs positive, the second hysteresis comparison voltage-VHYSNegative, VTR in FIGS. 3-5 is the first hysteresis comparison voltage + VHYSVTF is the second hysteresis comparison voltage-VHYS(ii) a The negative output end of the first-stage comparison unit is connected with the lower pole plate of the first blocking capacitor, and the positive output end of the first-stage comparison unit is connected with the lower pole plate of the second blocking capacitor.
The first input end of the second-stage comparison unit is connected with the upper polar plate of the first blocking capacitor or grounded under the control of the logic unit, the second input end of the second-stage comparison unit is connected with the upper polar plate of the second blocking capacitor or grounded under the control of the logic unit, and the output end of the second-stage comparison unit outputs a comparator output signal CMP _ OUT. As shown in fig. 6, in some embodiments, the first input terminal of the second stage comparison unit is a positive input terminal, and the second input terminal of the second stage comparison unit is a negative input terminal; in other embodiments, as shown in fig. 11, the first input terminal of the second-stage comparing unit may also be a negative input terminal, and the second input terminal of the second-stage comparing unit may be a positive input terminal; the comparator output signals CMP _ OUT generated by the two embodiments have opposite polarities and can be selected according to practical application conditions.
The logic cells include Latch control implemented by latches (Latch) and clocking implemented by a plurality of data selectors under control of a clock signal CLK.
As shown in fig. 8, when the clock signal CLK is in the first state, it is in the offset cancellation stage, and the logic unit controls the first and second positive input terminals of the first-stage comparing unit and the first and second input terminals of the second-stage comparing unit to be grounded, that is, the inputs of the first-stage comparing unit and the second-stage comparing unit are all connected to 0 level. Meanwhile, the logic unit latches the comparator output signal CMP _ OUT through a Latch (Latch), and saves the last state of the comparator output signal CMP _ OUT. In the offset elimination stage, an offset voltage V is inputOS,inAfter passing through the first-stage comparison unit, the offset information is stored in two DC blocking capacitors CAZThe above.
As shown in fig. 9, when the clock signal CLK is in the second state, which is a comparison phase, the first state and the first state of the clock signal CLK are inverted, and in some embodiments, the first state of the clock signal CLK may be set to a high level and the second state may be set to a low level. In the comparison stage, the logic unit controls a first positive input end of the first-stage comparison unit to be connected with an output signal of the input filter module, and controls a first input end and a second input end of the second-stage comparison unit to be respectively connected with upper pole plates of a first blocking capacitor and a second blocking capacitor; meanwhile, the logic unit controls the second positive input end of the first-stage comparison unit to be connected with the first hysteresis comparison voltage + V according to the output signal CMP _ OUT of the comparatorHYSOr a second hysteresis comparison voltage-VHYS. In the comparison stage, the input offset voltage is offset with the offset information stored in the two blocking capacitors, so that the equivalent input offset voltage is 0V. Input signal and delayHysteresis voltage +/-VHYSComparing, when the comparator input signal VIN is higher than the first hysteresis comparison voltage + VHYSWhen the comparator output signal CMP _ OUT is inverted from the second state to the first state, the comparator input signal VIN is lower than the second hysteresis comparison voltage-VHYSWhen the comparator input signal VIN is at the second hysteresis comparison voltage-V, the comparator output signal CMP _ OUT is inverted from the first state to the second stateHYSAnd a first hysteresis comparison voltage + VHYSIn between, the comparator output signal CMP _ OUT remains unchanged in state.
In this embodiment, the first state of the clock signal CLK is a high level, and the second state is a low level; meanwhile, the first state of the comparator output signal CMP _ OUT is high, and the second state is low. As shown in fig. 7, when the clock signal CLK is at a high level, the inverted signal CLKZ of the clock signal CLK is at a low level, so that the rising edge of the LATCH clock CLK _ LATCH is aligned with the rising edge of the clock signal CLK, and the falling edge of the LATCH clock CLK _ LATCH is later than the falling edge of the clock signal CLK, for example, the falling edge of the LATCH clock CLK _ LATCH is delayed by 1us compared with the falling edge of the clock signal CLK. The LATCH clock CLK _ LATCH is used for controlling the LATCH (LATCH), the LATCH (LATCH) latches the comparator output signal COMP _ OUT when the LATCH clock CLK _ LATCH is at a high level, and the comparator output signal COMP _ OUT is directly connected with the first hysteresis comparison voltage + V through the second positive input end for controlling the first-stage comparison unit when the LATCH clock CLK _ LATCH is at a low levelHYSOr a second hysteresis comparison voltage-VHYS(ii) a Specifically, in conjunction with the truth table shown in fig. 2, during the comparison phase, the Latch (Latch) is turned through, and when the comparator output signal COMP _ OUT is high, the logic unit controls the second positive input terminal of the first stage comparison unit to connect to the first hysteretic comparison voltage + VHYS(ii) a When the comparator output signal COMP _ OUT is low, the logic unit controls the second positive input end of the first-stage comparison unit to be connected with a second hysteresis comparison voltage-VHYS。
The following description is made in conjunction with a specific structure of the hysteresis comparison module, and a specific implementation circuit diagram of the hysteresis comparison module is shown in fig. 11, where the first-stage comparison unit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first current source IB1, a second current source IB2, a first resistor R1, a second resistor R2, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8, a gate of the first PMOS transistor MP1 serves as a first positive input terminal of the first-stage comparison unit, a source of the first PMOS transistor MP1 is connected to a source of the second PMOS transistor MP2 and to the first current source IB1, and a drain of the first-stage comparison unit serves as a positive output terminal and is grounded through the first resistor R1; the grid electrode of the second PMOS tube MP2 is connected with the grid electrode of the third PMOS tube MP3 and is used as the negative input end of the first-stage comparison unit, and the drain electrode of the second PMOS tube MP2 is used as the negative output end of the first-stage comparison unit and is grounded after passing through a second resistor R2; the gate of the fourth PMOS transistor MP4 is used as the second positive input terminal of the first-stage comparing unit, the source thereof is connected to the source of the third PMOS transistor MP3 and to the second current source IB2, and the drain thereof is connected to the negative output terminal of the first-stage comparing unit through the sixth switch S6 and to the positive output terminal of the first-stage comparing unit through the eighth switch S8, respectively; the drain of the third PMOS transistor MP3 is connected to the negative output terminal of the first stage comparing unit through the seventh switch S7 and to the positive output terminal of the first stage comparing unit through the fifth switch S5, respectively.
In the first-stage comparison unit, the first PMOS transistor MP1, the second PMOS transistor MP2, the tail current source IB1, the first resistor R1, and the second resistor R2 are a first group of inputs, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the tail current source IB2 are a second group of input pair transistors, and the polarity of the current of the second group of inputs can be changed through the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8, so that the hysteresis polarity is changed. The first-stage comparison unit and the second-stage comparison unit are connected through two blocking capacitors C1 and C2, and the two blocking capacitors C1 and C2 in FIG. 11 correspond to the two blocking capacitors C in FIG. 6AZ。
As shown in fig. 11, the second-stage comparison unit includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a third current source IB3, and a fourth current source IB4, a gate of the fifth PMOS transistor MP5 is used as a forward input terminal of the second-stage comparison unit and is connected to a forward output terminal of the first-stage comparison unit through a first dc blocking capacitor C1, a source of the fifth PMOS transistor MP5 is connected to a source of the sixth PMOS transistor MP6 and to the third current source IB3, and a drain of the sixth PMOS transistor MP1 is connected to a gate and a drain of the first NMOS transistor MN1 and a gate of the second NMOS transistor MN 2; the grid electrode of the sixth PMOS tube MP6 is used as the negative input end of the second-stage comparison unit and is connected with the negative output end of the first-stage comparison unit after passing through the second blocking capacitor C2, and the drain electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the second NMOS tube MN2 and the grid electrode of the third NMOS tube; the drain of the third NMOS transistor MN3 is connected to the fourth current source IB4 and serves as the output terminal of the second stage comparison unit, and the source thereof is connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 and grounded.
The logic unit comprises a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a ninth switch S9 and a tenth switch S10, one end of the first switch S1 is grounded, and the other end of the first switch S1 is connected with the first positive input end of the first-stage comparison unit; one end of the second switch S2 is connected with the input filtering module, and the other end is connected with the first positive input end of the first-stage comparison unit; one end of the third switch S3 is grounded, and the other end is connected to the second positive input end of the first stage comparison unit; one end of the fourth switch S4 is connected to the first hysteresis comparison voltage, and the other end is connected to the second positive input end of the first stage comparison unit; one end of the ninth switch S9 is grounded, and the other end is connected to the first input end of the second-stage comparing unit; one end of the tenth switch S10 is grounded, and the other end is connected to the second input terminal of the second stage comparing unit. When the clock signal CLK is in the first state, the first switch S1, the ninth switch S9, and the tenth switch S10 are closed, the second switch S2 is opened, and the inputs of the first-stage comparison unit and the second-stage comparison unit are grounded; when the clock signal CLK is in the second state, the first switch S1, the ninth switch S9, and the tenth switch S10 are opened, the second switch S2 is closed, the first positive input terminal of the first-stage comparison unit is connected to the output signal of the input filter module, the first input terminal and the second input terminal of the second-stage comparison unit are connected to the upper plates of the two dc blocking capacitors C1 and C2, and the second positive input terminal of the first-stage comparison unit is connected to the first hysteresis comparison voltage + VHYSOr a second hysteresis comparison voltage-VHYSIf the comparator output signal is in the first state (high in this embodiment), the seventh switch S7 and the eighth switchThe switch S8 is opened, the fifth switch S5 and the sixth switch S6 are closed, and the input signal is compared with the first hysteretic comparison voltage + VHYSIn comparison, if the comparator output signal is in the second state (low in this embodiment), the seventh switch S7 and the eighth switch S8 are closed, the fifth switch S5 and the sixth switch S6 are opened, and the input signal is compared with the second hysteresis comparison voltage-VHYSAnd (6) comparing.
The working process of the embodiment is as follows:
the first step is an offset canceling state, as shown in fig. 12, when the clock signal CLK is high, the first PMOS transistor MP1 of the first stage comparing unit is grounded to AVSS through the first switch S1, the fourth PMOS transistor MP4 is grounded to AVSS through the third switch S3, and the input of the second stage comparing unit is grounded to AVSS through the ninth switch S9 and the tenth switch S10. The logic unit latches the last state of the comparator output signal ON _ RAW by using a Latch (Latch), and in the state, the offset voltage V is inputOS,inAfter passing through the first stage amplification unit, the offset information is stored on two DC blocking capacitors C1 and C2
The second step is a comparison state, as shown in fig. 13, when CLKZ (the inverted signal of the clock signal CLK) is high, the first PMOS transistor MP1 of the first stage comparison unit is connected to the low pass filter output by the input filter module through the second switch S2, the fourth PMOS transistor MP4 is connected to the first hysteresis voltage VHYS through the fourth switch S4, and two input terminals of the second stage comparison unit are respectively connected to the upper stage boards of the two blocking capacitors C1 and C2. In the comparison phase, the Latch (Latch) of the logic block is in the through mode, outputting the comparator output signal ON _ RAW through, the output of which is ON _ F = ON _ RAW. The offset information stored in the two dc blocking capacitors C1 and C2 in the comparison stage will cancel the input offset voltage, and the equivalent input offset voltage is 0V. Input signal and hysteresis voltage +/-VHYSComparing, when the input signal is greater than + VHYSWhen so, the comparator output signal ON _ RAW is high; when the input signal is less than-VHYSThe comparator output signal ON _ RAW is low.
In summary, it can be seen that the comparator provided by the present invention reduces overshoot in the input signal through the low pass filter of the input filter module, reduces the offset voltage of the comparator through the auto-zero hysteresis comparator module, and the combination of the input filter module and the hysteresis comparator module can effectively improve the decoding rate of the wireless charging.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (6)

1. A high-precision comparator suitable for current demodulation in wireless charging is characterized by comprising an input filtering module and a hysteresis comparison module,
the input filtering module is used for filtering a direct current component and a high-frequency overshoot component in the input signal of the comparator and outputting the filtered direct current component and the filtered high-frequency overshoot component;
the hysteresis comparison module comprises a first-stage comparison unit, a second-stage comparison unit, two blocking capacitors and a logic unit,
the negative input end of the first-stage comparison unit is grounded, the first positive input end of the first-stage comparison unit is connected with the output signal of the input filter module or grounded under the control of the logic unit, the second positive input end of the first-stage comparison unit is connected with the first hysteresis comparison voltage, the second hysteresis comparison voltage or grounded under the control of the logic unit, the negative output end of the first-stage comparison unit is connected with the lower plate of the first DC blocking capacitor, and the positive output end of the first-stage comparison unit is connected with the lower plate of the second DC blocking capacitor;
a first input end of the second-stage comparison unit is connected with an upper polar plate of a first blocking capacitor or grounded under the control of the logic unit, a second input end of the second-stage comparison unit is connected with an upper polar plate of a second blocking capacitor or grounded under the control of the logic unit, and an output end of the second-stage comparison unit outputs a comparator output signal;
the logic unit comprises latch control and clock control, when a clock signal is in a first state, the logic unit is in an offset elimination stage, the logic unit controls a first positive input end and a second positive input end of the first-stage comparison unit and a first input end and a second input end of the second-stage comparison unit to be grounded, meanwhile, the logic unit latches an output signal of the comparator, and offset voltage is stored on the two blocking capacitors in the offset elimination stage;
when the clock signal is in a second state, the clock signal is in a comparison stage, the logic unit controls a first positive input end of the first-stage comparison unit to be connected with an output signal of the input filter module, and controls a first input end and a second input end of the second-stage comparison unit to be respectively connected with upper pole plates of a first blocking capacitor and a second blocking capacitor, meanwhile, the logic unit controls a second positive input end of the first-stage comparison unit to be connected with a first hysteresis comparison voltage or a second hysteresis comparison voltage according to an output signal of the comparator, the first hysteresis comparison voltage and the second hysteresis comparison voltage are opposite in phase, the first hysteresis comparison voltage is positive, and the second hysteresis comparison voltage is negative; in the comparison stage, the input offset voltage is offset from the offset information stored in the two blocking capacitors, when the comparator input signal is higher than the first hysteresis comparison voltage, the comparator output signal is inverted from the second state to the first state, when the comparator input signal is lower than the second hysteresis comparison voltage, the comparator output signal is inverted from the first state to the second state, and when the comparator input signal is between the second hysteresis comparison voltage and the first hysteresis comparison voltage, the state of the comparator output signal is kept unchanged.
2. The high-precision comparator suitable for current demodulation in wireless charging according to claim 1, wherein the input filtering module comprises a high-pass filtering capacitor, a high-pass filtering resistor, a low-pass filtering capacitor and a low-pass filtering resistor, one end of the high-pass filtering capacitor is connected with the input signal of the comparator, and the other end of the high-pass filtering capacitor is connected with one end of the low-pass filtering resistor and is grounded after passing through the high-pass filtering resistor; the other end of the low-pass filter resistor is used as the output end of the input filter module and is grounded after passing through the low-pass filter capacitor.
3. The high-precision comparator suitable for current demodulation in wireless charging according to claim 1 or 2, wherein in the comparison stage, when the output signal of the comparator is in the first state, the logic unit controls the second positive input terminal of the first stage comparison unit to connect to the first hysteresis comparison voltage; when the output signal of the comparator is in a second state, the logic unit controls a second positive input end of the first-stage comparison unit to be connected with the second hysteresis comparison voltage.
4. The high-precision comparator suitable for current demodulation in wireless charging according to claim 3, wherein the first-stage comparison unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current source, a second current source, a first resistor, a second resistor, a fifth switch, a sixth switch, a seventh switch and an eighth switch,
the grid electrode of the first PMOS tube is used as a first positive input end of the first-stage comparison unit, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a first current source, and the drain electrode of the first PMOS tube is used as a positive output end of the first-stage comparison unit and is grounded through a first resistor;
the grid electrode of the second PMOS tube is connected with the grid electrode of the third PMOS tube and is used as the negative input end of the first-stage comparison unit, and the drain electrode of the second PMOS tube is used as the negative output end of the first-stage comparison unit and is grounded after passing through the second resistor;
a grid electrode of the fourth PMOS tube is used as a second positive input end of the first-stage comparison unit, a source electrode of the fourth PMOS tube is connected with a source electrode of the third PMOS tube and is connected with a second current source, and a drain electrode of the fourth PMOS tube is connected with a negative output end of the first-stage comparison unit after passing through a sixth switch and is connected with a positive output end of the first-stage comparison unit after passing through an eighth switch respectively;
the drain electrode of the third PMOS tube is respectively connected with the negative output end of the first-stage comparison unit after passing through a seventh switch and connected with the positive output end of the first-stage comparison unit after passing through a fifth switch;
the second-stage comparison unit comprises a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third current source and a fourth current source,
a grid electrode of the fifth PMOS tube is used as a positive input end of the second-stage comparison unit and is connected with a positive output end of the first-stage comparison unit after passing through the first blocking capacitor, a source electrode of the fifth PMOS tube is connected with a source electrode of the sixth PMOS tube and is connected with a third current source, and a drain electrode of the fifth PMOS tube is connected with a grid electrode and a drain electrode of the first NMOS tube and a grid electrode of the second NMOS tube;
a grid electrode of the sixth PMOS tube is used as a negative input end of the second-stage comparison unit and is connected with a negative output end of the first-stage comparison unit after passing through the second blocking capacitor, and a drain electrode of the sixth PMOS tube is connected with a drain electrode of the second NMOS tube and a grid electrode of the third NMOS tube;
the drain electrode of the third NMOS tube is connected with a fourth current source and serves as the output end of the second-stage comparison unit, and the source electrode of the third NMOS tube is connected with the source electrodes of the first NMOS tube and the second NMOS tube and is grounded.
5. The high-precision comparator suitable for current demodulation in wireless charging according to claim 1 or 4, wherein the logic unit comprises a first switch, a second switch, a third switch, a fourth switch, a ninth switch and a tenth switch,
one end of the first switch is grounded, and the other end of the first switch is connected with the first positive input end of the first-stage comparison unit;
one end of the second switch is connected with the input filtering module, and the other end of the second switch is connected with the first positive input end of the first-stage comparison unit;
one end of the third switch is grounded, and the other end of the third switch is connected with the second positive input end of the first-stage comparison unit;
one end of the fourth switch is connected with the first hysteresis comparison voltage, and the other end of the fourth switch is connected with the second positive input end of the first-stage comparison unit;
one end of the ninth switch is grounded, and the other end of the ninth switch is connected with the first input end of the second-stage comparison unit;
one end of the tenth switch is grounded, and the other end of the tenth switch is connected with the second input end of the second-stage comparison unit;
when the clock signal is in a first state, the first switch, the ninth switch and the tenth switch are closed, and the second switch is opened; when the clock signal is in a second state, the first switch, the ninth switch and the tenth switch are opened, and the second switch is closed.
6. The comparator suitable for current demodulation in wireless charging according to claim 5, wherein the comparator output signal and the clock signal are made to be in a high level in a first state and in a low level in a second state;
the rising edge of the latch clock is aligned with the rising edge of the clock signal, and the falling edge of the latch clock is later than the falling edge of the clock signal; when the latch clock is at a high level, the output signal of the comparator is latched, when the latch clock is at a low level, the output signal of the comparator is directly used for controlling a second positive input end of the first-stage comparison unit to be connected with the first hysteresis comparison voltage or the second hysteresis comparison voltage, and if the output signal of the comparator is at the high level, the seventh switch and the eighth switch are turned off, and the fifth switch and the sixth switch are turned on; and if the output signal of the comparator is low level, the seventh switch and the eighth switch are switched on, and the fifth switch and the sixth switch are switched off.
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