CN117097596A - Adaptive analog control circuit for high-speed serdes equalization system - Google Patents
Adaptive analog control circuit for high-speed serdes equalization system Download PDFInfo
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Abstract
The application provides a self-adaptive analog control circuit for a high-speed serdes equalizing system, which comprises an error amplifying circuit, a sampling signal generating circuit and a sampling holding circuit, wherein the error amplifying circuit is used for amplifying a sampling signal; the sampling signal generating circuit realizes that the circuit sampling signal only appears when the pulse width of the input signal of the high-speed serdes equalizing circuit is longest through the negative feedback network, so that the self-adaptive analog control circuit only collects the rising and falling edge information on the signal with the longest pulse width to realize the self-adaptive control function, the requirement of the equalizing system on the response speed of the operational amplifier is reduced, the highest speed which can be supported by the circuit is improved, and meanwhile, the circuit power consumption can be reduced.
Description
Technical Field
The application relates to the technical field of integrated circuit design, in particular to a self-adaptive analog control circuit for a high-speed serdes equalizing system.
Background
In high speed serdes signal transmission, a serdes equalization circuit is typically required to modulate the serdes signal. With the continuous increase of the transmission rate, the requirement on the response speed of the serdes equalizing circuit is higher and higher. The response speed of the operational amplifier circuit in the conventional design determines the response speed of the serdes equalizing circuit, so that the highest transmission rate of the serdes signal is determined, which limits the further improvement of the rate of the serdes circuit.
Disclosure of Invention
The application provides a self-adaptive analog control circuit, which aims to overcome the limitation of the response speed of an operational amplifier on the transmission speed of a serdes signal so as to improve the highest speed which can be supported by the circuit and reduce the power consumption of the circuit.
In a first aspect, there is provided an adaptive analog control circuit comprising:
the error amplifying circuit is used for receiving the external equalizing circuit signal and generating a standard signal according to the external equalizing circuit signal, and generating an error signal by comparing the rising edge speed with the standard signal;
the sampling signal generation circuit is used for receiving the external equalization circuit signal, generating no sampling signal when the pulse width of the external equalization circuit signal is smaller than a preset pulse width, and generating a sampling signal when the pulse width of the external equalization circuit signal is larger than the preset pulse width;
and a sample-and-hold circuit for receiving the error signal from the error amplifying circuit and performing sample-and-hold based on the error signal when the sample signal is received from the sample signal generating circuit.
With reference to the first aspect, in certain implementations of the first aspect, the sampling signal generating circuit includes a first operational amplifier, a common mode adjustment circuit, a first capacitor, a second capacitor, a first nand gate, a second nand gate, and an inverter;
the two differential input ends of the first operational amplifier are respectively connected with the two output ends of the external equalizing circuit, and the two differential output ends of the first operational amplifier are respectively connected with the two differential input ends of the common mode adjusting circuit;
the positive end of the differential output end of the common mode adjusting circuit is connected with the positive end of the first capacitor and the positive end of the first NAND gate, the negative end of the first capacitor is grounded, the negative end of the differential output end of the common mode adjusting circuit is connected with the positive end of the second capacitor and the negative end of the first NAND gate, and the negative end of the second capacitor is grounded;
the output end of the first NAND gate is connected with the input end of the second NAND gate, the other input end of the second NAND gate is connected with an external enabling signal ENN, the output end of the second NAND gate is connected with the input end of the phase inverter, and is connected with the first input end of the sample hold circuit in parallel, the output end of the phase inverter is connected with the second input end of the sample hold circuit, the sampling signal is generated when the level of the first input end is lower than the level of the second input end, and the sampling signal is not generated when the level of the second input end is lower than the level of the first input end;
the common mode adjusting circuit is used for switching the charge and discharge states of the first capacitor and the second capacitor according to the differential input of the external equalizing circuit, so that one of the first capacitor and the second capacitor receives charge from the common mode adjusting circuit, the other is discharged to the common mode adjusting circuit, and the common mode adjusting circuit is used for enabling the charge speed of the first capacitor to be faster than the discharge speed of the first capacitor and enabling the charge speed of the second capacitor to be faster than the discharge speed of the second capacitor.
With reference to the first aspect, in certain implementations of the first aspect, the common mode adjustment circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor;
the positive end of the differential output end of the first operational amplifier is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the third PMOS tube; the negative end of the differential output end of the first operational amplifier is respectively connected with the grid electrode of the second PMOS tube and the grid electrode of the fourth PMOS tube; the first PMOS tube source stage, the second PMOS tube source stage, the third PMOS tube source stage and the fourth PMOS tube source stage are respectively connected with a power supply VCC; the drain electrode of the first PMOS tube is connected with the drain electrode and the grid electrode of the first NMOS tube and the grid electrode of the fourth NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode and the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube; the first NMOS tube source stage, the second NMOS tube source stage, the third NMOS tube source stage and the fourth NMOS tube source stage are respectively grounded GND; the drain electrode of the third PMOS tube is connected with the first resistor positive end, the first capacitor positive end and the first NAND gate input end; the drain electrode of the fourth PMOS tube is connected with the positive end of the second resistor, the positive end of the second capacitor and the other input end of the first NAND gate; the negative end of the first resistor is connected with the drain electrode of the third NMOS tube; the negative end of the second resistor is connected with the drain electrode of the fourth NMOS tube.
With reference to the first aspect, in some implementations of the first aspect, the first resistor and the second resistor have resistances of 1k to 3k ohms.
In combination with the first aspect, in some implementations of the first aspect, the aspect ratios of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 are all greater than the aspect ratios of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209.
With reference to the first aspect, in some implementations of the first aspect, the aspect ratio of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 is equal to 150-250; the aspect ratio of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209 is equal to 50 to 80.
With reference to the first aspect, in certain implementations of the first aspect, the error amplifying circuit includes a second operational amplifier, a bandpass network, and a summing amplifier; the output of the external equalization circuit generates the standard waveform through the second operational amplifier, the output of the external equalization circuit and the standard waveform are respectively output to the summing amplifier through the band-pass network, and the summing amplifier is used for comparing the rising and falling edge time difference of the output of the external equalization circuit and the standard waveform and generating the error signal.
With reference to the first aspect, in certain implementations of the first aspect, the band-pass network includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor.
The input end of the second operational amplifier is respectively connected with the positive poles of the third capacitor and the fourth capacitor and is connected with the output of the external equalizing circuit; the output end of the second operational amplifier is respectively connected with the positive poles of the first capacitor and the second capacitor; the first capacitor cathode, the second capacitor cathode, the third capacitor cathode and the fourth capacitor cathode are respectively connected with a first resistance cathode, a second resistance cathode, a third resistance cathode and a fourth resistance cathode, and the first resistance cathode, the second resistance cathode, the third resistance cathode and the fourth resistance cathode are respectively connected with a fifth resistance cathode, a sixth resistance cathode, a seventh resistance cathode and an eighth resistance cathode and are respectively connected with four input ends of the summing amplifier; the positive electrode of the ninth resistor is connected with a power supply, and the negative electrode of the ninth resistor is connected with the negative electrode of the fifth resistor, the negative electrode of the sixth resistor and the positive electrode of the tenth resistor; the tenth resistance negative electrode is connected with the seventh resistance negative electrode, the eighth resistance negative electrode and the eleventh resistance positive electrode; the negative electrode of the eleventh resistor is connected with the ground; the output end of the summing amplifier is output to the sample hold circuit.
With reference to the first aspect, in certain implementation manners of the first aspect, the sample-and-hold circuit includes a fifth PMOS transistor, a fifth NMOS transistor, a resistor, and a capacitor. The grid electrode of the fifth PMOS tube is connected with the output of the sampling signal generating circuit; the source stage of the fifth PMOS tube is connected with the source stage of the fifth NMOS tube and the output of the error amplifying circuit; the drain of the fifth PMOS tube is connected with the drain of the fifth NMOS tube and the positive end of the resistor; the grid electrode of the fifth NMOS tube is connected with the output of the sampling signal generating circuit; the source stage of the fifth NMOS tube is connected with the output of the error amplifying circuit; the drain of the fifth NMOS tube is connected with the positive end of the resistor; the negative end of the resistor is connected with the positive end of the capacitor and the output end; the negative end of the capacitor is grounded.
In a second aspect, a serdes equalization system is provided, the serdes equalization system comprising an adaptive analog control circuit as described in any implementation of the first aspect above.
Compared with the prior art, the scheme provided by the application at least comprises the following beneficial technical effects:
the application provides a self-adaptive analog control circuit for a high-speed serdes equalizing system, the working speed is 6.25Gbps, and circuit sampling signals only appear when the pulse width of an input signal of the high-speed serdes equalizing circuit is longest, so that the self-adaptive analog control circuit only collects rising and falling edge information on the signal with the longest pulse width to realize the self-adaptive control function, the response speed requirement of the equalizing system to an operational amplifier is reduced, the highest speed which can be supported by the circuit is improved, and meanwhile, the circuit power consumption is reduced.
Drawings
Fig. 1 is a block diagram of an adaptive analog control circuit according to the present application.
Fig. 2 is a block diagram of an error amplifying circuit according to the present application.
Fig. 3 is a block diagram of a sampling signal generating circuit according to the present application.
Fig. 4 is a block diagram of a sample-and-hold circuit according to the present application.
Detailed Description
The application is described in further detail below with reference to the drawings and the specific embodiments.
Fig. 1 shows a schematic block diagram of an adaptive analog control circuit according to an embodiment of the present application. The adaptive analog control circuit can be used for a high-speed serdes equalization circuit. The operating frequency of the circuit may be, for example, 6.25Gbps.
The adaptive analog control circuit may include an error amplification circuit, a sampling signal generation circuit, and a sample-and-hold circuit. The error amplifying circuit can be used for receiving the signal of the external equalizing circuit, comparing the signal with the rising and falling edge speed of the standard signal generated by internal amplification, generating an error signal and outputting the error signal to the sample hold circuit. The sampling signal generation circuit may be configured to receive the external equalization circuit signal, generate no sampling signal when the pulse is narrow (for example, 1.25Ghz to 3.125Ghz and above), generate a sampling signal when the pulse is wide (for example, 1.25Ghz and below), and output the sampling signal to the sample hold circuit. The sample hold circuit can be used for carrying out sample hold on the error signal when receiving the sampling signal from the sampling signal generating circuit, and outputting the result to the external equalization circuit, and modulating the equalization circuit to realize the self-adapting function.
Fig. 2 shows a schematic block diagram of an error amplifying circuit according to an embodiment of the present application.
The error amplifying circuit includes an operational amplifier 101, a band-pass network, and a summing amplifier 107. The bandpass network may be a resistor-capacitor frequency selective network. The band-pass network may operate at a frequency of 50Mhz to 3.5Ghz.
The external equalization circuit output generates a standard waveform through an operational amplifier 101 inside the error amplification circuit. The output of the external equalizing circuit and the standard waveform are respectively output to the summing amplifier through a resistor-capacitor frequency-selecting network. The summing amplifier 107 may be used to compare the rising and falling edge time differences of the external equalization circuit output and the standard waveform. The summing amplifier 107 may generate an error signal and output to a sample and hold circuit.
If the rising and falling edge time of the waveform output by the external equalization circuit is longer than the rising and falling edge time of the standard waveform, the error amplification circuit outputs a high-level error signal to the sample hold circuit so as to increase the high-frequency gain of the equalization circuit; if the rising and falling edge time of the waveform output by the external equalization circuit is shorter than that of the standard waveform, the error amplification circuit outputs a low-level control signal to the sample hold circuit so as to reduce the high-frequency gain of the equalization circuit.
In the embodiment shown in fig. 2, the band-pass network may include a first capacitor 102, a second capacitor 105, a third capacitor 108, a fourth capacitor 111, a first resistor 103, a second resistor 106, a third resistor 109, a fourth resistor 112, a fifth resistor 104, a sixth resistor 107, a seventh resistor 110, an eighth resistor 113, a ninth resistor 114, a tenth resistor 115, and an eleventh resistor 116.
The input end of the operational amplifier 101 is respectively connected with the anodes of the third capacitor 108 and the fourth capacitor 111 and is connected with the output of an external equalizing circuit; the output end of the operational amplifier 101 is respectively connected with the anodes of the first capacitor 102 and the second capacitor 105; the negative electrode of the first capacitor 102, the negative electrode of the second capacitor 105, the negative electrode of the third capacitor 108 and the negative electrode of the fourth capacitor 111 are respectively connected with the positive electrode of the first resistor 103, the positive electrode of the second resistor 106, the positive electrode of the third resistor 109 and the positive electrode of the fourth resistor 112, and the negative electrodes of the first resistor 103, the second resistor 106, the third resistor 109 and the fourth resistor 112 are respectively connected with the positive electrode of the fifth resistor 104, the positive electrode of the sixth resistor 107, the positive electrode of the seventh resistor 110 and the positive electrode of the eighth resistor 113 and are respectively connected with four input ends of the summing amplifier 117; the positive electrode of the ninth resistor 114 is connected with a power supply, and the negative electrode of the fifth resistor 104, the negative electrode of the sixth resistor 107 and the positive electrode of the tenth resistor 115 are connected with each other; the negative electrode of the tenth resistor 115 is connected with the negative electrodes of the seventh resistor 110, the eighth resistor 113 and the positive electrode of the eleventh resistor 116; the negative electrode of the eleventh resistor 116 is connected with the ground; the output terminal Vout3 of the adder 117 is output to the sample hold circuit.
Fig. 3 shows a schematic block diagram of a sampling signal generating circuit according to an embodiment of the present application.
The sampling signal generation circuit may include an operational amplifier 201, a common mode adjustment circuit, a first capacitor 212, a second capacitor 213, a first nand gate 214, a second nand gate 215, and an inverter 216.
The differential input ends of the operational amplifier 201 are respectively connected with the output of an external equalizing circuit; the differential output end of the operational amplifier 201 is respectively connected with the differential input end of the common mode adjusting circuit, the positive end of the differential output end of the common mode adjusting circuit is connected with the positive end of the first capacitor 212 and the positive end of the first NAND gate 214, the negative end of the first capacitor 212 is grounded, the negative end of the differential output end of the common mode adjusting circuit is connected with the positive end of the second capacitor 213 and the negative end of the first NAND gate 214, and the negative end of the second capacitor 213 is grounded.
The common mode adjustment circuit is configured to switch the charge/discharge states of the first capacitor 212 and the second capacitor 213 according to the differential input of the external equalization circuit, so that one of the first capacitor 212 and the second capacitor 213 receives charge from the common mode adjustment circuit, and the other discharges to the common mode adjustment circuit.
The common mode adjustment circuit is used for enabling the charging speed of the first capacitor 212 to be faster than the discharging speed of the first capacitor 212, and is used for enabling the charging speed of the second capacitor 213 to be faster than the discharging speed of the second capacitor 213. The output end of the first NAND gate 214 is connected with the input end of the second NAND gate 215; the other input terminal of the second nand gate 215 is connected to an external enable signal ENN (which may be at a high level); the output end Vout1 of the second NAND gate 215 is connected with the input end of the inverter 216 and outputs to the sample hold circuit; the output terminal Vout2 of the inverter 216 is output to the sample-and-hold circuit. When the ENN enable signal is low, the circuit output is fixed at a high level, and the circuit is in a standby state. When the ENN enable signal is high, the partial circuit is in an operating state.
In the case that the input signal is a narrow pulse, the positive terminal and the negative terminal of the differential output terminal of the common mode adjusting circuit are used for outputting the same type of level (for example, both the positive terminal and the negative terminal are high level), which specifically includes two cases: the positive end of the differential output end of the common mode adjusting circuit is charged to the first capacitor 212 rapidly, so that the positive end of the first capacitor 212 is at a high level, and the second capacitor 213 is discharged to the negative end of the differential output end of the common mode adjusting circuit slowly in a short time, so that the positive end of the second capacitor 213 is also at a high level; the first capacitor 212 discharges slowly to the positive end of the differential output end of the common mode adjustment circuit in a short time, so that the positive end of the first capacitor 212 is at a high level, and the negative end of the differential output end of the common mode adjustment circuit charges rapidly to the second capacitor 213, so that the positive end of the second capacitor 213 is also at a high level.
In a possible case where the input signal is narrower, since the inputs of the first nand gate 214 are both high, the output of the first nand gate 214 may be low, and the output of the second nand gate 215 may be high, so that the output of the second nand gate 215 is high at Vout1 and the output of the inverter 216 is low at Vout 2.
In the case where the input signal is a pulse with a relatively wide width, the positive terminal and the negative terminal of the differential output terminal of the common mode adjustment circuit are used for outputting different types of levels (respectively, a high level and a low level, in the present application, the high level is interpreted as a case higher than a preset level, and the low level is interpreted as a case lower than the preset level), specifically including two cases: the positive end of the differential output end of the common mode adjusting circuit is charged rapidly to the first capacitor 212, so that the positive end of the first capacitor 212 is at a high level, and the second capacitor 213 is discharged slowly for a long time to the negative end of the differential output end of the common mode adjusting circuit, so that the positive end of the second capacitor 213 is at a low level; the first capacitor 212 discharges slowly for a long time to the positive end of the differential output end of the common mode adjustment circuit, so that the positive end of the first capacitor 212 is at a low level, and the negative end of the differential output end of the common mode adjustment circuit charges rapidly to the second capacitor 213, so that the positive end of the second capacitor 213 is at a high level.
In a possible case where the input signal is a wide pulse, since the input of the first nand gate 214 is high and low, respectively, the output of the first nand gate 214 may be high, the output of the second nand gate 215 may be low, so that the output terminal Vout1 of the second nand gate 215 is low, and the output terminal Vout2 of the inverter 216 is high.
In some embodiments, the first capacitor 212 and the second capacitor 213 have a capacitance of 10 to 20fF, for example 13.5fF.
In the embodiment shown in fig. 3, the common mode adjustment circuit may include a first PMOS transistor 202, a second PMOS transistor 203, a third PMOS transistor 204, a fourth PMOS transistor 205, a first NMOS transistor 206, a second NMOS transistor 207, a third NMOS transistor 208, a fourth NMOS transistor 209, a first resistor 210, and a second resistor 211. The first resistor 210 and the second resistor 211 can be beneficial to reducing the discharge rate of the first capacitor 212 and the second capacitor 213, and also beneficial to raising the input level of the first nand gate 214 in a narrow pulse scene, namely raising the common-mode voltage output by the third PMOS transistor 204 and the fourth PMOS transistor 205.
The positive end of the differential output end of the operational amplifier 201 is respectively connected with the grid electrode of the first PMOS tube 202 and the grid electrode of the third PMOS tube 204; the negative end of the differential output end of the operational amplifier 201 is respectively connected with the grid electrode of the second PMOS tube 203 and the grid electrode of the fourth PMOS tube 205; the source stage of the first PMOS tube 202, the source stage of the second PMOS tube 203, the source stage of the third PMOS tube 204 and the source stage of the fourth PMOS tube 205 are respectively connected with a power supply VCC; the drain electrode of the first PMOS tube 202 is connected with the drain electrode and the grid electrode of the first NMOS tube 206 and the grid electrode of the fourth NMOS tube 209; the drain electrode of the second PMOS tube 203 is connected with the drain electrode and the grid electrode of the second NMOS tube 207 and the grid electrode of the third NMOS tube 208; the source stage of the first NMOS tube 206, the source stage of the second NMOS tube 207, the source stage of the third NMOS tube 208 and the source stage of the fourth NMOS tube 209 are respectively grounded to GND; the drain electrode of the third PMOS transistor 204 is connected to the positive terminal of the first resistor 210, the positive terminal of the first capacitor 212, and the input terminal of the first nand gate 214; the drain electrode of the fourth PMOS tube 205 is connected with the positive end of the second resistor 211, the positive end of the second capacitor 213 and the other input end of the first NAND gate 214; the negative end of the first resistor 210 is connected with the drain electrode of the third NMOS tube 208; the negative terminal of the second resistor 211 is connected with the drain electrode of the fourth NMOS tube 209.
When the output Vin1 of the external equalizing circuit is at a high level, the output Vin2 of the external equalizing circuit is at a low level, the gate voltage of the first PMOS transistor 202 is at a high level, the first PMOS transistor 202 is turned off, the gate voltage of the third PMOS transistor 204 is at a high level, the third PMOS transistor 204 is turned off, the gate voltage of the fourth PMOS transistor 205 is at a low level, and the fourth PMOS transistor 205 is turned on. Thus, the first capacitor 212 can be discharged through the first resistor 210 and the third NMOS transistor 208, and the first input terminal of the first nand gate 214 is high for a short time due to the slow discharge caused by the first resistor 210. The power VCC may charge the second capacitor 213 through the fourth PMOS transistor 205, and the other input terminal of the first nand gate 214 is at a high level.
When the output Vin1 of the external equalizing circuit is at a low level, the output Vin2 of the external equalizing circuit is at a high level, the gate voltage of the second PMOS transistor 203 is at a high level, the second PMOS transistor 203 is turned off, the gate voltage of the third PMOS transistor 204 is at a low level, the third PMOS transistor 204 is turned on, the gate voltage of the fourth PMOS transistor 205 is at a high level, and the fourth PMOS transistor 205 is turned off. The second capacitor 213 can be discharged through the second resistor 211 and the fourth NMOS transistor 209, and the second input terminal of the first nand gate 214 is high for a short time due to the slow discharge caused by the presence of the second resistor 211. The power VCC may charge the first capacitor 212 through the third PMOS transistor 204, and the first input terminal of the first nand gate 214 is high.
In some embodiments, the resistances of the first resistor 210 and the second resistor 211 may be 1k to 3k ohms, for example, 2k ohms.
In some embodiments provided by the present application, the aspect ratio of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 is greater than the aspect ratio of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209, so that the resistances of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 may be slightly smaller than the resistances of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209, so as to increase the charge rates of the first capacitor 212 and the second capacitor 213, and reduce the discharge rates of the first capacitor 212 and the second capacitor 213.
In some embodiments, the aspect ratio of the first PMOS tube 202, the second PMOS tube 203, the third PMOS tube 204, and the fourth PMOS tube 205 is equal to 150-250, e.g., 36/0.13; the aspect ratio of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209 is equal to 50-80, e.g., 12/0.13.
Fig. 4 shows a schematic block diagram of a sample-and-hold circuit according to an embodiment of the present application. The sample hold circuit comprises a PMOS tube 301, an NMOS tube 302, a resistor 303 and a capacitor 304. The grid electrode of the PMOS tube 301 is connected with the output Vout1 of the sampling signal generating circuit; the source stage of the PMOS tube 301 is connected with the source stage of the NMOS tube 302 and the output Vout3 of the error amplifying circuit; the drain of the PMOS tube 301 is connected with the drain of the NMOS tube 302 and the positive end of the resistor 303; the grid electrode of the NMOS tube 302 is connected with the output Vout2 of the sampling signal generating circuit; the source of the NMOS tube 302 is connected with the output Vout3 of the error amplifying circuit; the drain of the NMOS tube 302 is connected with the positive end of the resistor 303; the negative end of the resistor 303 is connected with the positive end of the capacitor 304 and the output end Vout; the negative terminal of the capacitor 304 is grounded to GND.
Vout1 and Vout2 are sampling signals, when the Vout1 signal is changed from high level to low level, the Vout2 signal is changed from low level to high level, the PMOS tube 301 and the NMOS tube 302 are both conducted, the sampling hold circuit samples the value of the error signal Vout3, and the holding sampling result of the resistor 303 and the capacitor 304 is output to an external equalizing circuit to control the gain of the external equalizing circuit. If the error signal is at a high level, the gain of the external equalizing circuit is improved; if the error signal is at low level, the gain of the external equalization circuit is reduced. Therefore, the gain of the external equalizing circuit automatically reaches the optimal state according to different input signals, and the purpose of self-adaptive control is achieved. The sampling hold circuit outputs through the sampling signal sampling hold error amplifying circuit, and the self-adaptive control function is realized.
The external equalizing circuit outputs a standard waveform generated by an operational amplifier 201 inside the sampling signal generating circuit; in a possible scenario, the nand gate 215 outputs a high level only when serdes encodes the longest 5-bit continuous 0 or 1 (i.e., the two inputs of the first nand gate 214 are respectively low and high when 5-bit continuous 0 or 1, and the two inputs of the first nand gate 214 are both the same when 4-bit continuous 0 or 1), thereby generating the sampling signal. Output to the sample-and-hold circuit through Vout1 and Vout 2. The sampling signal generating circuit can output the sampling signal only when the pulse width of the input signal of the high-speed serdes equalizing circuit is longest through the negative feedback network. Therefore, the self-adaptive analog control circuit provided by the application can be suitable for the response speed of the traditional operational amplifier circuit, and can realize the self-adaptive control function under the condition of wide pulse, so that the requirement of an equalization system on the response speed of the operational amplifier is reduced, the highest speed which can be supported by the circuit is improved, and meanwhile, the power consumption of the circuit is reduced.
While the application has been described in terms of the preferred embodiment, it is not intended to limit the application, but it will be apparent to those skilled in the art that variations and modifications can be made without departing from the spirit and scope of the application, and therefore the scope of the application is defined in the appended claims.
Claims (10)
1. An adaptive analog control circuit, comprising:
the error amplifying circuit is used for receiving the external equalizing circuit signal and generating a standard signal according to the external equalizing circuit signal, and generating an error signal by comparing the rising edge speed with the standard signal;
the sampling signal generation circuit is used for receiving the external equalization circuit signal, generating no sampling signal when the pulse width of the external equalization circuit signal is smaller than a preset pulse width, and generating a sampling signal when the pulse width of the external equalization circuit signal is larger than the preset pulse width;
and a sample-and-hold circuit for receiving the error signal from the error amplifying circuit and performing sample-and-hold based on the error signal when the sample signal is received from the sample signal generating circuit.
2. The adaptive analog control circuit according to claim 1, wherein the sampling signal generation circuit comprises a first operational amplifier (201), a common mode adjustment circuit, a first capacitor (212), a second capacitor (213), a first nand gate (214), a second nand gate (215), and an inverter (216);
two differential input ends of the first operational amplifier (201) are respectively connected with two output ends of an external equalization circuit, and two differential output ends of the first operational amplifier (201) are respectively connected with two differential input ends of the common mode adjustment circuit;
the positive end of the differential output end of the common mode adjusting circuit is connected with the positive end of the first capacitor (212) and the positive end of the first NAND gate (214), the negative end of the first capacitor (212) is grounded, the negative end of the differential output end of the common mode adjusting circuit is connected with the positive end of the second capacitor (213) and the negative end of the first NAND gate (214), and the negative end of the second capacitor (213) is grounded;
the output end of the first NAND gate (214) is connected with the input end of the second NAND gate (215), the other input end of the second NAND gate (215) is connected with an external enabling signal ENN, the output end of the second NAND gate (215) is connected with the input end of the phase inverter (216), and is connected with the first input end (Vout 1) of the sample-hold circuit in parallel, the output end of the phase inverter (216) is connected with the second input end (Vout 2) of the sample-hold circuit, the sampling signal is generated when the level of the first input end (Vout 1) is lower than the level of the second input end (Vout 2), and the sampling signal is not generated when the level of the second input end (Vout 2) is lower than the level of the first input end (Vout 1);
the common mode adjustment circuit is used for switching the charge and discharge states of the first capacitor (212) and the second capacitor (213) according to the differential input of the external equalization circuit, so that one of the first capacitor (212) and the second capacitor (213) receives charge from the common mode adjustment circuit, the other is discharged to the common mode adjustment circuit, and the common mode adjustment circuit is used for enabling the charge speed of the first capacitor (212) to be faster than the discharge speed of the first capacitor (212) and enabling the charge speed of the second capacitor (213) to be faster than the discharge speed of the second capacitor (213).
3. The adaptive analog control circuit according to claim 2, wherein the common mode adjustment circuit comprises a first PMOS transistor (202), a second PMOS transistor (203), a third PMOS transistor (204), a fourth PMOS transistor (205), a first NMOS transistor (206), a second NMOS transistor (207), a third NMOS transistor (208), a fourth NMOS transistor (209), a first resistor (210), and a second resistor (211);
the positive end of the differential output end of the first operational amplifier (201) is respectively connected with the grid electrode of the first PMOS tube (202) and the grid electrode of the third PMOS tube (204); the negative end of the differential output end of the first operational amplifier (201) is respectively connected with the grid electrode of the second PMOS tube (203) and the grid electrode of the fourth PMOS tube (205); the source stages of the first PMOS tube (202), the second PMOS tube (203), the third PMOS tube (204) and the fourth PMOS tube (205) are respectively connected with a power supply VCC; the drain electrode of the first PMOS tube (202) is connected with the drain electrode and the grid electrode of the first NMOS tube (206) and the grid electrode of the fourth NMOS tube (209); the drain electrode of the second PMOS tube (203) is connected with the drain electrode and the grid electrode of the second NMOS tube (207) and the grid electrode of the third NMOS tube (208); the source stage of the first NMOS tube (206), the source stage of the second NMOS tube (207), the source stage of the third NMOS tube (208) and the source stage of the fourth NMOS tube (209) are respectively grounded to GND; the drain electrode of the third PMOS tube (204) is connected with the positive end of the first resistor (210), the positive end of the first capacitor (212) and the input end of the first NAND gate (214); the drain electrode of the fourth PMOS tube (205) is connected with the positive end of the second resistor (211), the positive end of the second capacitor (213) and the other input end of the first NAND gate (214); the negative end of the first resistor (210) is connected with the drain electrode of the third NMOS tube (208); the negative end of the second resistor (211) is connected with the drain electrode of the fourth NMOS tube (209).
4. An adaptive analog control circuit according to claim 3, characterized in that the resistances of the first resistor (210) and the second resistor (211) are 1 k-3 k ohms.
5. The adaptive analog control circuit of claim 3, wherein the aspect ratio of the first PMOS transistor (202), the second PMOS transistor (203), the third PMOS transistor (204), and the fourth PMOS transistor (205) is greater than the aspect ratio of the first NMOS transistor (206), the second NMOS transistor (207), the third NMOS transistor (208), and the fourth NMOS transistor (209).
6. The adaptive analog control circuit of claim 5, wherein the aspect ratio of the first PMOS transistor (202), the second PMOS transistor (203), the third PMOS transistor (204), and the fourth PMOS transistor (205) is equal to 150-250; the width-to-length ratio of the first NMOS tube (206), the second NMOS tube (207), the third NMOS tube (208) and the fourth NMOS tube (209) is equal to 50-80.
7. The adaptive analog control circuit according to claim 1, wherein the error amplification circuit comprises a second operational amplifier (101), a bandpass network, and a summing amplifier (117); the output of the external equalization circuit generates the standard waveform through the second operational amplifier (101), the output of the external equalization circuit and the standard waveform are respectively output into the summing amplifier (117) through the band-pass network, and the summing amplifier (117) is used for comparing the rising and falling edge time difference of the output of the external equalization circuit and the standard waveform and generating the error signal.
8. The adaptive analog control circuit of claim 7, wherein the bandpass network comprises a third capacitor (102), a fourth capacitor (105), a fifth capacitor (108), a sixth capacitor (111), a third resistor (103), a fourth resistor (106), a fifth resistor (109), a sixth resistor (112), a seventh resistor (104), an eighth resistor (107), a ninth resistor (110), a tenth resistor (113), an eleventh resistor (114), a twelfth resistor (115), a thirteenth resistor (116);
the input end of the second operational amplifier (101) is respectively connected with the anodes of the fifth capacitor (108) and the sixth capacitor (111) and is connected with the output of the external equalizing circuit; the output end of the second operational amplifier (101) is respectively connected with the anodes of the third capacitor (102) and the fourth capacitor (105); the negative electrode of the third capacitor (102), the negative electrode of the fourth capacitor (105), the negative electrode of the fifth capacitor (108) and the negative electrode of the sixth capacitor (111) are respectively connected with the positive electrode of the third resistor (103), the positive electrode of the fourth resistor (106), the positive electrode of the fifth resistor (109) and the positive electrode of the sixth resistor (112), the negative electrode of the third resistor (103), the negative electrode of the fourth resistor (106), the negative electrode of the fifth resistor (109) and the negative electrode of the sixth resistor (112) are respectively connected with the positive electrode of the seventh resistor (104), the positive electrode of the eighth resistor (107), the positive electrode of the ninth resistor (110) and the positive electrode of the tenth resistor (113), and are respectively connected with four input ends of the addition amplifier (117); the anode of the eleventh resistor (114) is connected with a power supply, and the cathode of the eleventh resistor (104), the cathode of the eighth resistor (107) and the anode of the twelfth resistor (115) are connected; the twelfth resistor (115) negative electrode is connected with the ninth resistor (110) negative electrode, the tenth resistor (113) negative electrode and the thirteenth resistor (116) positive electrode; the negative electrode of the thirteenth resistor (116) is connected with the ground; the output terminal (Vout 3) of the summing amplifier (117) is output to a sample-and-hold circuit.
9. The adaptive analog control circuit according to claim 1, wherein the sample-and-hold circuit comprises a fifth PMOS transistor (301), a fifth NMOS transistor (302), a fourteenth resistor (303), and a seventh capacitor (304);
the grid electrode of the fifth PMOS tube (301) is connected with the first output end (Vout 1) of the sampling signal generation circuit; the source stage of the fifth PMOS tube (301) is connected with the source stage of the fifth NMOS tube (302) and the output end (Vout 3) of the error amplifying circuit; the drain of the fifth PMOS tube (301) is connected with the drain of the fifth NMOS tube (302) and the positive end of the fourteenth resistor (303); the grid electrode of the fifth NMOS tube (302) is connected with the second output end (Vout 2) of the sampling signal generating circuit; the source of the fifth NMOS tube (302) is connected with the output end (Vout 3) of the error amplifying circuit; the drain of the fifth NMOS tube (302) is connected with the positive end of the fourteenth resistor (303); the negative end of the fourteenth resistor (303) is connected with the positive end and the output end of the seventh capacitor (304); the negative end of the seventh capacitor (304) is grounded.
10. A serdes equalization system, characterized in that the serdes equalization system comprises an adaptive analog control circuit according to any of the claims 1 to 9.
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| CN202310436212.3A CN117097596A (en) | 2023-04-21 | 2023-04-21 | Adaptive analog control circuit for high-speed serdes equalization system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118092571A (en) * | 2024-04-23 | 2024-05-28 | 成都芯正微电子科技有限公司 | Portable programmable direct-current linear power supply generating circuit with variable slope |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118092571A (en) * | 2024-04-23 | 2024-05-28 | 成都芯正微电子科技有限公司 | Portable programmable direct-current linear power supply generating circuit with variable slope |
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