CN111510111A - Oscillation module and chip power-on method - Google Patents
Oscillation module and chip power-on method Download PDFInfo
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- CN111510111A CN111510111A CN202010342099.9A CN202010342099A CN111510111A CN 111510111 A CN111510111 A CN 111510111A CN 202010342099 A CN202010342099 A CN 202010342099A CN 111510111 A CN111510111 A CN 111510111A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application relates to the technical field of semiconductor integrated circuits, in particular to an oscillation module and a chip power-on method. Wherein the oscillation module includes: the device comprises a first oscillating unit and a second oscillating unit which are cascaded; the first oscillation unit is used for outputting a first clock signal when receiving a first trigger signal and generating a second trigger signal when the number of pulses of the first clock signal reaches a first threshold value; and the second oscillation unit is used for outputting a second clock signal to the integrated circuit system when receiving the second trigger signal, and generating a third trigger signal when the number of pulses of the second clock signal reaches a second threshold value, wherein the third trigger signal is used for controlling the first oscillation unit to stop outputting the first clock signal. According to the technical scheme, the integrated circuit can be prevented from resetting and losing efficacy while low-voltage starting is achieved, and power-on power consumption of the integrated circuit system is effectively controlled.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to an oscillation module and a chip power-on method.
Background
In the technical field of semiconductor integrated circuits, a system Power-on process is a process of slowly climbing a Power supply voltage, in the process, an integrated circuit system is kept static, a Power-on reset (POR) circuit releases a POR signal until the Power supply voltage reaches a preset voltage, so that the integrated circuit system is initialized, and after the initialization is finished, the integrated circuit starts to normally work.
However, when the power-on reset circuit releases the POR signal, the voltage reached by the power supply is lower than the voltage that can ensure the normal operation of the integrated circuit system. Taking the slow power-on process of the integrated circuit system with the normal working voltage as the high-voltage threshold (1.65V-5.5V) as an example, when the power-on reset circuit releases the POR signal, the minimum voltage reached by the power supply voltage is about 1V, which may cause adverse effects on the normal reset of the integrated circuit system.
The related art generally employs a ring oscillator to time and wait for the power supply voltage to reach a normal operating voltage, but the accuracy of the duty ratio of the clock signal generated by the ring oscillator is poor, and the power consumption thereof varies greatly with the power supply voltage.
Disclosure of Invention
The application provides an oscillation module and a chip power-on method, which can effectively control the power-on power consumption of an integrated circuit system.
As a first aspect of the present application, there is provided an oscillation module including: the device comprises a first oscillating unit and a second oscillating unit which are cascaded;
the first oscillation unit is used for outputting a first clock signal when receiving a first trigger signal and generating a second trigger signal when the number of pulses of the first clock signal reaches a first threshold value;
and the second oscillation unit is used for outputting a second clock signal to the integrated circuit system when receiving the second trigger signal and generating a third trigger signal when the number of pulses of the second clock signal reaches a second threshold value, wherein the third trigger signal is used for controlling the first oscillation unit to stop outputting the first clock signal.
Optionally, a first oscillator, the first oscillator comprising an input terminal, an output terminal, and a control terminal; the input end of the first oscillator is used for receiving the first trigger signal, and when the first trigger signal is received, the output end of the first oscillator outputs a first clock signal;
the first counter is used for receiving the first clock signal and counting the pulses of the first clock signal, and when the number of the pulses of the first clock signal reaches a first threshold value, the first counter generates a second trigger signal.
Optionally, a second oscillator comprising an input and an output; the input end of the second oscillator is used for receiving the second trigger signal, and when the second trigger signal is received, the output end of the second oscillator outputs a second clock signal;
and the second counter is used for receiving the second clock signal and counting the pulses of the second clock signal, and when the number of the pulses of the second clock signal reaches a second threshold value, the second counter generates a third trigger signal to the control end of the first oscillator.
As a second aspect of the present application, there is provided a chip power-on method, including:
releasing a first trigger signal when it is determined that the power supply voltage increases to a first target voltage, the first trigger signal being for triggering a first oscillating unit as described in the first aspect of the present application;
oscillating to form a first clock signal when the first trigger signal is received;
calculating the number of pulses in the first clock signal, and generating a second trigger signal when the number of pulses reaches a first threshold, wherein the second trigger signal is used for triggering a second oscillation unit according to the first aspect of the present application;
when receiving the second trigger signal, oscillating to form a second clock signal and transmitting the second clock signal to the integrated circuit system;
and calculating the number of pulses in the second clock signal, and generating a third trigger signal when the number of pulses reaches a second threshold value, wherein the third trigger signal is used for controlling to stop the first clock signal.
Optionally, when the number of pulses reaches a first threshold, the power supply voltage reaches a second target voltage, and the second target voltage is 90% to 97% of a normal operating voltage.
Optionally, during the chip power-on method, the power supply voltage is gradually increased.
Optionally, when the number of pulses reaches a second threshold, the power supply voltage reaches a normal operating voltage.
Optionally, the first target voltage ranges from 50% to 60% of the normal operating voltage.
The technical scheme at least comprises the following advantages: according to the technical scheme, the integrated circuit can be prevented from resetting and losing efficacy while low-voltage starting is achieved, and power-on power consumption of the integrated circuit system is effectively controlled.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a block diagram of an oscillating module provided in an embodiment of a first aspect of the present application;
FIG. 2 is a flowchart of a method for powering on a chip according to an embodiment of a second aspect of the present application;
fig. 3 is a timing diagram during a power supply voltage ramp in accordance with the present application.
100. The oscillator includes a first oscillation unit, 110, a first oscillator, 120, a first counter, 200, a second oscillation unit, 210, a second oscillator, 220, and a second counter.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
As a first aspect of the present invention, there is provided an oscillation module, referring to fig. 1, including a first oscillation unit 100 and a second oscillation unit 200 which are cascaded;
the first oscillation unit 100 is used for oscillating and outputting a first clock signal U L V clock when receiving a first trigger signal1, and generating a second trigger signal2 when the number of pulses of the first clock signal U L V clock reaches a first threshold value;
the second oscillating unit 200 is configured to oscillate and output the second clock signal U L P clock to the integrated circuit system when receiving the second trigger signal2, and generate a third trigger signal3 when the number of pulses of the second clock signal U L P clock reaches a second threshold, where the third trigger signal3 is configured to control the first oscillating unit 100 to stop outputting the first clock signal U L V clock.
The first oscillation unit 100 includes:
the first oscillator 110, the first oscillator 110 comprises an input terminal, an output terminal and a control terminal, the input terminal of the first oscillator 110 is configured to receive the first trigger signal1, and when receiving the first trigger signal1, the output terminal of the first oscillator 110 outputs a first clock signal U L V clock.
A first counter 120, the first counter 120 being configured to receive the first clock signal U L V clock and count pulses of the first clock signal U L V clock, and when the number of pulses of the first clock signal U L V clock reaches a first threshold, the first counter 120 generates a second trigger signal 2.
The second oscillation unit 200 includes:
the second oscillator 210 comprises an input end and an output end, the input end of the second oscillator 210 is used for receiving the second trigger signal2, and when the second trigger signal2 is received, the output end of the second oscillator 210 outputs a second clock signal U L P clock.
A second counter 220, wherein the second counter 220 is configured to receive the second clock signal U L P clock, count pulses of the second clock signal U L P clock, and generate a third trigger signal3 to the control terminal of the first oscillator 110 when the number of pulses of the second clock signal U L P clock reaches a second threshold value.
The method comprises the steps that in the power-on process of an integrated circuit, the power supply voltage of the integrated circuit is gradually increased, when the power supply voltage is increased to a first target voltage V1, a first trigger signal1 capable of enabling an oscillation module to work is released, the range of the first target voltage V1 is 50% -60% of a normal working voltage V3, when the number of pulses of a first clock signal U L V clock reaches a first threshold value, the power supply voltage reaches a second target voltage V2, the second target voltage V2 is 90% -97% of the normal working voltage V3, when a second clock signal U L P clock is output to the integrated circuit system in an oscillation mode, the integrated circuit system is initialized, and after the initialization is completed, the integrated circuit starts to work normally.
Referring to fig. 3, when the power supply voltage reaches the first target voltage V1, the first oscillating unit 100 of the oscillating module starts to operate, the first oscillating unit 100 starts to oscillate to form a first clock signal U L V clock, the number of pulses of the first clock signal U L V clock is counted, when the number of pulses of the first clock signal U L V clock reaches the first threshold, the power supply voltage reaches the second target voltage V2 which is 90% -97% of the normal operating voltage V3, the second oscillating unit 200 generates the second trigger signal2, when the second oscillating unit 200 receives the second trigger signal2, the second oscillating unit starts to oscillate to form a second clock signal U L P clock, and outputs the second clock signal U L P clock to the integrated circuit system, the number of pulses of the second clock signal U L Pclock is counted, when the number of pulses of the second clock signal U L P clock reaches the second threshold, the power supply voltage reaches the normal operating voltage V3, and the integrated circuit stops outputting the first clock signal Vclock, that is the integrated circuit 100 starts to operate.
Exemplarily, the following steps are carried out:
the integrated circuit system with the normal working voltage V3 of the power supply voltage being 1.65V starts to work when the power supply voltage reaches a first target voltage V11V, the first oscillation unit 100 of the oscillation module starts oscillation to form a first clock signal U L V clock, counts the number of pulses of the first clock signal U L V clock, starts oscillation to form a second clock signal U L P clock when the number of pulses of the first clock signal U L V clock reaches a first threshold and the power supply voltage reaches a second target voltage V21.6V, outputs the second clock signal U L P clock to the integrated circuit system, initializes according to the second clock signal U L P clock when the second oscillation unit 200 receives the second trigger signal U L V clock 2, counts the number of pulses of the second clock signal U L P clock, and stops outputting the second clock signal U L P clock when the number of pulses of the second clock signal U382P clock reaches the normal working voltage V V, and controls the power supply voltage to stop being the first clock signal U V31.65V.
As a second aspect of the present application, there is provided a chip power-on method based on the oscillation module, and referring to fig. 2, the chip power-on method includes:
s1: determining that the power supply is increasing to the first target voltage V1 releases the first trigger signal1, which first trigger signal1 is used to trigger the first oscillating unit 100 according to the first aspect of the present application.
In step S1, in the power-on process of the integrated circuit, the power voltage of the integrated circuit gradually increases, and when the power voltage increases to the first target voltage V1, the first trigger signal1 enabling the oscillation module to operate is released, where the range of the first target voltage V1 is 50% to 60% of the normal operating voltage V3, so that the low-voltage start-up of the oscillation module can be achieved.
S2, when the first oscillating unit 100 receives the first trigger signal1, the first oscillating unit 100 starts oscillating to form a first clock signal U L V clock.
Illustratively, when the first oscillator 110 of the first oscillation unit 100 receives the first trigger signal1, the first oscillator 110 starts oscillation, and oscillates to form a first clock signal U L V clock.
S3, the first oscillating unit 100 counts the number of pulses of the first clock signal U L V clock, and generates a second trigger signal2 when the number of pulses reaches a first threshold, the second trigger signal2 being used for triggering the second oscillating unit 200 according to the first aspect of the present application.
Wherein, for step S3, when the number of pulses reaches the first threshold, the power voltage reaches a second target voltage V2, and the second target voltage V2 is 90% to 97% of the normal operating voltage V3;
the first counter 120 counts the number of pulses of the first clock signal U L V clock, and generates the second trigger signal2 when the number of pulses reaches a first threshold.
S4, the second oscillating unit 200 oscillates to form a second clock signal U L P clock when receiving the second trigger signal2, and transmits the second clock signal U L P clock to the integrated circuit system.
Illustratively, when the second oscillator 210 of the second oscillating unit 200 receives the second trigger signal2, the second oscillator 210 starts oscillating to form a second clock signal U L P clock.
When the power supply voltage reaches 90% -97% of the normal working voltage V3, a second clock signal U L Pclock is formed and transmitted to the integrated circuit system, so that the integrated circuit system is initialized, and the low-power-consumption operation of the oscillation module can be avoided while the reset failure of the integrated circuit is avoided.
And S5, calculating the number of pulses in the second clock signal U L P clock, and generating a third trigger signal3 when the number of pulses reaches a second threshold value, wherein the third trigger signal3 is used for controlling the stopping of the first clock signal U L V clock.
Illustratively, the second counter 220 of the second oscillating unit 200 counts a number of pulses in said second clock signal U L P clock, and generates a third trigger signal3 when said number of pulses reaches a second threshold value.
When the third trigger signal3 is generated, the power supply voltage reaches the normal working voltage V3, the integrated circuit system can work normally, and at the moment, the first clock signal U L V clock is controlled to stop, so that the power consumption of the system is effectively controlled.
FIG. 3 is a timing diagram of a power-up process of an integrated circuit, wherein an oblique line is a ramp-up state diagram of a power supply voltage, and shows a relationship between a power supply voltage value and time in the ramp-up process of the power supply voltage, the oblique line has three nodes, namely Q1(T1, V1), Q2(T2, V2) and Q3(T3, V3), wherein Q1 shows that a first trigger voltage signal1 is received at a time T1, the power supply voltage is ramped up to a first target voltage V1, a first clock signal U1V clock is formed, the first clock signal U1V clock is generated until the third trigger voltage signal1 is received and stopped at the time T1, Q1 shows that a second trigger voltage signal1 is received at the time T1, the power supply voltage is ramped up to the second target voltage V1, a second clock signal U1P clock is formed, the second clock signal U1P clock signal is generated until the third trigger voltage signal U1P clock signal is received and the power supply voltage is ramped up to the time T1, the third trigger voltage is generated until the time T1, the power supply voltage is normally generated, and the third trigger voltage is generated at the time T1.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. An oscillation module, characterized in that the oscillation module comprises: the device comprises a first oscillating unit and a second oscillating unit which are cascaded;
the first oscillation unit is used for outputting a first clock signal when receiving a first trigger signal and generating a second trigger signal when the number of pulses of the first clock signal reaches a first threshold value;
and the second oscillation unit is used for outputting a second clock signal to the integrated circuit system when receiving the second trigger signal and generating a third trigger signal when the number of pulses of the second clock signal reaches a second threshold value, wherein the third trigger signal is used for controlling the first oscillation unit to stop outputting the first clock signal.
2. The oscillation module of claim 1, wherein the first oscillation unit comprises:
a first oscillator comprising an input terminal, an output terminal, and a control terminal; the input end of the first oscillator is used for receiving the first trigger signal, and when the first trigger signal is received, the output end of the first oscillator outputs a first clock signal;
the first counter is used for receiving the first clock signal and counting the pulses of the first clock signal, and when the number of the pulses of the first clock signal reaches a first threshold value, the first counter generates a second trigger signal.
3. The oscillation module of claim 2, wherein the second oscillation unit comprises:
a second oscillator comprising an input and an output; the input end of the second oscillator is used for receiving the second trigger signal, and when the second trigger signal is received, the output end of the second oscillator outputs a second clock signal;
and the second counter is used for receiving the second clock signal and counting the pulses of the second clock signal, and when the number of the pulses of the second clock signal reaches a second threshold value, the second counter generates a third trigger signal to the control end of the first oscillator.
4. A chip power-on method is characterized by comprising the following steps:
releasing a first trigger signal when the power supply voltage is determined to be increased to a first target voltage, wherein the first trigger signal is used for triggering a first oscillating unit according to any one of claims 1-3;
oscillating to form a first clock signal when the first trigger signal is received;
calculating the number of pulses in the first clock signal, and generating a second trigger signal when the number of pulses reaches a first threshold, the second trigger signal being used for triggering a second oscillation unit according to any one of claims 1 to 3;
when receiving the second trigger signal, oscillating to form a second clock signal and transmitting the second clock signal to the integrated circuit system;
and calculating the number of pulses in the second clock signal, and generating a third trigger signal when the number of pulses reaches a second threshold value, wherein the third trigger signal is used for controlling to stop the first clock signal.
5. The method for powering on a chip according to claim 4, wherein when the number of pulses reaches a first threshold, the power supply voltage reaches a second target voltage, the second target voltage being 90% to 97% of a normal operating voltage.
6. The on-chip power-on method according to claim 4, wherein the power supply voltage is gradually increased during the on-chip power-on method.
7. The method for powering on a chip according to claim 4, characterized in that said power supply voltage reaches a normal operating voltage when said number of pulses reaches a second threshold value.
8. The method for powering on a chip according to claim 4, wherein the first target voltage ranges from 50% to 60% of the normal operating voltage.
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| CN202010342099.9A CN111510111B (en) | 2020-04-27 | 2020-04-27 | Oscillation module and chip powering-up method |
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| CN202010342099.9A CN111510111B (en) | 2020-04-27 | 2020-04-27 | Oscillation module and chip powering-up method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969631A (en) * | 1996-06-14 | 1999-10-19 | Temic Telefunken Microelectronic Gmbh | Method and control system for the synchronized transmission of digital data |
| EP2573683A1 (en) * | 2010-05-20 | 2013-03-27 | Renesas Electronics Corporation | Data processor and electronic control unit |
| CN106291148A (en) * | 2015-05-20 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Test circuit and method of testing thereof |
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2020
- 2020-04-27 CN CN202010342099.9A patent/CN111510111B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969631A (en) * | 1996-06-14 | 1999-10-19 | Temic Telefunken Microelectronic Gmbh | Method and control system for the synchronized transmission of digital data |
| EP2573683A1 (en) * | 2010-05-20 | 2013-03-27 | Renesas Electronics Corporation | Data processor and electronic control unit |
| CN106291148A (en) * | 2015-05-20 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Test circuit and method of testing thereof |
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| CN111510111B (en) | 2024-03-15 |
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