CN111445862B

CN111445862B - Display panel and display device

Info

Publication number: CN111445862B
Application number: CN202010394181.6A
Authority: CN
Inventors: 肖云升; 青海刚; 董向丹
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-05-11
Filing date: 2020-05-11
Publication date: 2022-05-24
Anticipated expiration: 2040-05-11
Also published as: CN111445862A

Abstract

The invention relates to a display panel and a display device. The display panel comprises a display area, a peripheral area and a plurality of shift register units. The display area comprises a first boundary extending in a non-straight line; the peripheral area is adjacent to the display area and comprises a second boundary and a corner sub-area which do not extend linearly; the corner sub-region is located between the first boundary and the second boundary; the plurality of shift register units are positioned in the corner sub-area, and the extending directions of the plurality of shift register units are the same. According to the embodiment of the invention, the same characteristics of the transistors with the same connection relation in the plurality of shift register units can be ensured, and the uniformity of display of the display panel can be improved.

Description

Display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of display panel technology, the frame of the display panel is narrower and narrower, and more display panels with diversified appearances are provided. For a special-shaped display panel, how to arrange a GOA (Gate On Array, Array substrate row driver) circuit in a narrower frame to improve the display performance of the display panel is a technical problem to be solved.

Disclosure of Invention

The invention provides a display panel and a display device to solve the defects in the related art.

According to a first aspect of embodiments of the present invention, there is provided a display panel including:

a display area including a non-linearly extending first boundary;

a peripheral region adjacent to the display region, the peripheral region including a non-linearly extending second border and corner sub-regions; the corner sub-region is located between the first boundary and the second boundary;

the plurality of shift register units are located in the corner sub-region, and the extending directions of the plurality of shift register units are the same.

In one embodiment, a plurality of the shift register units are divided into a plurality of shift register unit groups, and at least one shift register unit is included in the shift register unit groups; for each of the shift register unit groups, when the shift register unit group includes N shift register units, centers of the N shift register units are aligned in a first direction, the first direction intersects with the extending direction, and N is a positive integer greater than 1.

In one embodiment, the extending direction of the central connecting line of the plurality of shift register unit groups is the same as the extending direction of the first boundary.

In one embodiment, N is 2, 3 or 4.

In one embodiment, the number of shift register cells in each of the shift register cell groups is the same.

In one embodiment, the first direction and the extension direction are perpendicular to each other.

In one embodiment, the shift register cell includes a plurality of transistors; the channel directions of the transistors in the plurality of shift register units are the same, and the transistors are connected in the same relation.

In one embodiment, the plurality of transistors includes a first type transistor and a second type transistor; the channel direction of the first type transistor is the same as the extension direction; the channel direction of the second-type transistor is a first direction, and the first direction is intersected with the extending direction; the transistors in the plurality of shift register units, which are connected in the same relationship, are of the same type.

In one embodiment, the first boundary is arcuate and the second boundary is arcuate.

According to a second aspect of the embodiments of the present invention, there is provided a display device including the display panel described above.

According to the embodiments, since the plurality of shift register units located in the corner sub-region between the first boundary and the second boundary have the same extending direction, the channel directions of the transistors having the same connection relationship among the plurality of shift register units are the same, and the same angle between the crystallization orientation of a-Si (amorphous silicon) in the active layer of the transistor having the same connection relationship among the plurality of shift register units and the channel direction can be ensured in the same crystallization process.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic view showing a structure of a display panel according to the related art;

FIG. 2 is a diagram showing a relation between a-Si crystallization orientation and a channel direction according to the related art;

FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram illustrating another display panel according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is an enlarged schematic view of B of FIG. 5;

FIG. 7 is a diagram illustrating the relationship between the crystallization orientation of a-Si and the channel direction according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of an equivalent circuit of a shift register unit according to an embodiment of the present invention;

fig. 9 is a timing diagram illustrating the operation of a shift register unit according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

In the related art, there is a display panel including a display area AA and a peripheral area Z, as shown in fig. 1, corners of the display area AA are not right angles but rounded, and corners of the peripheral area Z adjacent to the display area AA are also rounded, so that an area between corners of the display area AA and corners of the peripheral area Z located opposite to each other in the peripheral area Z is an irregularly shaped area. For convenience of description, a region between the corners of the display area AA and the peripheral area Z located opposite to each other in the peripheral area Z is referred to as a corner sub-region 11. In the corner sub-region 11, the plurality of shift register units 12 are arranged toward the display region AA along the rounded corner of the display region AA, and therefore, the extending directions of the plurality of shift register units 12 on the display panel are different from each other.

It should be noted that each shift register unit 12 may include a plurality of transistors, for example, each shift register unit 12 may be a shift register unit with an 8T2C structure, a 7T2C structure, or a 6T2C structure, but is not limited thereto. For each shift register cell 12, the channel direction of the transistors in the shift register cell 12 is either parallel to the extension direction of the shift register cell 12 or perpendicular to the extension direction of the shift register cell 12. Therefore, the channel directions of the transistors in different shift register units 12 are different, for example, the channel directions of the transistors having the same connection relationship are different, or the channel directions of the transistors having the same function are different.

It should be noted that, in the process of manufacturing a transistor, the material of the active layer of the transistor is a-Si before the crystallization process is performed, and after the crystallization process, the a-Si is crystallized and becomes p-Si (polycrystalline silicon), and the included angle between the crystallization orientation of the a-Si and the channel direction of the transistor affects the characteristics of the transistor.

In the related art, an ELA (excimer laser annealing) process can be used to achieve the conversion of a-Si into p-Si. In the ELA process, a-Si is scanned in a predetermined direction using a laser, and the crystallization orientation of a-Si is related to the scanning direction of the laser. Since the laser scanning direction is the same, the crystallization orientations 22 of a-Si in the active layers 21 of the transistors in the plurality of shift register cells 12 are substantially the same as shown in fig. 2, wherein the channel 23 is located between a source region (not shown) and a drain region (not shown) of the active layers 21. However, since the channel directions of the transistors in the plurality of shift register units 12 are different, the included angles between the crystallization orientations of the a-Si in the active layers 21 of the transistors in the plurality of shift register units 12 and the channel directions of the transistors are different, the characteristics of the transistors in the plurality of shift register units 12 are different, and when the characteristics of the transistors in the plurality of shift register units 12 having the same connection relationship are different, the gate driving signals output by the plurality of shift register units 12 are different, and thus, the uniformity of the display panel is poor.

In addition, the width of the frame of the display panel is greatly limited by the layout of the GOA (Gate On Array) circuits. The GOA circuit may include a plurality of cascaded shift register cells 12. Therefore, how to perform reasonable circuit layout to fully utilize the limited frame space and achieve the narrowing of the frame to the maximum extent is also a technical problem to be solved.

In view of the above technical problems, embodiments of the present invention provide a display panel and a display device, so as to solve the above technical problems, and to facilitate improvement of uniformity of display of the display panel.

The embodiment of the invention provides a display panel. As shown in fig. 3 to 4, the display panel includes a display area AA, a peripheral area Z, and a plurality of shift register units 12.

As shown in fig. 3, the peripheral area Z is adjacent to the display area AA. The display area AA comprises a non-linearly extending first border 31. The peripheral zone Z comprises the non-linearly extending second border 32 and the corner sub-zone 11. The corner sub-region 11 is located between the first boundary 31 and the second boundary 32.

As shown in fig. 4, a plurality of the shift register units 12 are located in the corner sub-region 11, and the extending directions of the plurality of the shift register units 12 are the same.

Note that the extending direction of the shift register unit 12 may be the extending direction of the long side of the shift register unit 12.

In this embodiment, since the plurality of shift register units located in the corner sub-region between the first boundary and the second boundary have the same extending direction, the channel directions of the transistors having the same connection relationship among the plurality of shift register units are the same, and the same angle between the crystallization orientation of a-Si in the active layer of the transistor having the same connection relationship among the plurality of shift register units and the channel direction can be ensured in the same crystallization process.

The display panel provided by the embodiment of the present invention is briefly described above, and the display panel provided by the embodiment of the present invention is described in detail below.

The embodiment of the invention also provides a display panel. As shown in fig. 3 to 4, the display panel includes a display area AA, a peripheral area Z, and a plurality of shift register units 12.

As shown in fig. 3, the display area AA is located in the middle of the display panel and includes pixels (not shown) arranged in an array for displaying a picture. Specifically, each pixel may be driven to emit light by a corresponding pixel circuit, wherein the pixel circuit may perform an operation of turning on, writing data, or resetting under the control of the corresponding shift register unit 12. The pixel circuits may be located in the display area AA, and the shift register unit 12 is located in the peripheral area Z.

As shown in fig. 3, the corners of the display area AA are rounded. Specifically, the boundaries of the display area AA include a first wide-side boundary W1, a first long-side boundary L1, and a first boundary 31. The first wide side boundary W1 and the first long side boundary L1 extend linearly, and the first boundary 31 extends non-linearly. The first boundary 31 is located between the adjacent first wide-side boundary W1 and first long-side boundary L1, and the first boundary 31 may have an arc shape to perform a transition function.

As shown in fig. 3, a first turning point D1 exists between the first long-side boundary L1 and the first boundary 31, a second turning point D2 exists between the first wide-side boundary W1 and the first boundary 31, and the first boundary 31 is located between the first turning point D1 and the second turning point D2.

As shown in fig. 3, the peripheral area Z is adjacent to the display area AA. The peripheral area Z may at least partially surround the display area AA. In the present embodiment, the peripheral area Z completely surrounds the display area AA.

As shown in fig. 3, corners of the peripheral area Z away from the display area AA are rounded. Specifically, the boundaries of the peripheral area Z away from the display area AA include the second broadside boundary W2, the second long-side boundary L2, and the second boundary 32. The second wide side boundary W2 and the second long side boundary L2 extend linearly, and the second boundary 32 extends non-linearly. The second boundary 32 is located between the adjacent second wide side boundary W2 and second long side boundary L2, and the second boundary 32 may be curved to provide a transition.

As shown in fig. 3, a third transition point D3 exists between the second long-side boundary L2 and the second boundary 32, a fourth transition point D4 exists between the second wide-side boundary W2 and the second boundary 32, and the second boundary 32 is located between the third transition point D3 and the fourth transition point D4.

As shown in fig. 3, the peripheral region Z includes the corner sub-region 11, a first straight stripe region (not shown), and a second straight stripe region (not shown). The first straight strip-shaped area is located between the first long side boundary L1 and the second long side boundary L2 which are opposite, the second straight strip-shaped area is located between the first broadside boundary W1 and the second broadside boundary W2 which are opposite, and the corner sub-area 11 is located between the first boundary 31 and the second boundary 32 which are opposite.

In this embodiment, the GOA circuit of the display panel may include a plurality of cascaded shift register units 12, wherein an output terminal of a shift register unit 12 of a previous stage may be connected to an input terminal of a shift register unit 12 of a next stage. In the GOA circuit, a part of the shift register cells 12 are located in the first straight stripe region, and another part of the shift register cells 12 are located in the corner sub-region 11.

In the present embodiment, the plurality of shift register units 12 in the first stripe region have the same extending direction, and can be linearly arranged along the first long side boundary L1.

In the present embodiment, as shown in fig. 4, the extending directions of the plurality of shift register cells 12 in the corner sub-region 11 are also the same. The actual structure of the display panel in this embodiment is as shown in fig. 5, and as can be seen from fig. 5, the extending directions of the plurality of shift register units 12 in the corner sub-region 11 are the same.

In this embodiment, as shown in fig. 6, each shift register unit 12 has an 8T2C structure, and includes transistors T1 to T8, C1, and C2, where devices in the shift register unit 12 may be connected through a via 41, or may be connected in other manners, for example, the transistor T6 and the transistor T7 are adjacent and connected, and the two may be connected through the common active layer 21. The channel directions of the transistors T1 to T8 are the first direction Y, the extending direction X of the shift register unit, the first direction Y, and the first direction Y, respectively. The first direction Y intersects with the extending direction X of the shift register unit and is perpendicular to the extending direction X. The first direction Y may be a direction in which long sides of the display panel extend, and the extending direction X of the shift register unit may be a direction in which short sides of the display panel extend.

In this embodiment, as shown in fig. 6, the channel directions of the transistors in the same connection relationship in the plurality of different shift register units 12 are the same. For example, in the plurality of different shift register units 12, the channel directions of the transistors T1 are the same, the channel directions of the transistors T2 are the same, and the channel directions of the transistors T … … and T8 are the same.

In the display panel of the present embodiment, the material of the active layer 21 of the transistors T1 to T8 is a-Si before the crystallization process is performed, the laser scanning direction is the first direction Y in the process of converting a-Si into p-Si by the ELA process, and after the laser scanning, as shown in fig. 7, the crystallization orientations 22 of a-Si in the active layer 21 of the transistors in the plurality of shift register units 12 are substantially the same, and are respectively the first direction Y.

In this way, since the channel directions of the transistors with the same connection relation in the plurality of shift register units are the same, the same included angle of the crystallization orientation of the a-Si in the active layer of the transistor with the same connection relation in the plurality of shift register units relative to the channel direction can be ensured in the same crystallization process, and further, the same characteristics of the transistors with the same connection relation in the plurality of shift register units can be ensured, which is beneficial to improving the uniformity of display of the display panel.

In the present embodiment, as shown in fig. 6, the transistors T1 to T8 included in each shift register unit 12 are divided into a first type transistor and a second type transistor. The channel direction of the first-type transistor is the same as the extending direction X, the channel direction of the second-type transistor is the first direction Y, and the transistors in the shift register units 12 having the same connection relationship are of the same type. For example, the transistors T1, T3-T8 belong to the second type of transistor, and the transistor T2 belongs to the first type of transistor.

In this embodiment, an equivalent circuit of the shift register unit 12 is shown in fig. 8. Each shift register unit 12 includes an INPUT terminal INPUT and an OUTPUT terminal OUTPUT, the INPUT terminal INPUT of the first stage of the shift register unit 12 can INPUT a specified clock signal, and the OUTPUT terminal OUTPUT of the first stage of the shift register unit 12 OUTPUTs a corresponding gate driving signal. From the second stage shift register unit 12, the INPUT terminal INPUT of each shift register unit 12 is connected to the OUTPUT terminal OUTPUT of the previous stage shift register unit 12, and the OUTPUT terminal OUTPUT OUTPUTs a corresponding gate driving signal.

In the present embodiment, as shown in fig. 6, each shift register unit 12 is connected to the first clock signal line CK, the second clock signal line CB, the high-level signal line VGH, and the low-level signal line VGL, respectively. Specifically, the shift register unit 12 may be connected to the first clock signal line CK, the second clock signal line CB, the high-level signal line VGH, and the low-level signal line VGL through the via-holes 41 for conduction, respectively. The first clock signal line CK, the second clock signal line CB, the high level signal line VGH, and the low level signal line VGL are used for providing a first clock signal CK, a second clock signal CB, a high level signal, and a low level signal, respectively. Wherein a level value of the high level signal is greater than a level value of the low level signal.

In this embodiment, the gates of the transistors T1 through T8 are located in different metal layers from the first clock signal line CK, the second clock signal line CB, the high level signal line VGH, and the low level signal line VGL, and the first clock signal line CK, the second clock signal line CB, the high level signal line VGH, and the low level signal line VGL may be located in different metal layers, but the invention is not limited thereto.

In this embodiment, the timing of the INPUT signal inuput inputted from the INPUT terminal INPUT of one shift register unit 12, the first clock signal ck and the second clock signal cb received by the shift register unit 12, the level signal at the node N2 of the shift register unit 12, and the OUTPUT signal OUTPUT outputted from the OUTPUT terminal OUTPUT of the shift register unit 12 are as shown in fig. 9.

In the present embodiment, during the operation of the shift register unit 12, in the first stage S1, the first clock signal ck and the input signal inuput are at low level, the transistor T1 and the transistor T3 are turned on, and the transistor T2, the transistor T4, the transistor T5, and the transistor T6 are turned on. The output signal output from the shift register unit 12 is high.

In the second stage S2, the first clock signal ck is at a high level while the second clock signal cb is at a low level, the transistor T1, the transistor T3, the transistor T4, and the transistor T6 are turned off, the transistor T2, the transistor T5, and the transistor T7 are turned on, and the output signal output from the shift register unit 12 is at a low level.

In the third stage S3, the first clock signal ck is at a low level and the second clock signal cb is at a high level, the transistor T1, the transistor T3, and the transistor T4 are turned on, the transistor T5 is turned off, and the output signal output from the shift register unit 12 is at a high level.

In the 4 th stage S4, the first clock signal ck is at a high level while the second clock signal cb is at a low level, the transistor T1 and the transistor T3 are turned off, the node N1 is kept at a low level, the node N2 is kept at a high level, so the transistor T4 is turned on, the transistor T5 is turned off, and the shift register unit 12 keeps outputting at a high level.

The embodiment of the invention also provides a display panel. In the present embodiment, as shown in fig. 5, the plurality of shift register units 12 are divided into a plurality of shift register unit groups B, and the shift register unit group B includes at least one shift register unit 12.

In one embodiment, as shown in FIG. 4, one shift register cell 12 is included in each shift register cell group B. In this embodiment, the extending direction of the center O connecting line S of the plurality of shift register units 12 is the same as the extending direction of the first boundary 31. The plurality of shift register units 12 may be arranged in a ladder shape. Therefore, the space occupied by the shift register unit can be reduced, the width of the peripheral area in the direction in which the short side of the display panel extends can be reduced, and the narrow frame can be realized.

In another embodiment, the shift register cell group B includes N shift register cells, N being a positive integer greater than 1. For each of the shift register unit groups B, when the shift register unit group B includes N shift register units, centers O of the N shift register units are aligned in the first direction Y.

In one embodiment, as shown in fig. 5, N is 2. That is, two shift register cells 12 are included in each shift register cell group B. The centers of the two shift register cells 12 are aligned in the same shift register cell group B. Like this, can reduce the number of times of buckling of first clock signal line CK, second clock signal line CB, high level signal line VGH and low level signal line VGL, be favorable to reducing its space that occupies, can reduce the width of peripheral area in the direction that the minor face of display panel extends, be favorable to realizing the narrow frame.

It should be noted that in other embodiments, N may also be 3, 4 or other values.

In one embodiment, the extending direction of the central connecting line of the plurality of shift register unit groups B is the same as the extending direction of the first boundary 31. That is, a plurality of shift register unit groups B may be arranged in a staircase shape. For example, when two shift register cells 12 are included in each shift register cell group B, the extending direction of the center connecting lines of a plurality of the shift register cell groups B is the same as the extending direction of the first boundary 31. Therefore, the space occupied by the shift register unit can be reduced, the width of the peripheral area in the direction in which the short side of the display panel extends can be reduced, and the narrow frame can be realized.

In one embodiment, the number of shift register cells 12 in different shift register cell groups B may be different.

In another embodiment, the number of shift register cells 12 in a portion of the plurality of shift register cell groups B is the same.

In yet another embodiment, the number of shift register cells in each of said shift register cell groups B is the same, as shown in fig. 5. The number of shift register cells in each shift register cell group B is two.

In the embodiment of the present invention, the display panel may be an AMOLED (Active-matrix organic light-emitting diode) display panel, but is not limited thereto.

The embodiment of the invention also provides a display device which comprises a display module and the display panel of any one of the embodiments.

In this embodiment, since the plurality of shift register units located in the corner sub-region between the first boundary and the second boundary have the same extending direction, the channel directions of the transistors having the same connection relationship in the plurality of shift register units are the same, and the same angle between the crystallization orientation of a-Si in the active layer of the transistors having the same connection relationship in the plurality of shift register units and the channel direction can be ensured in the same crystallization process.

It should be noted that, the display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.

In the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims

1. A display panel, comprising:

a display area including a non-linearly extending first boundary;

The plurality of shift register units are positioned in the corner sub-region, and the extension directions of the plurality of shift register units are the same;

the first clock signal line is positioned on one side, away from the display area, of the shift register unit, and each shift register unit is connected with the first clock signal line;

the second clock signal line is positioned on one side of the shift register units away from the display area, and each shift register unit is respectively connected with the second clock signal line;

the high-level signal line is positioned on one side of the shift register units away from the display area, and each shift register unit is connected with the high-level signal line;

the low-level signal line sequentially penetrates through each shift register unit, and each shift register unit is connected with the low-level signal line;

the plurality of shift register units are divided into a plurality of shift register unit groups, and each shift register unit group comprises at least one shift register unit;

for each of the shift register unit groups, when the shift register unit group includes N shift register units, centers of the N shift register units are aligned in a first direction, the first direction intersects the extending direction, N is a positive integer greater than 1; the sides, far away from the display area, of the N shift register units are basically aligned, the sections, where the N connecting positions of the N shift register units are located, in the first clock signal line extend along the first direction, the sections, where the N connecting positions of the N shift register units are located, in the second clock signal line extend along the first direction, the sections, where the N connecting positions of the N shift register units are located, in the high-level signal line extend along the first direction, and the sections, where the N connecting positions of the N shift register units are located, in the low-level signal line extend along the first direction;

The plurality of shift register unit groups are arranged in a step shape, and the extending direction of the central connecting line of the plurality of shift register unit groups is the same as the extending direction of the first boundary.

2. A display panel as claimed in claim 1 characterized in that N is 2, 3 or 4.

3. The display panel according to claim 1, wherein the number of shift register cells in each of the shift register cell groups is the same.

4. The display panel according to claim 1, wherein the first direction and the extending direction are perpendicular to each other.

5. The display panel according to claim 1, wherein the shift register unit includes a plurality of transistors; the channel directions of the transistors in the plurality of shift register units are the same, and the transistors are connected in the same relation.

6. The display panel according to claim 5, wherein the plurality of transistors includes a first type transistor and a second type transistor;

the channel direction of the first type transistor is the same as the extension direction; the channel direction of the second-type transistor is a first direction, and the first direction is intersected with the extending direction;

The transistors in the plurality of shift register units, which are connected in the same relationship, are of the same type.

7. The display panel of claim 1, wherein the first border is curved and the second border is curved.

8. A display device characterized by comprising the display panel according to any one of claims 1 to 7.