CN110426900B - Array substrate, display panel and display device - Google Patents

Array substrate, display panel and display device Download PDF

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CN110426900B
CN110426900B CN201910721293.5A CN201910721293A CN110426900B CN 110426900 B CN110426900 B CN 110426900B CN 201910721293 A CN201910721293 A CN 201910721293A CN 110426900 B CN110426900 B CN 110426900B
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goa
row
array substrate
pixel circuits
pixel
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CN110426900A (en
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袁丽君
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The application discloses array substrate, display panel and display device relates to and shows technical field. Each GOA unit group included in the array substrate is positioned on one side of the pixel circuits, and the GOA unit group comprises at least two rows of GOA units. Because every GOA unit group includes two at least GOA units, compare in the correlation technique with a plurality of GOA units set up in one row, can effectively reduce the line number of the GOA unit in the array substrate, the width increase in the region that corresponding every row of GOA unit can occupy to can effectively reduce the required precision to the exposure machine, reduce array substrate's the manufacturing degree of difficulty, and then can effectively reduce the restriction of manufacturing process to display panel's resolution ratio.

Description

Array substrate, display panel and display device
Technical Field
The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
Background
The array substrate generally includes a plurality of pixel circuits arranged in an array on a substrate and a plurality of cascaded shift register units, which are also called gate driver on array (GOA) units. Each GOA unit is connected to a row of pixel circuits, and can provide gate driving signals to the row of pixel circuits, so that each pixel circuit drives the connected light emitting element to emit light.
In the related art, the plurality of cascaded GOA units may be arranged in a direction parallel to a column direction of the pixel circuits, and each GOA unit may be located at one side of a row of pixel circuits to which it is connected. In order to ensure that a plurality of GOA units can be effectively arranged on the substrate, the width of each GOA unit is less than or equal to the width of the pixel circuit. The width direction of the GOA unit and the width direction of the pixel circuit are parallel to the column direction of the pixel circuit.
With the improvement of the resolution of the display panel, the number of pixel circuits required to be arranged in a unit area in the array substrate is increased, so that the size of the pixel circuits is further reduced. However, the number of thin film transistors included in the GOA unit is large, which makes the size reduction difficult, thereby limiting the improvement of the resolution of the display panel.
Disclosure of Invention
The application provides an array substrate, display panel and display device, can solve the problem of correlation technique because the size reduction degree of difficulty of GOA unit is great, has restricted the promotion of display panel resolution ratio. The technical scheme is as follows:
in one aspect, an array substrate is provided, where the array substrate includes a plurality of pixel circuits arranged in an array, and at least one array substrate row driving GOA unit group;
each GOA unit group is positioned at one side of the pixel circuits and comprises at least two columns of GOA units, and the arrangement direction of the GOA units in each column is intersected with the row direction of the pixel circuits;
each of the GOA units is connected with at least one pixel circuit in a row of the pixel circuits.
Optionally, the array substrate includes one GOA unit group, and each GOA unit included in the one GOA unit group is connected to each pixel circuit in one row of the pixel circuits.
Optionally, the array substrate includes two GOA unit groups;
the two GOA unit groups are oppositely arranged on two sides of the pixel circuits.
Optionally, the number of the GOA units included in each GOA unit group is equal to the number of rows of the pixel circuits, and each GOA unit corresponds to one row of the pixel circuits;
and part of the pixel circuits in each row of the pixel circuits are connected with a corresponding GOA unit in one GOA unit group, and the rest of the pixel circuits are connected with a corresponding GOA unit in the other GOA unit group.
Optionally, the width of each GOA unit is greater than the width of the pixel circuit;
wherein the width direction of each GOA unit and the width direction of the pixel circuit are parallel to the arrangement direction.
Optionally, a width of each of the GOA units is twice a width of the pixel circuit, and each of the GOA unit groups includes four columns of the GOA units.
Optionally, an arrangement direction of the GOA units in each column is perpendicular to a row direction of the pixel circuits.
In another aspect, there is provided a display panel including: at least one array substrate as described in the above aspect.
Optionally, the display panel includes: a plurality of the array substrates that splice.
In still another aspect, there is provided a display device including: the display panel according to the above aspect.
The beneficial effect that technical scheme that this application provided brought includes at least:
the application provides an array substrate, display panel and display device, every GOA unit group that includes in this array substrate is located a plurality of pixel circuit one sides, and this GOA unit group is including two at least GOA units. Because every GOA unit group includes two at least GOA units, compare in the correlation technique with a plurality of GOA units set up in one row, can effectively reduce the line number of the GOA unit in the array substrate, the width increase in the region that corresponding every row of GOA unit can occupy to can effectively reduce the required precision to the exposure machine, reduce array substrate's the manufacturing degree of difficulty, and then can effectively reduce the restriction of manufacturing process to display panel's resolution ratio.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display device in the related art;
FIG. 2 is a schematic view of a structure of a TFT in the related art;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a GOA unit according to an embodiment of the present invention
Fig. 8 is a schematic structural diagram of another GOA unit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display device in the related art. Referring to fig. 1, the display device may include an array substrate 10, and at least one source driver Integrated Circuit (IC) 20, for example, 2 source driver ICs 20 are shown in fig. 1. The array substrate may include a plurality of pixel circuits 101 arranged in an array, and a plurality of cascaded GOA units 102.
As shown in fig. 1, the plurality of GOA cascaded units 102 may be disposed at one side of the plurality of pixel circuits 101, and the arrangement direction of the plurality of GOA units 102 may be perpendicular to the row direction of the pixel circuits 101. Each GOA cell 102 of the plurality of GOA cells 102 can be connected to a respective pixel circuit 101 of a row of pixel circuits 101 via a gate line for providing a gate drive signal to each pixel circuit 101 to which it is connected.
Each of the at least one source drive IC 20 may be connected to each of the pixel circuits 101 in at least one column of the pixel circuits 101 through a data line for supplying a data signal to each of the pixel circuits 101 to which it is connected. Each pixel circuit 101 can drive the light emitting element connected thereto to emit light under the drive of the gate drive signal and the data signal. It should be noted that, if the display device includes one source drive IC 20, the source drive IC 20 may be connected to each column of the pixel circuits 101.
It can also be seen from fig. 1Furthermore, each GOA cell 102 in the related art can be disposed on one side of the row of pixel circuits 101 to which it is connected, such that the width W of each GOA cell 102 1 And width W of pixel circuit 101 2 May be approximately equal. The width direction of each GOA unit 102 and the width direction of the pixel circuit 101 are perpendicular to the row direction of the pixel circuit 101.
In the related art, each GOA unit 102 may include at least one capacitor and a plurality of Thin Film Transistors (TFTs). Fig. 2 is a schematic structural view of a TFT in the related art. The TFT may include: a gate (gate, G), a source (S), a drain (D), and an active layer (ACT), wherein the active layer ACT may also be referred to as a channel. As can also be seen from fig. 2, at least one via a is further disposed on each of the source S and the drain D, and the source S and the drain D may be respectively connected to the active layer ACT through the via a.
Referring to fig. 2, a source S and a drain D of a TFT may be formed in the same layer, and a source/drain electrode line L may be further disposed on the source/drain layer of the TFT 1 And L 2 So that the TFT can be connected to other components in the GOA unit 102. As can be seen from fig. 2, the source S and the source/drain electrode line L 2 There is a gap H between 1 Drain D and source-drain electrode line L 1 There is a gap H between 1 Therefore, the source S and the source-drain electrode line L can be avoided 2 Contact, drain D and source-drain electrode line L 1 Contact, causing the TFT to short.
In the manufacturing process of the TFT, it is usually necessary to expose the material film layers forming the various levels (e.g., the active layer, the gate electrode, the source electrode, and the drain electrode) of the TFT by using an exposure machine. The precision of the exposure machine may be 1 micrometer (μm). Therefore, the exposure machine exposes the formed source/drain electrode lines L in an ideal state 1 And L 2 The line width of (A) can be at least 1 μm, the gap H 1 May be at least 1 μm, the width H of the active layer ACT 2 May be 3.5 μm, the width H of the gate G 3 May be 7.5 μm. Therefore, the exposure machine forms a TFT and a source/drain on the substrate under ideal conditionsThe width of the area required for the electrode lines is at least 8.5 μm. The width direction refers to a column direction of the pixel circuit, that is, an extending direction of the data line in the array substrate.
At present, the resolution of the display panel is higher, that is, the number of pixel units included per inch is higher, and accordingly, the width of each pixel unit is smaller, and the width of the pixel circuit included in each pixel unit is also smaller. For example, if the resolution of the display panel is 3000PPI (pixel density), i.e., 3000 pixel units per inch, the width of the pixel circuit in each pixel unit is 8.5 μm at the maximum.
Therefore, if the resolution of the display panel is 3000PPI, the width of each GOA unit in the array substrate should be less than or equal to 8.5 μm. However, since each GOA cell usually includes a plurality of TFTs and at least one capacitor, and at present, the width of the area required by the exposure machine to form a TFT on the substrate under ideal conditions is 7.5 μm, and in addition, the routing lines are required to connect the TFTs and the capacitor C in the GOA cell, the width of the area required to form a GOA cell on the substrate is usually greater than 8.5 μm. Therefore, for a high-resolution display panel, when the GOA unit is formed on the substrate in the array substrate, the requirement for the accuracy of the exposure machine is higher, which results in that the difficulty of forming the GOA unit on the substrate by using the current exposure machine is higher, and thus the resolution of the display panel cannot be effectively improved.
Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and referring to fig. 3, the array substrate may include a plurality of pixel circuits 01 arranged in an array, and at least one GOA unit group 02. For example, two GOA cell groups 02 are shown in fig. 3.
As can be seen from fig. 3, each GOA cell group 02 may be located at one side of a plurality of pixel circuits 01, and each GOA cell group 02 may include at least two columns of GOA cells 021, and an arrangement direction Y of each column of GOA cells 021 may intersect with a row direction X of the pixel circuit 01.
Wherein, each GOA cell 021 can be connected to at least one pixel circuit 01 in a row of pixel circuits 01. For example, each GOA cell 021 can be connected to a respective pixel circuit 01 in a row of pixel circuits 01.
In summary, embodiments of the present invention provide an array substrate, in which each of the plurality of GOA cell groups included in the array substrate is located at one side of the plurality of pixel circuits, and each of the plurality of GOA cell groups includes at least two rows of GOA cells. Because every GOA unit group includes two at least GOA units, set up a plurality of GOA units in one row in comparison with in the correlation technique, can effectively reduce the line number of GOA unit in the array substrate, the width increase in the region that corresponding every row of GOA unit can occupy to can effectively reduce the required precision to the exposure machine, reduce array substrate's the manufacturing degree of difficulty, and then can effectively reduce the restriction of manufacturing process to display panel's resolution ratio.
Optionally, the width of each GOA cell 021 can be greater than the width of the pixel circuit 01, for example, the width of each GOA cell 021 can be K times the width of the pixel circuit 01, and K is a positive integer greater than 1. Accordingly, each GOA cell 021 can be disposed on one side of at least two rows of pixel circuits 01. The width direction of each GOA cell 021 and the width direction of the pixel circuit 01 are both parallel to the arrangement direction of each row of GOA cells 021.
As an example, each GOA cell 021 can have twice the width of the pixel circuit 01. For example, the width of the pixel circuit 01 may be 8.5 μm, and the width of the GOA cell 021 may be 17 μm.
In the embodiment of the present invention, the array substrate may further include a substrate, and the plurality of pixel circuits 01 arranged in an array and the at least one GOA cell group 02 may be disposed on the substrate.
Each pixel circuit 01 may include at least one TFT, and at least one capacitor. The width of each pixel circuit 01 may be the width of the area occupied by it on the substrate base, that is, the width of the area occupied by the TFT included in the pixel circuit 01 on the substrate base.
It should be noted that, if the display panel to which the array substrate is applied is a Liquid Crystal Display (LCD) panel, each pixel circuit 01 in the array substrate may include a TFT and at least one capacitor. If the display panel to which the array substrate is applied is an organic light-emitting diode (OLED) display panel, each pixel circuit 01 in the array substrate may include at least two TFTs and at least one capacitor.
In the embodiment of the present invention, at least two rows of GOA cells 021 included in each GOA cell group 02 may also be arranged in an array, that is, a plurality of GOA cells 021 included in each GOA cell group 02 may be divided into multiple rows and multiple columns, and the number of GOA cells 021 included in each row of GOA cells 021 is equal to the number of columns of GOA cells 021 included in each GOA cell group 02.
The arrangement direction of the GOA cells 021 in each row can be perpendicular to the row direction of the pixel circuit 01, i.e. the row direction of the GOA cells 021 in each GOA cell group 02 can be parallel to the extending direction of the data lines in the array substrate. Accordingly, the row direction of the GOA cells 021 in each GOA cell group 02 can be parallel to the row direction of the pixel circuit 01, i.e., the row direction of the GOA cells 021 in each GOA cell group 02 can be parallel to the extending direction of the gate lines in the array substrate.
It should be noted that, in the embodiment of the present invention, in each GOA cell group 02, a plurality of GOA cells 021 included in each row of GOA cells 021 may be connected to a plurality of rows of adjacent pixel circuits 01. Accordingly, the plurality of GOA cells 021 in each row of GOA cells 021 may be sequentially cascaded, and the GOA cell 021 in the last column of GOA cells in each row may be connected to the GOA cell 021 in the first column of GOA cells 021 in the next row. This can ensure that the GOA cell group 02 can drive the pixel circuits 01 of each row by row.
As an alternative implementation, referring to fig. 4, the array substrate may include a group 02 of GOAs. Each of the GOA cells 021 included in the one GOA cell group 02 may be connected to each of the pixel circuits 01 in a row of the pixel circuits 01.
As another alternative implementation manner, as shown in fig. 3 and 5, the array substrate may include two GOA cell groups 02, and the two GOA cell groups 02 may be oppositely disposed at two sides of the plurality of pixel circuits 01.
In the embodiment of the present invention, each GOA cell 021 in the two GOA cell groups 02 may be connected to a part of pixel circuits 01 in a row of pixel circuits 01, or may be connected to each pixel circuit 01 in the row of pixel circuits 01.
Alternatively, the number of the GOA cells 021 included in each GOA cell group 02 may be equal to the number of rows of the pixel circuit 01, and each GOA cell 021 corresponds to one row of the pixel circuit 01. That is, the number of the GOA cells 021 included in the two GOA cell groups 02 may be 2 times the number of rows of the pixel circuit 01. Referring to fig. 3, a part of the pixel circuits 01 in each row of the pixel circuits 01 may be connected to a corresponding one of the GOA cells 021 of one of the GOA cell groups 02, and the remaining pixel circuits 01 may be connected to a corresponding one of the GOA cells 021 of the other of the GOA cell groups 02. The two GOA cells 021 connected to the same row of pixel circuits 01 can be located in the same row.
In the embodiment of the present invention, assuming that the left side of the array substrate shown in fig. 3 is used as a starting point, the first half row of pixel circuits 01 in each row of pixel circuits 01 may be connected to a corresponding one of the GOA cells 021 of the GOA cell group 02 located at the left side of the array substrate, and the second half row of pixel circuits 01 may be connected to a corresponding one of the GOA cells 021 of the GOA cell group 02 located at the right side of the array substrate.
For example, it is assumed that each row of pixel circuits 01 includes N pixel circuits 01, where N is a positive integer. If N is an even number, each GOA cell 021 in the two GOA cell groups 02 located at the left side of the array substrate may be connected to the first N/2 pixel circuits 01 in a row of pixel circuits 01, and each GOA cell 021 located at the right side of the array substrate may be connected to the last N/2 pixel circuits 01.
If N is an odd number, each GOA cell 021 in the two GOA cell groups 02 located at the left side of the array substrate may be connected to the first (N +1)/2 pixel circuits 01 in a row of pixel circuits 01, and each GOA cell 021 located at the right side of the array substrate may be connected to the last (N-1)/2 pixel circuits 01.
Alternatively, as shown in fig. 5, the number of GOA cells 021 included in each GOA cell group 02 may be less than the number of rows of the pixel circuit 01, and the total number of GOA cells 021 included in the two GOA cell groups 02 may be equal to the number of rows of the pixel circuit 01. Each GOA cell 021 included in each GOA cell group 02 corresponds to a row of pixel circuits 01, and each GOA cell 021 may be connected to each pixel circuit 01 in the corresponding row of pixel circuits 01.
For example, referring to fig. 5, each GOA cell 021 in one of two GOA cell groups 02 may be connected to each pixel circuit 01 in an even row of pixel circuits 01 in a plurality of rows of pixel circuits 01, and each GOA cell 021 in the other GOA cell group 02 may be connected to each pixel circuit 01 in an odd row of pixel circuits 01 in the plurality of rows of pixel circuits 01.
In the embodiment of the present invention, the arrangement of the GOA cell group 02 in the array substrate will be described by taking the example that the width of each GOA cell 021 is twice that of the pixel circuit 01, and taking the example that each GOA cell 021 is connected to each pixel circuit 01 in one row of the pixel circuits 01.
Since each GOA cell 021 has twice the width of the pixel circuit 01, each GOA cell 021 can be disposed on one side of at least two rows of pixel circuits 01. The GOA cell sets 02 may be arranged in an array, and a plurality of GOA cells 021 included in each row of GOA cells 021 may be connected to a plurality of rows of adjacent pixel circuits 01.
Referring to fig. 4, it is assumed that the array substrate includes one GOA cell group 02, and the GOA cell group 02 includes four rows of GOA cells 021, i.e., each row of GOA cells 021 includes four GOA cells 021 in each of the rows of GOA cells 021 included in the GOA cell group 02. Each GOA cell 021 can be connected to one row of pixel circuits 01, and the four GOA cells 021 included in each row can be connected to the adjacent four rows of pixel circuits 01, as shown in fig. 4.
For example, a first row of pixel circuits 01 in the array substrate may be connected to a GOA cell 021 in a first row and a first column in the GOA cell group 02, a second row of pixel circuits 01 may be connected to the GOA cell 021 in a first row and a second column, a third row of pixel circuits 01 may be connected to the GOA cell 021 in a first row and a third column, and a fourth row of pixel circuits 01 may be connected to the GOA cell 021 in a first row and a fourth column. By analogy, the last row of pixel circuits 01 in the array substrate can be connected to the GOA cells 021 in the fourth column of the last row of the GOA cell group 02.
Since each GOA cell 021 can be arranged at one side of 4 rows of pixel circuits 01, and the width of each GOA cell 021 is only equal to the width of two rows of pixel circuits 01, after the GOA cell group 02 is formed on the substrate, a larger space is arranged between two adjacent rows of GOA cells 021, thereby being convenient for wiring.
Alternatively, referring to fig. 6, the array substrate may include one GOA cell group 02, and the GOA cell group 02 may include two rows of GOA cells 021, that is, each row of GOA cells 021 of the plurality of rows of GOA cells 021 included in the GOA cell group 02 includes two GOA cells 021. Each GOA cell 021 can be connected to one row of pixel circuits 01, and the two GOA cells 021 included in each row can be connected to two adjacent rows of pixel circuits 01, as shown in fig. 6. That is, one row of the two rows of the GOA cells 021 can be connected to the odd row of the pixel circuits 01, and the other row of the GOA cells 021 can be connected to the even row of the pixel circuits 01.
Because the number of columns of the GOA units 021 included in each GOA unit group 02 is small, and only two columns of GOA units 021 are included, the length of an area occupied by the GOA unit group 02 on the substrate can be prevented from being too long, and the narrow-frame display panel can be conveniently realized. Wherein, the length direction is perpendicular to the row direction of the GOA cells 021 in the GOA cell group 02.
In the embodiment of the present invention, if the width of each GOA cell 021 is M times of the width of the pixel circuit 01, and M is a number greater than 1, in order to ensure that there is a sufficient wiring space between two adjacent rows of GOA cells 021, the number of columns of the GOA cells 021 included in each GOA cell group 02 may be set to be greater than or equal to M. In addition, the number of columns of the GOA cells 021 included in each group of GOA cells 02 can be flexibly set according to the number of each GOA cell group 02 and the connection manner between the GOA cells 021 and the pixel circuit 01.
For example, if the array substrate includes two GOA cell groups 02 and each GOA cell 021 is connected to a row of pixel circuits 01, the number of columns of the GOA cells 021 included in each GOA cell group 02 is an integer greater than or equal to M. For example, if M is equal to 1.5 or equal to 2, the number of columns of GOA cells included in each GOA cell group 02 may be equal to 2.
If the array substrate comprises two groups of GOA units 02, and each GOA unit 021 is connected to only a part of the pixel circuits 01 in one row of pixel circuits 01, that is, each row of pixel circuits 01 is connected to the GOA units 021 of two different groups of GOA units 02; or if the array substrate includes one GOA cell group 02 and each GOA cell 021 is connected to one row of pixel circuits 01, the number of columns of the GOA cells 021 included in each GOA cell group 02 is an integer greater than M, for example, if M is equal to 2, the number of columns of the GOA cells 021 included in each GOA cell group 02 may be equal to 3 or 4.
Fig. 7 is a schematic structural diagram of a GOA unit according to an embodiment of the present invention. Fig. 8 is a schematic structural diagram of another GOA unit according to an embodiment of the present invention. Referring to fig. 7 and 8, each GOA cell 021 in the array substrate provided by the embodiments of the present invention may include 10 TFTs and two capacitors C. The 10 TFTs are M1 to M10, respectively, and the two capacitors are C1 and C2, respectively.
As shown in fig. 7, each GOA unit 102 may have an input terminal i (n), an output terminal g (n), a first reset terminal T _ RST, a second reset terminal RST, a first control signal terminal CN, a second control signal terminal CNB, a first clock signal terminal CLK, a second clock signal terminal CLKB, a first power supply terminal VGH, and a second power supply terminal VGL. Referring to fig. 8, for the first stage GOA unit 102, its input terminal may be the start signal terminal STV.
The potential of the first control signal provided by the first control signal terminal CN may be a first potential, and the potential of the second control signal provided by the second control signal terminal CNB may be a second potential. The potential of the voltage signal supplied from the first power source terminal VGH may be a first potential, and the potential of the voltage signal supplied from the second power source terminal VGL may be a second potential. The timing of the first timing signal provided by the first clock signal terminal CLK and the timing of the second timing signal provided by the second clock signal terminal CLKB may be complementary. The first potential may be a high potential relative to the second potential.
Alternatively, if the GOA cell 021 comprises 10 TFTs and two capacitors, the length of the GOA cell can be 725 μm. The length direction of the GOA units is perpendicular to the row direction of the GOA units 021 in the GOA unit group 02, i.e. parallel to the extending direction of the gate lines in the array substrate.
It should be noted that, in the embodiment of the present invention, the array substrate may include a display area and a non-display area. The plurality of pixel circuits 01 further include a plurality of dummy pixel circuits, and both the dummy pixel circuits and the GOA cell group 02 in the array substrate may be located in the non-display area. The pixel circuit 011 other than the dummy pixel circuit may be located in the display region. Each row of the dummy pixel circuits may be connected to one or more GOA cells 021, and the GOA cells connected to the dummy pixel circuits may be referred to as the dummy GOA cells 021.
In summary, embodiments of the present invention provide an array substrate, in which each of the plurality of GOA cell groups included in the array substrate is located at one side of the plurality of pixel circuits, and each of the plurality of GOA cell groups includes at least two rows of GOA cells. Because every GOA unit group includes two at least GOA units, compare in the correlation technique with a plurality of GOA units set up in one row, can effectively reduce the line number of the GOA unit in the array substrate, the width increase in the region that corresponding every row of GOA unit can occupy to can effectively reduce the required precision to the exposure machine, reduce array substrate's the manufacturing degree of difficulty, and then can effectively reduce the restriction of manufacturing process to display panel's resolution ratio.
An embodiment of the present invention further provides a display panel, where the display panel may include: at least one array substrate as provided in the above embodiments. For example, the display panel may include an array substrate as provided in the above embodiments. Alternatively, the display panel may include a plurality (e.g., four) of array substrates provided as in the above embodiments, which are tiled. That is, as shown in fig. 9, the display panel may be formed by splicing a plurality of sub-display panels 00, and each sub-display panel 00 may include an array substrate provided in the above embodiment.
For example, the plurality of tiled array substrates may be located in the same row or the same column, or as shown in fig. 9, the plurality of tiled array substrates may be arranged in an array, that is, the plurality of tiled array substrates may be arranged in multiple rows and columns.
In the embodiment of the present invention, if the display panel includes a plurality of tiled array substrates, that is, the display panel is formed by tiling a plurality of sub-display panels, the resolution of the display panel may be equal to the sum of the resolutions of the tiled sub-display panels.
For example, it is assumed that the display panel is formed by splicing 4 sub-display panels with the same resolution, and each sub-display panel includes 7680 × 4320 pixel units (piexl, PX), that is, the array substrate in the sub-display panel has 7680 columns of 4320 rows of pixel circuits, and the resolution of the sub-display panel is 8K 4K. The display panel may comprise 15360 × 8640 pixel cells, i.e. the array substrate in the display panel has 15360 columns, 8640 rows of pixel circuits, and the resolution of the display panel is 16K 8K. Wherein 1K may refer to 1024.
In the embodiment of the present invention, if the display panel includes 4 display sub-panels arranged in 2 rows and 2 columns. The array substrate in each sub-display panel may include only one group 02 of GOAs. As shown in fig. 9, each of the GOA unit groups 02 may be disposed on a side of the array substrate away from the array substrate spliced thereto, and the arrangement and connection of the GOA units 021 in each of the GOA unit groups 02 are the same.
For example, referring to fig. 9, the group of GOA cells 02 in the left two sub-display panels 00 may be axisymmetrically arranged with respect to the first axis P parallel to the data lines in the display panel with respect to the group of GOA cells 02 in the right two sub-display panels 00. The GOA cell groups 02 in the two sub-display panels 00 on the upper side may be arranged to be axisymmetrical with the GOA cell groups 02 in the two sub-display panels 00 on the lower side, with the second axis Q of the display panel parallel to the gate lines.
Optionally, in the embodiment of the present invention, the working timings of the two symmetric GOA units 021 may be the same. That is, the two symmetric GOA cells 021 can output the gate driving signals at the same time. The symmetrical arrangement may mean symmetrical arrangement with the first axis as the axis P, or symmetrical arrangement with the second axis Q as the axis.
For example, referring to fig. 9, the tiled display panel includes 4 array substrates, and the GOA cell group 02 of each of the two array substrates located at the upper side of the display panel (i.e., the first row of the display panel) may drive each row of pixel cells 011 from the last row of pixel cells 011 to the first row of pixel cells 011 row by row. The GOA cell group 02 of each of the two array substrates located at the lower side of the display panel (i.e., the second row of the display panel) can drive each row of pixel cells 011 from the first row of pixel cells 011 row by row until the last row of pixel cells 011. Thus, each row of pixel units 011 included in the display panel can be lit up row by row from the middle to both ends.
Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 10, the display panel may include a plurality of pixel units 011 arranged in an array. Each pixel unit 011 may include a pixel circuit and a light emitting element connected to the pixel circuit.
If the display panel is an LCD panel, each light emitting element may include: the liquid crystal display device comprises a pixel electrode, a common electrode and liquid crystal molecules positioned between the pixel electrode and the common electrode. Correspondingly, the LCD panel can also comprise a color film substrate and a liquid crystal layer positioned between the array substrate and the color film substrate. The pixel electrode may be disposed in the array substrate, and the common electrode may be disposed in the color filter substrate.
If the display panel is an OLED panel, each light emitting element may include a cathode, an anode, and a light emitting layer between the cathode and the anode. The cathode, the anode and the light emitting layer may be disposed in the array substrate.
It should be noted that, in the embodiment of the present invention, referring to fig. 10, a plurality of rows of dummy (dummy) pixel units (DPX) may be further included in the plurality of rows of pixel units 011 included in the display panel, the dummy pixel units may be located in a non-display region of the display panel, and the pixel units 011 other than the dummy pixel units are located in a display region of the display panel. The pixel circuit included in the dummy pixel unit is a dummy pixel circuit. For example, referring to fig. 10, the first 4 rows of pixel cells 011 and the last 4 rows of pixel cells 011 in the display panel can be dummy pixel cells, and at least one dummy pixel cell 011 in each row of dummy pixel cells can be connected to one GOA cell 021.
An embodiment of the present invention further provides a display device, where the display device may include: the display panel provided by the embodiment is included. For example, a display panel as shown in fig. 9 or fig. 10 may be included.
In an embodiment of the present invention, the display device may further include a driving device, which may be connected to each column of the pixel circuits in the array substrate in the display panel through a data line, for providing a data signal to each pixel circuit.
Alternatively, the display device may be an LCD display device or an OLED display device. The display device may be: the display device includes any product or component having a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
The above description is only exemplary of the application and should not be taken as limiting the application, and any modifications, equivalents, improvements and the like that are made within the spirit and principle of the application should be included in the protection scope of the application.

Claims (9)

1. The array substrate is characterized by comprising a plurality of pixel circuits arranged in an array manner, and at least one array substrate row driving GOA unit group;
each GOA unit group is positioned at one side of the pixel circuits and comprises at least two columns of GOA units arranged in an array manner, the arrangement direction of each column of GOA units is intersected with the row direction of the pixel circuits, and the arrangement direction of each row of GOA units is parallel to the row direction of the pixel circuits;
the GOA units in each row are sequentially cascaded, and the GOA unit in the last column in each row of GOA units is connected with the GOA unit in the first column in the next row of GOA units;
each GOA unit is connected with at least one pixel circuit in a row of the pixel circuits, the width of each GOA unit is larger than that of the pixel circuits, and the width direction of each GOA unit and the width direction of each pixel circuit are parallel to the arrangement direction of each row of the GOA units.
2. The array substrate of claim 1, wherein the array substrate comprises one group of the GOA units, and each GOA unit comprised by one group of the GOA units is connected with each of the pixel circuits in one row of the pixel circuits.
3. The array substrate according to claim 1, wherein the array substrate comprises two GOA unit groups;
the two GOA unit groups are oppositely arranged on two sides of the pixel circuits.
4. The array substrate according to claim 3, wherein each group of the GOA units comprises the same number of GOA units as the number of rows of the pixel circuits, and each GOA unit corresponds to one row of the pixel circuits;
and part of the pixel circuits in each row of the pixel circuits are connected with a corresponding GOA unit in one GOA unit group, and the rest of the pixel circuits are connected with a corresponding GOA unit in the other GOA unit group.
5. The array substrate according to any one of claims 1 to 4, wherein each GOA unit has a width twice that of the pixel circuit, and four columns of the GOA units are included in each GOA unit group.
6. The array substrate according to any one of claims 1 to 4, wherein the arrangement direction of the GOA units in each column is perpendicular to the row direction of the pixel circuits.
7. A display panel, comprising: at least one array substrate according to any one of claims 1 to 6.
8. The display panel according to claim 7, characterized in that the display panel comprises: a plurality of the array substrates that splice.
9. A display device, characterized in that the display device comprises: a display panel as claimed in claim 7 or 8.
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