CN111243482A

CN111243482A - Shift register unit, shift register, display panel and display device

Info

Publication number: CN111243482A
Application number: CN202010101577.7A
Authority: CN
Inventors: 吴昊; 吴薇
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-02-19
Filing date: 2020-02-19
Publication date: 2020-06-05
Anticipated expiration: 2040-02-19
Also published as: CN111243482B

Abstract

The invention discloses a shift register unit, a shift register, a display panel and a display device, wherein the shift register unit comprises a shift module, an enabling module, a signal conversion circuit and at least one clock signal input end; wherein at least the shifting module comprises a first inverter; the first inverter includes a first transistor of a P-type and a second transistor of an N-type; a first electrode of the first transistor receives a high-level signal; a second electrode of the second transistor receives a low level signal; the grid electrode of the first transistor and the grid electrode of the second transistor are input ends of the first inverter; the second electrode of the first transistor and the first electrode of the second transistor are output ends of the first inverter; the signal conversion circuit is electrically connected to the clock signal input terminal, the gate of the first transistor, and the gate of the second transistor, respectively, to raise the potential of the clock signal input to the gate of the first transistor and/or to lower the potential of the clock signal input to the gate of the second transistor.

Description

Shift register unit, shift register, display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a shift register unit, a shift register, a display panel and a display device.

Background

The display panel comprises a display area and a non-display area surrounding the display area, wherein the display area is provided with a plurality of data lines and a plurality of scanning lines, and the scanning lines and the data lines are crossed to define corresponding pixels. When the display panel displays a frame of picture, corresponding scanning signals are sequentially input to each scanning line of the display panel, so that data signals can be written into corresponding pixels of the display area through the corresponding data lines, and the scanning signals input to the pixels through the scanning lines are provided by the gate driving circuit.

The gate driving circuit generally includes a plurality of cascaded shift register units, each shift register unit includes a plurality of clock signal input terminals, and the shift register units output corresponding scan signals under the control of clock signals input by the clock signal input terminals and shift signals output by the shift register units of a previous stage. The clock signal of the shift register unit is transmitted to the shift register unit through the corresponding clock signal line. When the number of clock signal lines is large, the frame area of the display panel is increased. In the prior art, by arranging an inverter in a shift register unit, a clock signal transmitted by a clock signal line can be converted into a clock signal opposite to the clock signal transmitted by the clock signal line when passing through the inverter, and at this time, a clock signal line required by the opposite clock signal does not need to be arranged, so that the number of clock signal output pins and clock signal lines is reduced.

However, when the clock signal line is used to transmit the clock signal, the clock signal transmitted to the shift register unit is delayed to a certain extent, so that a through current is generated in the inverter when the clock signal passes through the inverter, thereby increasing power consumption and damaging the inverter.

Disclosure of Invention

The invention provides a shift register unit, a shift register, a display panel and a display device, which are used for reducing the time of through current in an inverter so as to reduce the power consumption of the shift register unit.

In a first aspect, an embodiment of the present invention provides a shift register unit, including: a shift module and an enable module;

the shift module is used for receiving and latching a shift signal;

the enabling module is electrically connected with the shifting module; the enabling module is used for generating a gate driving signal according to the shifting signal;

the shifting module comprises at least a first inverter; the first inverter includes a first transistor and a second transistor; the first transistor is a P-type transistor, and the second transistor is an N-type transistor; a first electrode of the first transistor is electrically connected with a high-level signal, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor; a second electrode of the second transistor is electrically connected to a low level signal; the grid electrode of the first transistor and the grid electrode of the second transistor are input ends of the first inverter; a second electrode of the first transistor and a first electrode of the second transistor are output ends of the first inverter;

the shift register unit also comprises a signal conversion circuit and at least one clock signal input end;

the clock signal input ends are used for receiving clock signals, and the clock signals received by different clock signal input ends are different;

the signal conversion circuit is electrically connected with the clock signal input end, the grid electrode of the first transistor and the grid electrode of the second transistor respectively; the signal conversion circuit is configured to raise a potential of the clock signal input to the gate of the first transistor and/or to lower a potential of the clock signal input to the gate of the second transistor.

In a second aspect, an embodiment of the present invention further provides a shift register, including the shift register unit.

In a third aspect, an embodiment of the present invention further provides a display panel, including the shift register.

In a fourth aspect, an embodiment of the present invention further provides a display device, including the display panel.

According to the technical scheme of the embodiment of the invention, the signal conversion circuit is arranged between the first inverter and the clock signal input end of the shift register unit, and can increase the clock signal input to the grid electrode of the first transistor and/or reduce the clock signal of the grid electrode of the second transistor so as to narrow the voltage range of the simultaneous conduction of the first transistor and the second transistor, thereby reducing the power consumption of the through current generated by the simultaneous conduction of the first transistor and the second transistor, weakening the influence of the through current on the performance of the inverter, further being beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

Drawings

FIG. 1 is a schematic diagram of an inverter;

FIG. 2 is a diagram illustrating a shift register unit according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

fig. 4 is a schematic structural diagram of a signal conversion circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a signal conversion circuit according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of another signal conversion circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another signal conversion circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a signal conversion circuit according to another embodiment of the present invention;

fig. 9 is a schematic structural diagram of another signal conversion circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another signal conversion circuit according to an embodiment of the present invention;

fig. 11 is a driving timing chart of a signal conversion circuit corresponding to fig. 10;

FIG. 12 is a schematic diagram of a shift register unit according to an embodiment of the present invention;

FIG. 13 is a timing diagram of a shift register unit corresponding to FIG. 12;

FIG. 14 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

FIG. 15 is a schematic circuit diagram of a shift register unit according to another embodiment of the present invention;

fig. 16 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic diagram of an inverter. As shown in fig. 1, inverter 001 includes a transistor N01 of N type and a transistor P01 of P type. Wherein the gate of the N-type transistor N01 and the gate of the P-type transistor P01 are both the input terminal I01 of the inverter 001, the first electrode of the N-type transistor N01 and the second electrode of the P-type transistor P01 are both the output terminals of the inverter 001, and the first electrode of the P-type transistor P01 receives a high level signal and the second electrode of the N-type transistor N01 receives a low level signal. When the gate of the N-type transistor N01 is a high-level signal, the first electrode of the N-type transistor N01 is connected to the second electrode thereof; when the gate of the P-type transistor P01 is a low signal, the first electrode of the P-type transistor P01 is connected to the second electrode thereof; therefore, when the input terminal I01 of the inverter 001 inputs a low level signal, i.e. the gate of the P-type transistor P01 and the gate of the N-type transistor N01 are both low level signals, the first electrode of the P-type transistor P01 is turned on, so that the high level signal of the first electrode of the P-type transistor P01 is transmitted to the second electrode of the P-type transistor P01, i.e. the output terminal O01 of the inverter 001 outputs a high level signal; when the input I01 of the inverter 001 inputs a high level signal, the gate of the P-type transistor P01 and the gate of the N-type transistor N01 are both high level signals, and the first electrode of the N-type transistor N01 is connected to the second electrode thereof, so that the low level signal of the second electrode of the N-type transistor N01 is transmitted to the first electrode of the N-type transistor N01, i.e., the output O01 of the inverter 001 outputs a low level signal. Thus, when a high level signal is input to the input end of the inverter 001, a low level signal is output from the output end of the inverter 001; when a low level signal is input to the input terminal of the inverter 001, a high level signal is output from the output terminal of the inverter 001.

An inverter 001 is generally provided in each shift register cell of the shift register of the display panel, and an input terminal I01 of the inverter 001 receives a clock signal transmitted through a clock signal line and can output a signal opposite to the clock signal transmitted through the clock signal line. Illustratively, the clock signal transmitted to the input terminal I01 of the inverter 001 in the shift register cell may be varied between-7V and 8V to satisfy the turn-on requirements of the N-type transistor N01 and the P-type transistor P01 in the inverter 001, so that the inverter 001 can output a signal opposite to the clock signal.

However, when the clock signal transmitted to the input terminal I01 of the inverter 001 in the shift register cell may vary between-7V to 8V, the N-type transistor N01 of the inverter 001 may be turned on when the clock signal received at the input terminal I01 of the inverter 001 is-5.5V to 8V, and the P-type transistor P01 of the inverter 001 may be turned on when the clock signal received at the input terminal I01 of the inverter 001 is-7V to 6.5V. Thus, when the clock signal varies between-5.5V to 6.5V, the N-type transistor N01 and the P-type transistor P01 of the inverter 001 are turned on simultaneously, so that a loop is formed between the high level signal received by the first electrode of the P-type transistor P01 and the low level signal received by the second electrode of the N-type transistor N01, thereby generating a through current inside the inverter 001, affecting the performance of the inverter 001, and generating unnecessary power consumption, further affecting the display performance of the display panel, and improving the power consumption of the display panel.

In order to solve the above technical problem, an embodiment of the present invention provides a shift register unit, where the shift register unit includes a shift module and an enable module; the shift module is used for receiving and latching a shift signal; the enabling module is electrically connected with the shifting module and used for generating a grid driving signal according to the shifting signal. Wherein at least the shifting module comprises a first inverter; the first inverter includes a first transistor and a second transistor; the first transistor is a P-type transistor, the second transistor is an N-type transistor, a first electrode of the first transistor is electrically connected with a high level signal, a second electrode of the first transistor is electrically connected with a first electrode of the second transistor, and a second electrode of the second transistor is electrically connected with a low level signal; the grid electrode of the first transistor and the grid electrode of the second transistor are input ends of the first inverter; the second electrode of the first transistor and the first electrode of the second transistor are output ends of the first inverter; the shift register unit also comprises a signal conversion circuit and at least one clock signal input end; the clock signal input end is used for receiving clock signals, and the clock signals received by different clock signal input ends are different; the signal conversion circuit is respectively and electrically connected with the clock signal input end, the grid electrode of the first transistor and the grid electrode of the second transistor; the signal conversion circuit is used for raising the potential of a clock signal input to the gate of the first transistor and/or for lowering the potential of a clock signal input to the gate of the second transistor.

By adopting the technical scheme, the signal conversion circuit is arranged between the first phase inverter and the clock signal input end of the shift register unit and can increase the clock signal input to the grid electrode of the first transistor and/or reduce the clock signal of the grid electrode of the second transistor so as to narrow the voltage range of the simultaneous conduction of the first transistor and the second transistor, thereby reducing the power consumption of the through current generated by the simultaneous conduction of the first transistor and the second transistor and weakening the influence of the through current on the performance of the phase inverter, further being beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

The above is the core idea of the present invention, and based on the embodiments of the present invention, a person skilled in the art can obtain all other embodiments without creative efforts, which belong to the protection scope of the present invention. The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

In the embodiment of the invention, the shift register unit at least comprises a shift module and an enable module, and at least the shift module comprises a first inverter; meanwhile, on the premise that the enable module can realize the corresponding function, the enable module may also include a first inverter, which is not specifically limited in the embodiment of the present invention. For convenience of description, the shift module according to the embodiment of the present invention includes the first inverter.

Fig. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention. As shown in fig. 2, the shift register unit 100 includes a signal conversion circuit 30, a shift module 10, an enable module 20, and at least one clock signal input terminal (CKV 1). Each clock signal input terminal (CKV1) receives a different clock signal to enable the shift module to receive and latch the shift signal and enable the enable module to generate the gate driving signal according to the shift signal.

The shift module 10 includes a first inverter 11, the first inverter 11 including a first transistor M1 of P-type and a second transistor M2 of N-type; a first electrode of the first transistor M1 receives the high level signal VGH, a second electrode of the second transistor M2 receives the low level signal VGL, a gate of the first transistor M1 and a gate of the second transistor M2 are both input ends of the first inverter 11, and a second electrode of the first transistor M1 and a first electrode of the second transistor M2 are both output ends of the first inverter 11. Thus, when the gate potential Vg1 of the first transistor M1 is less than VGH + Vth1, the first electrode of the first transistor M1 is conductive to the second electrode thereof, and the output end of the first inverter 11 can output a high-level signal VGH; when the gate potential Vg2 of the gate potential of the second transistor M2 > VGL + Vth2, the first electrode of the second transistor M2 is turned on with the second electrode thereof, and the output terminal of the first inverter 11 can output the low level signal VGL. Where Vth1 is the threshold voltage of the first transistor M1, and Vth2 is the threshold voltage of the second transistor M2.

When the value range of the clock signal CK1 inputted from the clock signal input terminal CKV1 is a < CK1< b, a is not less than VGL + Vth2, and b is not less than VGH + Vth1, if the clock signal CK1 of the clock signal input terminal CKV1 is directly inputted to the gate of the first transistor M1 and the gate of the second transistor M2, the clock signal in the range of [ a, VGH + Vth1] can satisfy the on condition of the first transistor M1, and the clock signal in the range of [ VGL + Vth2, b ] can satisfy the on condition of the second transistor M2. When VGL + Vth2< VGH + Vth1, the clock signal CK1 inputted from the clock signal input terminal CKV1 can turn on the first transistor M1 and the second transistor M2 simultaneously, which will generate a through current through the first transistor M1 and the second transistor M2.

The signal conversion circuit 30 is provided between the clock signal input terminal CKV1 and the gate of the first transistor M1 and the gate of the second transistor M2, and the signal conversion circuit 30 is capable of raising the potential of the clock signal input to the gate of the first transistor M1 and/or capable of lowering the potential of the clock signal input to the gate of the second transistor M2. That is, when the signal conversion circuit 30 raises the potential of the clock signal input to the gate of the first transistor M1 by Δ V1, the clock signal CK1 with the clock signal input terminal CKV1 is input to the gate of the first transistor M1 through the signal conversion circuit 30 and becomes CK1+ Δ V1, and at this time, the range of the clock signal CK1 that turns on the first transistor M1 is [ a, VGH + Vth1- Δ V1], so that the range of the clock signal CK1 that turns on the first transistor M1 is narrowed; when the signal conversion circuit 30 lowers the potential of the clock signal inputted to the gate of the second transistor M2 by Δ V2, the clock signal CK1 inputted to the clock signal input terminal CKV1 is inputted to the gate of the second transistor M2 through the signal conversion circuit 30 and then becomes CK1- Δ V2, and at this time, the range of the clock signal for turning on the second transistor M2 is [ VGL + Vth2+ Δ V2, b ], so that the range of the clock signal CK1 for turning on the second transistor M2 is narrowed. Thus, the range of the clock signal CK1 for turning on the first transistor M1 and/or the second transistor M2 is narrowed, which is beneficial to reducing the time for generating the through current, thereby reducing the power consumption caused by the through current, further improving the performance of the shift register unit 100, reducing the power consumption of the display panel comprising the shift register unit 100, and improving the display effect of the display panel.

It should be noted that Δ V1 and Δ V2 may be the same or different, and this is not particularly limited in the embodiment of the present invention. In addition, fig. 2 is a diagram illustrating an embodiment of the present invention, and fig. 2 illustrates that the shift register unit 100 includes only one clock signal input terminal CKV 1; the shift register unit 100 may further include two or more clock signal input terminals in the embodiment of the present invention.

For example, fig. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. The same points in fig. 3 and fig. 2 are not repeated herein, and only the differences between fig. 3 and fig. 2 will be exemplarily described here. As shown in FIG. 3, the shift register cell 100 includes two clock signal inputs CKV1 and CKV 2; the shift register unit 100 further includes a shift signal input terminal IN, a shift signal output terminal Next, and a gate driving signal output terminal Gout. The clock signal received by the clock signal input terminal CKV1 is input into the shift module 10, and is also input into the first inverter of the shift module 10 through the signal conversion circuit 30, so that the shift module 10 can latch the shift signal at the shift signal input terminal IN and can provide the shift signal to the Next stage of shift register unit through the shift signal output terminal Next; the clock signal provided by the clock signal input terminal CKV2 is input into the enable module 20, so that the enable module 20 can output a corresponding gate driving signal through the gate driving signal output terminal Gout after performing logic operation according to the clock signal provided by the clock signal input terminal CKV2 and the signal output by the shift module 10.

For convenience of description, the functions and structures of the signal conversion circuit according to the embodiment of the present invention will be described by taking the shift register unit shown in fig. 3 as an example.

Optionally, the signal conversion circuit may include at least one first diode and at least one second diode; the first diodes are sequentially connected in series, the anodes of the first diodes are electrically connected with the grid electrodes of the first transistors of the first phase inverters, and the cathodes of the first diodes are electrically connected with the clock signal input end; the second diodes are sequentially connected in series, the anodes of the second diodes are electrically connected with the grid electrodes of the second transistors, and the cathodes of the second diodes are electrically connected with the clock signal input end.

For example, fig. 4 is a schematic structural diagram of a signal conversion circuit according to an embodiment of the present invention. As shown in fig. 4, the signal conversion circuit 30 includes a first diode D1 and a second diode D2; an anode of the first diode D1 is electrically connected to a gate of the first transistor M1 of the first inverter 11, and a cathode of the first diode D1 is electrically connected to the clock signal input terminal CKV 1; an anode of the second diode D2 is electrically connected to the clock signal input terminal CKV1, and a cathode of the second diode D2 is electrically connected to the gate of the second transistor M2. Since the diode has a diode voltage Δ Vd drop and the diode has a forward conduction characteristic, the anode potential of the first diode D1 should be higher than the cathode potential of the first diode D1 by Δ Vd1, and the anode potential of the second diode D2 should be higher than the cathode potential of the second diode D2 by Δ Vd 2. That is, when the first diode D1 is turned on, if the clock signal at the clock signal input terminal CKV1 electrically connected to the cathode of the first diode D1 is CK1, the gate potential of the first transistor M1 electrically connected to the anode of the first diode D1 is CK1+ Δ Vd1, and the signal input to the gate of the first transistor M1 is increased by Δ Vd1 compared to the case where the clock signal CK1 at the clock signal input terminal CKV1 is directly input to the gate of the first transistor M1; accordingly, when the second diode D2 is turned on, if the clock signal at the clock signal input terminal CKV1 electrically connected to the anode of the second diode D2 is CK1, the gate potential of the second transistor M2 electrically connected to the cathode of the second diode D2 is CK1 to Δ Vd2, and the signal input to the gate of the second transistor M2 is decreased by Δ Vd2 compared to the case where the clock signal CK1 at the clock signal input terminal CKV1 is directly input to the gate of the second transistor M2. Thus, when the clock signal CK1 of the clock signal input terminal CKV1 has a value range of [ a, b ], the threshold voltage of the first transistor M1 is Vth1, and the threshold voltage of the second transistor M2 is vtari 2, when the clock signal CK1 changes within the range of [ a, VGH + Vth1- Δ Vd1], the first transistor M1 is turned on, when the clock signal CK1 changes within the range of [ VGL + Vth2+ Δ Vd2, b ], the second transistor M2 is turned on, i.e. the range of the clock signal CK1 turning on the first transistor M1 and the second transistor M2 is narrowed, therefore, the range of the clock signal CK1 for simultaneously turning on the first transistor M1 and the second transistor M2 can be narrowed, which is beneficial to reducing the time for simultaneously turning on the first transistor M1 and the second transistor M2, reducing the power consumption caused by the through current generated by simultaneously turning on the first transistor M1 and the second transistor M2, and further improving the performance of the shift register unit.

The diode voltage drop Δ Vd1 of the first diode D1 and the diode voltage drop Δ Vd2 of the second diode D2 may be the same or different, and the embodiment of the invention is not limited in this respect. Take the example that the diode drop of the first diode D1 is the same as the diode drop of the second diode D2. For example, the tube voltage drop Vd of the first diode D1 and the second diode D2 may be 1.5V, the threshold voltage Vth1 of the first transistor M1 may be-1.5V, the threshold voltage Vth2 of the second transistor M2 may be 1.5V, the high level signal VGH may be 8V, the low level signal VGL may be-7V, and the clock signal CK1 inputted from the clock signal input terminal CKV1 varies within a range of [ -7V, 8V ]. At this time, the gate potential of the first transistor M1 is turned on when it is in the range of [ -7V, 6.5V ], that is, the first transistor M1 is turned on when the clock signal CK1 inputted from the clock signal input terminal CKV1 is in the range of [ -7V, 5V ]; the gate potential of the second transistor M2 is turned on when it is in the range of [ -5.5V, 8V ], that is, the second transistor M2 is turned on when the clock signal CK1 inputted from the clock signal input terminal CKV1 is in the range of [ -4V, 8V ]. Thus, in the prior art, when the clock signal from the clock signal input terminal CKV1 is directly inputted to the gate of the first transistor M1 and the gate of the second transistor M2, the range of the clock signal CK1 in which the first transistor M1 and the second transistor M2 are simultaneously turned on is [ -5.5V, 6.5V ], the range of the clock signal CK1 that enables the first transistor M1 and the second transistor M2 to be turned on simultaneously can be reduced to [ -4V, 5V ], when the clock signal CK1 is between-7V and-4V, the first transistor M1 is turned on, the second transistor M1 is turned on between 5V and 8V, and the first transistor M1 and the second transistor M2 are turned on simultaneously only between-4V and 5V, which reduces the range of clock signals for turning on the first transistor M1 and the second transistor M2 simultaneously and reduces the time for generating the through current compared to the prior art.

It should be noted that fig. 4 is a diagram illustrating an embodiment of the present invention, and fig. 4 illustrates only an example, where the signal conversion circuit 30 includes a first diode D1 and a second diode D2; in addition, the signal conversion circuit 30 may further include two or more first diodes and/or two or more second diodes to further narrow the range of the clock signal CK1 for simultaneously turning on the first transistor M1 and the second transistor M2. The present embodiment does not specifically limit the number of the first diode and the second diode in the signal conversion circuit on the premise that the reduction of the range of the clock signal CK1 that simultaneously turns on the first transistor M1 and the second transistor M2 can be achieved.

Optionally, fig. 5 is a schematic structural diagram of another signal conversion circuit provided in the embodiment of the present invention. As shown in fig. 5, the signal conversion circuit 30 includes a first resistor R1 and a second resistor R2; a first end of the first resistor R1 is electrically connected to the clock signal input terminal CKV1, and a second end of the first resistor R1 is electrically connected to the gate of the first transistor M1; a first end of the second resistor R2 is electrically connected to the clock signal input terminal CKV1, and a second end of the second resistor R2 is electrically connected to the gate of the second transistor M2; the threshold voltage of the first transistor M1 is Vth1, the threshold voltage of the second transistor M2 is Vth2, the divided voltage value of the first resistor R1 is V1, and the divided voltage value of the second resistor R2 is V2; wherein V1 > | Vth1| and V2 > Vth 2.

Specifically, the clock signal CK1 inputted from the clock signal input terminal CKV1 is divided by the first resistor R1 to be inputted to the gate of the first transistor M1, and is divided by the second resistor R2 to be inputted to the second transistor M2. Since the voltage division value of the first resistor R1 is V1, the clock signal CK1 at the clock signal input terminal CKV1 approaches V1 toward 0V through the first resistor R1, when the clock signal CK1 at the clock signal input terminal CKV1 changes in the range of [ VGL, VGH ] and VGL <0V, VGH >0V, the clock signal CK1 at the clock signal input terminal CKV1 is input to the gate of the first transistor M1 through the first resistor R1, so that the gate potential of the first transistor M1 changes in the range of [ VGL + V1, VGH-V1 ]; similarly, the clock signal CK1 at the clock signal input terminal CKV1 is input to the gate of the second transistor M2 through the second resistor R2, so that the gate potential of the second transistor M2 varies within the range of [ VGL + V2, VGH-V2 ]. That is, when the clock signal CK1 at the clock signal input terminal CKV1 is greater than 0V, the signal conversion circuit 10 can lower the clock signal at the clock signal input terminal CKV1 and input the clock signal to the gates of the first transistor M1 and the second transistor M2; when the clock signal CK2 at the clock signal input terminal CKV2 is less than 0V, the signal conversion circuit 10 can raise the clock signal CK1 at the clock signal input terminal CKV1 and input the clock signal CK1 to the gates of the first transistor M1 and the second transistor M2.

When the threshold voltage of the first transistor M1 is Vth1 and the threshold voltage of the second transistor M2 is Vth2, if the clock signal CK1 of the clock signal terminal CKV1 is directly input to the gate of the first transistor M1 and the gate of the second transistor M2, the ranges of the first transistor M1 and the second transistor M2 that are simultaneously turned on are [ VGL + Vth2, VGH + Vth1 ]. In contrast, when the clock signal C of the clock signal input terminal CKV1 is inputted to the gate of the first transistor M1 and the gate of the second transistor M2 after passing through the first resistor R1 and the second resistor R2, respectively, as the divided voltage value V1 of the first resistor R1 is greater than Vth1, the divided voltage value of the second resistor R2 is greater than Vth2, the first transistor M1 is a P-type transistor, that is, Vth1<0V, and the second transistor M2 is an N-type transistor, that is, Vth2>0V, the gate potential Vg1 of the first transistor M1 is turned on in the range of [ VGL + V1, VGH-V1] and the gate potential Vg2 of the second transistor M2 is turned on in the range of [ VGL + V2, VGH-V2 ]. When V1 is greater than | Vth1|, V2 is greater than Vth2, VGH-V1 is less than VGH + Vth1, VGL + V2 is greater than VGL + Vth 2; when V1 is equal to V2, the voltage range in which the first transistor M1 and the second transistor M2 are turned on simultaneously is [ VGL + Vth2, VGH-V1], and the range [ VGL + Vth2, VGH-V1] is included in the range [ VGL + Vth2, VGH + Vth1], so that the voltage range in which the first transistor M1 and the second transistor M2 are turned on simultaneously is narrowed, which is beneficial to reducing the power consumption caused by the existence of the through current, and thus the performance of the shift register unit can be improved.

It should be noted that, on the premise that the function of the signal conversion circuit in this embodiment can be realized, no specific limitation is imposed on whether the voltage drop value V1 of the first resistor R1 is the same as the voltage drop value V2 of the second resistor R2. Meanwhile, on the premise that the function of the signal conversion circuit in this embodiment can be realized, the signal conversion circuit may include a plurality of first resistors and a plurality of second resistors, which is not specifically limited in this embodiment of the present invention.

Optionally, fig. 6 is a schematic structural diagram of another signal conversion circuit provided in the embodiment of the present invention. As shown in fig. 6, the signal conversion circuit 30 includes a load unit 31; a first terminal of the load unit 31 is electrically connected to the clock signal input terminal CKV1, and a second terminal of the load unit 31 is electrically connected to the gate of the first transistor M1 and the gate of the second transistor M2; wherein, a potential difference between the first terminal of the load unit 31 and the second terminal of the load unit 31 is greater than a threshold voltage of the second transistor M2. At this time, the clock signal CK1 at the clock signal input terminal CKV1 goes through the load unit 31 and approaches 0V, or drops.

Specifically, the clock signal CK1 of the clock signal input terminal CKV1 approaches 0V after passing through the load unit 31, that is, when the potential difference between the two ends of the load unit 31 is Δ V and the clock signal CK1 of the clock signal input terminal CKV1 changes within the range of [ VGL, VGH ], the gate potential of the first transistor M1 and the gate potential of the second transistor M2 can change within the range of [ VGL + Δ V, VGH- Δ V ]. Since the potential difference across the load unit 31 is greater than the threshold voltage Vth2 of the second transistor M2, when the absolute value | Vth1| of the threshold voltage Vth1 of the first transistor M1 is equal to the threshold voltage Vth2 of the second transistor M2, VGL + Δ V is greater than VGL + Vth2, and VGH- Δ V is smaller than VGH + Vth 1. Therefore, the variation range [ VGL + Δ V, VGH- Δ V ] of the gate potential of the first transistor M1 and the gate potential of the second transistor M2 is within the range [ VGL + Vth2, VGH + Vth1], that is, compared with the prior art, the voltage range in which the first transistor M1 and the second transistor M2 are simultaneously turned on is narrowed, which is beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

For example, for the case that the clock signal CK1 at the clock signal input terminal CKV1 approaches 0V after passing through the load unit 31, the load unit may include at least one third resistor. Fig. 7 is a schematic structural diagram of another signal conversion circuit according to an embodiment of the present invention. As shown in conjunction with fig. 6 and 7, the load unit 31 may include at least one third resistor R3; a first end of the third resistor R3 is electrically connected to the clock signal input terminal CKV1, and a second end of the third resistor R3 is electrically connected to the gate of the first transistor M1 and the gate of the second transistor M2. At this time, when the divided voltage value of the third resistor R3 is greater than the threshold voltage of the second transistor M2, the voltage range in which the first transistor M1 and the second transistor M2 are simultaneously turned on can be narrowed, which is beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit. The load unit 31 may include one third resistor R3, or may include a plurality of third resistors R3, which is not specifically limited in this embodiment of the present invention.

Alternatively, the clock signal CK1 of the clock signal input terminal CKV1 may generate a voltage drop across the load unit 31, that is, when the potential difference across the load unit 31 is Δ V and the clock signal CK1 of the clock signal input terminal CKV1 varies within the range of [ VGL, VGH ], the gate potential of the first transistor M1 and the gate potential of the second transistor M2 may vary within the range of [ VGL- Δ V, VGH- Δ V ]. Since the potential difference across the load cell 31 is greater than the threshold voltage Vth2 of the second transistor M2, when the absolute value | Vth1| of the threshold voltage Vth1 of the first transistor M1 is equal to the threshold voltage Vth2 of the second transistor M2, VGL- Δ V is smaller than VGL + Vth2, and VGH- Δ V is smaller than VGH + Vth1, and the voltage range at which the first transistor M1 and the second transistor M2 are simultaneously turned on is [ VGL + Vth2, VGH- Δ V ]. Therefore, the voltage range [ VGL + Vth2, VGH- Δ V ] of the first transistor M1 and the second transistor M2 which are turned on simultaneously is within the range [ VGL + Vth2, VGH + Vth1], that is, compared with the prior art, the voltage range of the first transistor M1 and the second transistor M2 which are turned on simultaneously is reduced, which is beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

For example, in case that the clock signal CK1 of the clock signal input terminal CKV1 generates a voltage drop through the load unit 31, the load unit 31 may include at least one third diode, an anode of the third diode is electrically connected to the clock signal input terminal CKV1, and a cathode of the third diode is electrically connected to the gate of the first transistor M1 and the gate of the second transistor M2; and when at least two second diodes are included, the third diodes should be connected in series in sequence. Fig. 8 is a schematic structural diagram of another signal conversion circuit according to an embodiment of the present invention. As shown in fig. 8, the load unit 31 includes a third diode D3, an anode of the third diode D3 is electrically connected to the clock signal input terminal CKV 1; a cathode of the third diode D3 is electrically connected to the gate of the first transistor M1 and the gate of the second transistor M2. Because the third diode D3 has a tube voltage drop, that is, the clock signal CK1 at the clock signal input terminal CKV1 generates a voltage drop after passing through the third diode D3, so that the voltages input to the gate of the first transistor M1 and the gate of the second transistor M2 are changed, thereby achieving the purpose of reducing the voltage range in which the first transistor M1 and the second transistor M2 are simultaneously turned on, and thus being beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

Optionally, fig. 9 is a schematic structural diagram of another signal conversion circuit provided in the embodiment of the present invention. As shown in fig. 9, the signal conversion circuit 30 includes a first switching unit 321, a second switching unit 322, and a coupling capacitor C1; the first switch unit 321 is electrically connected between the first end C11 of the coupling capacitor C1 and the clock signal input terminal CKV 1; the second switch unit 322 is electrically connected between the second end C12 of the coupling capacitor C1 and the clock signal input terminal CKV 1; a first end C11 of the coupling capacitor C1 is electrically connected with the gate of the first transistor M1 and the gate of the second transistor M2; the third switching unit 323 is electrically connected between the second terminal C12 of the coupling capacitor C1 and the low level signal VGL; the fourth switching unit 324 is electrically connected between the second end C12 of the coupling capacitor C1 and the VGH high-level signal; the first switch unit 321 is configured to be turned on during the first stage and the third stage, and write the clock signal CK1 from the clock signal input terminal CKV1 of the first stage or the third stage into the first terminal C11 of the coupling capacitor C1; the second switch unit 322 is used for conducting during the second stage and the fourth stage, and writing the clock signal from the clock signal input terminal CKV2 of the second stage or the fourth stage into the second terminal of the coupling capacitor C1 to raise or lower the potential of the first terminal C11 of the coupling capacitor C1; the third switching unit 323 is configured to be turned on in the first stage to write the low level signal VGL into the second end C11 of the coupling capacitor C1; the fourth switching unit 324 is configured to be turned on in the third phase to write the high-level signal VGH into the second terminal C12 of the coupling capacitor C1; the first stage and the second stage are rising edge stages of the clock signal CK1, the third stage and the fourth stage are falling edge stages of the clock signal CK1, and the second stage and the third stage are located between the first stage and the fourth stage.

Illustratively, when the clock signal CK1 of the clock signal input terminal CKV1 varies within the range of [ -8V, 8V ], the clock signal CK1 may gradually rise from-8V to 0V in the first stage; in the second phase, the clock signal CK1 may gradually rise from 0V to 8V; in the third stage, the clock signal CK1 may fall from 8V to 0V; in the fourth stage, the clock signal CK1 may fall from 0V to-8V; meanwhile, the high level signal may be a fixed potential of 8V, and the low level signal may be a fixed potential of-8V.

At the beginning of the first phase, the first switching unit 321 and the third switching unit 323 are turned on, the second switching unit 322 and the fourth switching unit are turned off, and the clock signal CK1 is written into the first end C11 of the coupling capacitor C1 and the gate of the first transistor M1 and the gate of the second transistor M2 through the turned-on first switching unit 321, so that the gate potential of the first transistor M1 and the gate potential of the second transistor M2 are-8V; the low level signal VGL is written into the second terminal C12 of the coupling capacitor C1 through the turned-on third switching unit 323; at the end of the first phase, the clock signal CK1 rises to 0V, so that the first terminal C11 of the coupling capacitor C1 rises to 0V, the potential of the second terminal C12 of the coupling capacitor C1 is maintained at-8V, and the potential difference between the first terminal C11 and the second terminal C12 of the coupling capacitor C1 is 8V.

At the beginning of the second phase, the second switch unit 322 is turned on, the first switch unit 321, the third switch unit 323 and the fourth switch unit 324 are all turned off, and since the clock signal CK1 at this time has risen to 0V, the clock signal CK1 of 0V is written into the second end C12 of the coupling capacitor C1 through the turned-on second switch unit 322, so that the potential of the second end C12 of the coupling capacitor C1 rises by 8V; due to the coupling effect of the coupling capacitor C1, the potential difference between the first end C11 and the second end C12 of the coupling capacitor C1 needs to be kept unchanged, so the potential of the first end C11 of the coupling capacitor C1 also rises by 8V, that is, the potential of the first end C11 of the coupling capacitor C1 jumps from 0V to 8V directly at the beginning of the second stage, and at this time, the gate potential of the first transistor M1 and the gate potential of the second transistor M2 jump from 0V to 8V directly; at the end of the second phase, the potential of the second terminal C12 of the coupling capacitor C1 is raised to 8V, and correspondingly, the potential of the first terminal C11 of the coupling capacitor C1 is raised to 16V, i.e., the gate potential of the first transistor M1 and the gate potential of the second transistor M2 are raised to 16V.

At the beginning of the third stage, the clock signal CK1 starts to enter into a falling edge, the first switching unit 321 and the fourth switching unit 324 are turned on, the second switching unit 322 and the third switching unit 323 are turned off, and since the clock signal CK1 has risen to 8V at this time, the 8V clock signal CK1 is written to the first end C11 of the coupling capacitor C1 through the turned-on first switching unit 321; meanwhile, the high level signal VGH is written into the second terminal C12 of the coupling capacitor C1 through the turned-on fourth switching unit 324; at the end of the third stage, the clock signal CK1 falls to 0V, so that the first terminal C11 of the coupling capacitor C1 falls to 0V, the potential of the second terminal C12 of the coupling capacitor C1 is maintained at 8V, and the potential difference between the first terminal C11 and the second terminal C12 of the coupling capacitor C1 is 8V.

At the beginning of the fourth phase, the second switch unit 322 is turned on, the first switch unit 321, the third switch unit 323 and the fourth switch unit are turned off, and since the clock signal CK1 at this time has risen to 0V, the clock signal CK1 of 0V is written into the second terminal C12 of the coupling capacitor C1 through the turned-on second switch unit 322, so that the potential of the second terminal C12 of the coupling capacitor C1 drops by 8V; due to the coupling effect of the coupling capacitor C1, the potential difference between the first end C11 and the second end C12 of the coupling capacitor C1 needs to be kept unchanged, so the potential of the first end C11 of the coupling capacitor C1 also drops by 8V, that is, the potential of the first end C11 of the coupling capacitor C1 jumps from 0V to-8V directly at the beginning of the second stage, and the gate potential of the first transistor M1 and the gate potential of the second transistor M2 jump from 0V to-8V directly at this time; at the end of the fourth phase, the potential of the second terminal C12 of the coupling capacitor C1 is decreased to-8V, and correspondingly, the potential of the first terminal C11 of the coupling capacitor C1 is decreased to-16V, i.e., the gate potential of the first transistor M1 and the gate potential of the second transistor M2 are increased to-16V.

In the present embodiment, when the clock signal CK1 is on the rising edge, the voltages input to the gate of the first transistor M1 and the gate of the second transistor M2 are-8V to 0V and 8V to 16V, and when the clock signal CK1 is on the falling edge, the voltages input to the gate of the first transistor M1 and the gate of the second transistor M2 are 8V to 0V and-8V to-16V; when the threshold voltage Vth1 of the first transistor M1 is-2V and the threshold voltage Vth2 of the second transistor M2 is 2V, if the gate potential Vg1 of the first transistor M1 is less than 6V, the first transistor M1 is turned on; if the gate potential Vg2 of the second transistor M2 is greater than-6V, the second transistor M2 is turned on. In this way, at the rising edge, the voltage at which the first transistor M1 and the second transistor M2 are turned on simultaneously is reduced to [ -6V, 0V ], and at the falling edge, the voltage at which the first transistor M1 and the second transistor M2 are turned on simultaneously is reduced to [0V, 6V ], so that the time of the through current generated by the simultaneous turning on of the first transistor M1 and the second transistor M2 is reduced, which is beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

Optionally, fig. 10 is a schematic structural diagram of another signal conversion circuit provided in the embodiment of the present invention. As shown in conjunction with fig. 9 and 10, the first switching unit 321 of the signal converting circuit 30 includes a third transistor T3, the second switching unit 322 of the signal converting circuit 30 includes a fourth transistor T4, and the third switching unit 323 of the signal converting circuit 30 includes a fifth transistor T5; the fourth switching unit 324 of the signal conversion circuit 30 includes a sixth transistor T6; a first electrode of the third transistor T3 is electrically connected to the clock signal input terminal CKV1, and a second electrode of the third transistor T3 is electrically connected to the first end C11 of the coupling capacitor C1; the gate of the third transistor T3 is electrically connected to receive the first gate control signal SW 1; a first electrode of the fourth transistor T4 is electrically connected to the clock signal input terminal CKV1, a second electrode of the fourth transistor T4 is electrically connected to the second terminal C12 of the coupling capacitor C1, and a gate of the fourth transistor T4 receives the second gate control signal SW 2; a first electrode of the fifth transistor T5 is electrically connected to the low level signal VGL, a second electrode of the fifth transistor T5 is electrically connected to the second terminal C11 of the coupling capacitor C1, and a gate of the fifth transistor T5 receives the third gate control signal SW 3; a first electrode of the sixth transistor T6 is electrically connected to the high level signal VGH, a second electrode of the sixth transistor T6 is electrically connected to the second terminal C11 of the coupling capacitor C1, and a gate of the sixth transistor T6 receives the fourth gate control signal SW 4.

Specifically, the third transistor T3 is turned on under the control of the active first gate control signal SW 1. The fourth transistor T4 is turned on under the control of the effective second gate control signal SW2, the fifth transistor T5 is turned on under the control of the effective third gate control signal SW3, and the sixth transistor T6 is turned on under the control of the effective fourth gate control signal SW4, so that in the clock signal writing process, through the coupling effect of the coupling capacitor C1, the electric signals written to the gate of the first transistor M1 and the gate of the second transistor M2 are rapidly increased or rapidly decreased, thereby reducing the time for simultaneously turning on the first transistor M1 and the second transistor M2, reducing the power consumption caused by the through current generated by simultaneously turning on the first transistor M1 and the second transistor M2, and further improving the performance of the shift register unit.

Optionally, when the third transistor T3 is an N-type transistor and the fourth transistor T4 is a P-type transistor, or the third transistor T3 is a P-type transistor and the fourth transistor T4 is an N-type transistor, the first gate control signal SW1 and the second gate control signal SW2 are the same gate control signal SW.

The grid of the N-type transistor is conducted when the grid of the N-type transistor is a high level signal, and the grid of the P-type transistor is conducted when the grid of the P-type transistor is a low level signal. Taking the third transistor T3, the fifth transistor T5, and the sixth transistor T6 as N-type transistors and the fourth transistor T4 as P-type transistors as an example, the driving timing of the present embodiment is exemplarily described.

Illustratively, fig. 11 is a driving timing diagram of a signal conversion circuit corresponding to fig. 10. As shown in fig. 10 and 11, the clock signal CK1 of the clock signal input terminal CKV1 can be changed between [ -8V, 8V ], the high level signal VGH is a fixed potential of 8V, for example, and the low level signal is a fixed potential of-8V, for example, when the gate potential Vg1 of the first transistor M1 is less than 6V, the first transistor M1 is turned on, and when the gate potential Vg2 of the second transistor M2 is greater than-6V, the second transistor M2 is turned on.

At a start time T1 of the first phase, the third transistor T3 and the fifth transistor T5 start to be turned on, the fourth transistor T4 and the sixth transistor T6 are turned off, the-8V clock signal CK1 is written into the first end C11 of the coupling capacitor C1 through the turned-on third transistor T3, and the-8V low-level signal is written into the second end C12 of the coupling capacitor C1 through the turned-on fifth transistor T5; in the first stage from T1 to T2, the third transistor T3 and the fifth transistor T5 are kept on, the fourth transistor T4 and the sixth transistor T6 are kept off, the potential of the first end C11 of the coupling capacitor C1 is gradually increased, and the potential of the second end C12 of the coupling capacitor C1 is kept unchanged; at the end time t2 of the first stage, the potential of the first terminal C11 of the coupling capacitor C1 rises to 0V, so that the potential difference between the first terminal C11 and the second terminal C12 of the coupling capacitor C1 is 8V.

At the start time T2 of the second phase, the fourth transistor T4 starts to be turned on, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned off, the clock signal CK1 at this time has risen to 0V, and the clock signal CK1 of 0V is written into the second end C12 of the coupling capacitor C1 through the turned-on fourth transistor T4, so that the potential of the second end C12 of the coupling capacitor C1 jumps from-8V to 0V, that is, the potential of the second end C12 of the coupling capacitor C1 rises by 8V; due to the coupling effect of the coupling capacitor C1, the potential difference between the first terminal C11 and the second terminal C12 of the coupling capacitor C1 needs to be kept constant, so the potential of the second terminal C12 of the coupling capacitor C1 also rises by 8V, and the potential of the second terminal C12 of the coupling capacitor C1 jumps from 0V to 8V, that is, the gate potentials Vg of the first transistor M1 and the second transistor M2 jump from 0V to 8V; in the second phase t 2-t 3, the clock signal CK1 continues to rise to 8V, that is, at the end time t3 of the second phase, the potential of the second terminal C12 of the coupling capacitor C1 rises to 8V; accordingly, the potential of the first terminal C11 of the coupling capacitor C1 is raised to 16V, i.e., the gate potentials Vg of the first transistor M1 and the second transistor M2 are raised to 16V.

At the start time T3 of the third stage, the clock signal CK1 starts to enter a falling edge, the third transistor T3 and the sixth transistor T6 are turned on, the fourth transistor T4 and the fifth transistor T5 are turned off, and since the clock signal CK1 at this time has risen to 8V, the 8V clock signal CK1 is written to the first end C11 of the coupling capacitor C1 through the turned-on third transistor T3; meanwhile, the high level signal VGH is written into the second terminal C12 of the coupling capacitor C1 through the turned-on sixth transistor T6; at the end time t4 of the third stage, the clock signal CK1 falls to 0V, so that the first end C11 of the coupling capacitor C1 falls to 0V, the potential of the second end C12 of the coupling capacitor C1 is maintained at 8V, and the potential difference between the first end C11 and the second end C12 of the coupling capacitor C1 is 8V.

At the start time T4 of the fourth stage, the fourth transistor T4 starts to be turned on, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned off, and since the clock signal CK1 at this time has risen to 0V, the clock signal CK1 of 0V is written into the second end C12 of the coupling capacitor C1 through the turned-on fourth transistor T4, so that the potential of the second end C12 of the coupling capacitor C1 drops by 8V; due to the coupling effect of the coupling capacitor C1, the potential difference between the first end C11 and the second end C12 of the coupling capacitor C1 needs to be kept unchanged, so the potential of the first end C11 of the coupling capacitor C1 also drops by 8V, that is, the potential of the first end C11 of the coupling capacitor C1 jumps from 0V to-8V directly at the beginning of the second stage, and the gate potentials Vg of the first transistor M1 and the second transistor M2 also jump from 0V to-8V directly at this time; at the end of the fourth phase, the potential of the second terminal C12 of the coupling capacitor C1 drops to-8V, and correspondingly, the potential of the first terminal C11 of the coupling capacitor C1 drops to-16V, i.e., the gate potentials Vg of the first transistor M1 and the second transistor M2 drop to-16V.

In this way, at the rising edge, the voltage at which the first transistor M1 and the second transistor M2 are turned on simultaneously is reduced to [ -6V, 0V ], and at the falling edge, the voltage at which the first transistor M1 and the second transistor M2 are turned on simultaneously is reduced to [0V, 6V ], so that the time of the through current generated by the simultaneous turning on of the first transistor M1 and the second transistor M2 is reduced, which is beneficial to reducing the power consumption of the shift register unit and improving the performance of the shift register unit.

In addition, in the embodiment of the present invention, in order for the shift module to realize a latch function of the shift signal, the shift module may be composed of a plurality of transistors. For example, fig. 12 is a schematic circuit diagram of a shift register unit according to an embodiment of the present invention. As shown in fig. 12, the shift module 10 may be composed of a first inverter 11, a second inverter 12, and 8 transistors (M3 to M10). The first inverter 11 is composed of a first transistor M1 and a second transistor M2 with different channel types, the second inverter 12 can also be composed of transistors M11 and M12 with different channel types, and the channel type of the transistor M11 can be the same as that of the first transistor M1, and the channel type of the transistor M12 can be the same as that of the second transistor M2, when the gate of the transistor M11 and the gate of the transistor M12 are input terminals of the second inverter 12, the second electrode of the transistor M11 and the first electrode of the transistor M12 are output terminals of the second inverter 12, and the first electrode of the transistor M11 is electrically connected to a high level signal VGH, and the first electrode of the transistor M12 is electrically connected to a low level signal VGL; meanwhile, channel types of the transistors M3, M4, M7, and M8 may be the same as that of the first transistor M1, and the transistors M5, M6, M9, and M10 may be the same as that of the second transistor M2.

A first electrode of the first transistor M1 is electrically connected to the high level signal VGH, a second electrode of the second transistor M1 is electrically connected to the low level signal VGL, and a gate of the first transistor M1 and a gate of the second transistor M2 are both electrically connected to the clock signal input terminal CKV1 through the signal conversion circuit 30; the second electrode of the first transistor M1 and the first electrode of the second transistor M2 are output terminals of the first inverter 11; the gate of the transistor M3 is electrically connected to the output terminal of the first inverter 11. A first electrode of the transistor M3 is electrically connected to the high level signal VGH, and a second electrode of the transistor M3 is electrically connected to the first electrode of the transistor M4. The second electrode of the transistor M4 and the first electrode of the transistor M5 are both electrically connected to the first node N1, and the gate of the transistor M4 and the gate of the transistor M5 are both electrically connected to the shift signal input terminal IN; a first electrode of the transistor M5 is electrically connected to a first electrode of the transistor M6; the gate of the transistor M6 is electrically connected to the clock signal input terminal CKV1, and the second electrode of the transistor M6 is electrically connected to the low level signal VGL. The gate of the transistor M7 is electrically connected to the clock signal input terminal CKV1, the first electrode of the transistor M7 is electrically connected to the high level signal VGH, and the second electrode of the transistor M7 is electrically connected to the first electrode of the transistor M8. A second electrode of the transistor M8 and a first electrode of the transistor M9 are electrically connected to the first node N1, and a gate of the transistor M8, a gate of the transistor M9, and an output terminal of the second inverter 12 are electrically connected to the second node N2; a first electrode of the transistor M9 is electrically connected to a second electrode of the transistor M10; a first electrode of the transistor M10 is electrically connected to the low level signal VGL, and a gate of the transistor M10 is electrically connected to the output terminal of the first inverter 11; the input terminal of the second inverter 12 is electrically connected to the first node N1. In addition, the second node N2 is electrically connected to the enable module 20 and the shift signal output Next as an output terminal of the latch 10.

Accordingly, the enable module may be composed of a plurality of transistors in order to enable the enable module to perform a logic operation and output a gate driving signal. Illustratively, with continued reference to fig. 12, the enable module 20 may include 4 transistors (M13, M14, M15, and M16). The gate of the transistor M15 is electrically connected to the clock signal input terminal CKV2, and the first electrode of the transistor M15 is electrically connected to the high level signal VGH; a second electrode of the transistor M15 is electrically connected to the first electrode of the transistor M13 and the gate driving signal output terminal Gout; a second electrode of the transistor M13 is electrically connected to the high level signal VGH, and a gate of the transistor M13 and a gate of the transistor M14 are electrically connected to the output terminal of the latch module 10 as the input terminal of the enable module 20; a first electrode of the transistor M14 is electrically connected to the low level signal VGL, and a second electrode of the transistor M14 is electrically connected to the first electrode of the transistor M16; a second electrode of the transistor M16 is electrically connected to the gate driving signal output terminal Gout. Here, the transistor M13 has the same channel type as the transistor M15, and the transistor M14 has the same channel type as the transistor M16. The gate driving signal output by the gate driving signal output terminal Gout is a signal obtained by nand-operating the signal received by the input terminal of the enable module and the clock signal received by the clock signal input terminal CKV2 by the enable module.

Illustratively, fig. 13 and fig. 12 correspond to a driving timing diagram of a shift register unit. As shown in fig. 12 and 13, the transistors M3, M4, M7, M8, M11, M13, and M15 are all N-type transistors, and the transistors M5, M6, M9, M10, M12, M14, and M16 are all P-type transistors.

IN the first stage t 1', the clock signal CK1 of the clock signal input terminal CKV1 controls the transistor M6 to be turned on, the shift signal of the shift signal input terminal IN controls the transistor M5 to be turned on, the clock signal CK2 of the clock signal input terminal CKV2 controls the transistor M15 to be turned on, the low level signal VGL is written into the first node through the turned-on transistors M5 and M6 IN sequence, so that the input terminal of the second inverter 12 electrically connected to the first node inputs the low level signal VGL, at this time, the output terminal of the second inverter 12 outputs the high level signal VGH to the second node, and the shift signal output terminal Next electrically connected to the second node outputs the high level signal; accordingly, the shift module 10 outputs a high level signal to the gates of the transistors M13 and M14 of the enable module 20, so that the transistor M14 is turned on, and at this time, the transistor M16 is turned off, and the low level signal VGL received by the first electrode of the transistor M14 cannot be output to the gate driving signal output terminal Gout; since M15 is turned on, the high level signal VGH is output through the turned-on transistor M15 and the gate driving signal output terminal Gout, i.e., the gate driving signal Si output by the gate driving signal output terminal Gout is a high level signal.

In the second stage t 2', the clock signal CK1 at the clock signal input terminal CKV1 controls the first transistor M1 to be turned on after passing through the signal conversion circuit 30, the clock signal CK2 at the clock signal input terminal CKV2 controls the transistor M16 to be turned on, and the high-level signal VGH is written into the gate of the transistor M10 through the turned-on first transistor M1, so that the transistor M10 is turned on; since the second node N2 is a high level signal in the first phase, the transistor M9 is kept turned on, so that a low level signal is written into the first node N1 through the turned-on transistors M10 and M9, i.e., the first node N1 keeps a low level signal, the second inverter 12 outputs a high level signal to the second node N2, and the shift signal output by the Next signal output terminal is kept as a high level signal; at this time, the transistors M14 and M16 in the enable module 20 are turned on, and the low level signal VGL is output through the turned-on transistors M14 and M16 and the gate driving signal output terminal Gout, i.e., the gate driving signal Si output by the gate driving signal output terminal Gout is a low level signal.

IN the third stage t 3', the clock signal CK1 at the clock signal input terminal CKV1 controls the second transistor M2 to be turned on after passing through the signal conversion circuit 30, the shift signal STV at the shift signal input terminal IN controls the transistor M4 to be turned on, and the clock signal CK2 at the clock signal input terminal CKV2 controls the transistor M15 to be turned on; a low-level signal VGL is written into the gate of the transistor M3 through the turned-on second transistor M2, so that the transistor M3 is turned on, a high-level signal VGH is written into the first node N1 through the turned-on transistors M3 and M4 in sequence, and the first node N1 becomes a high-level signal; at this time, the input terminal of the second inverter 12 inputs a high level signal, so that the second inverter 12 outputs a low level signal VGL to the second node N2; a shift signal output terminal Next electrically connected to the second node N2 outputs a shift signal of a low level; accordingly, the shift module 10 outputs a low level signal to the gates of the transistors M13 and M14 of the enable module 20, so that the transistor M13 is turned on, the transistor M14 is turned on, and the high level signal VGH is output to the gate driving signal output terminal Gout through the turned-on transistor M13, that is, the gate driving signal output terminal Gout outputs the high level gate driving signal Si.

Since the N-type transistor is turned on at a high level and the P-type transistor is turned on at a low level, when the channel type of the transistor changes, the transistor can be turned on at a corresponding stage by a corresponding timing change. In the embodiment of the present invention, on the premise that the shift module and the enable module of the shift register unit can realize corresponding functions, the channel types of the transistors of the shift module and the enable module in the shift register unit are not specifically limited.

Optionally, fig. 14 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. As shown in fig. 14, the shift register unit 100 may further include a buffer 40, the buffer 40 being disposed between the enable module 20 and the gate driving signal output terminal Gout; the buffer 40 is used for increasing the driving capability of the gate driving signal output by the enable module 20 and outputting the gate driving signal through the gate driving signal output terminal. Fig. 15 is a schematic circuit diagram of another shift register unit according to an embodiment of the present invention. As shown in fig. 15, the buffer 40 of the shift register unit 100 may include three third inverters connected in sequence.

Optionally, with continued reference to fig. 15, the shift register unit 100 may further include a reset signal input terminal Rest and a reset unit 50; the reset unit 50 is electrically connected between the reset signal input terminal Rest and the shift module 10; the reset unit 50 is configured to reset the shift signal of the shift module 10 under the control of the reset signal at the reset signal input terminal Rest. Illustratively, with continued reference to fig. 15, the reset unit 50 may include a transistor M17.

It should be noted that fig. 15 is a schematic diagram illustrating an embodiment of the present invention, and the structure of the reset unit and the buffer is not particularly limited in the embodiment of the present invention, on the premise that the functions of the buffer and the reset unit can be realized.

The embodiment of the invention also provides a shift register. The shift register includes the shift register unit provided in the embodiment of the present invention, and therefore the shift register also has the beneficial effects of the shift register unit provided in the embodiment of the present invention, and the same points can be referred to the above description of the shift register unit, and are not described herein again.

In the embodiment of the present invention, the shift register may include a plurality of cascaded shift register units, and a part or all of the plurality of cascaded shift register units are the shift register units provided in the embodiment of the present invention. When a part of the shift register units in the shift register are the shift register units provided by the embodiment of the invention, the part of the shift register units can be the shift register units far away from the clock signal input pins. For convenience of description, the shift register units of the shift register provided in the embodiment of the present invention are all exemplified as the shift register units provided in the embodiment of the present invention.

For example, fig. 16 is a schematic structural diagram of a shift register according to an embodiment of the present invention. As shown in fig. 16, the shift register may include N shift register units ASG 1-ASGn according to an embodiment of the present invention; the N shift register units ASG 1-ASGn are arranged in a cascade mode, and N is a positive integer; the shift module of the first stage shift register unit ASG1 receives and latches the start signal STV, and the shift module of each of the second to nth stage shift register units ASG 2-ASGn receives and latches the shift signal output from the shift module of the previous stage shift register unit.

Specifically, the first stage shift register unit ASG1 outputs corresponding gate driving signals according to the start signal STV and the clock signals of the clock signal input terminal CKV1 and the clock signal input terminal CKV2, and outputs corresponding shift signals to the second stage shift register unit ASG 2; the second stage shift register unit ASG2 outputs corresponding gate driving signals according to the shift signal output from the first stage shift register unit ASG1 and the clock signals of the clock signal input terminal CKV1 and the clock signal input terminal CKV2, and outputs corresponding shift signals to the third stage shift register unit ASG 3; therefore, the shift register unit of the next stage can output corresponding gate driving signals according to the shift signals output by the shift register unit of the previous stage and the clock signals of the clock signal input terminal CKV1 and the clock signal input terminal CKV2, and output corresponding shift signals to the shift register unit of the next stage of the shift register unit of the previous stage, so that the cascaded shift register units can sequentially output the gate driving signals.

The embodiment of the invention also provides a display panel, which comprises the shift register provided by the embodiment of the invention. Therefore, the advantageous effects of the shift register provided in any embodiment are not described herein.

Exemplarily, fig. 17 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 17, the display panel includes a shift register provided by the embodiment of the present invention, and further includes pixels 201 and scanning signal lines 210 arranged in an array, the shift register is electrically connected to the pixels 201 through the scanning signal lines 210, and the shift register units ASG1 to ASGn of the shift register correspond to each other one by one, and provide scanning signals for a row of the pixels 201 through the scanning signal lines 210. When the cascaded shift register units ASG 1-ASGn sequentially output scan signals, the pixels 101 in the display panel are supplied with the scan signals line by line.

Embodiments of the present invention further provide a display device, where the display device includes the display panel provided in the embodiments of the present invention, and therefore the display device provided in the embodiments of the present invention has the beneficial effects of the display panel provided in the embodiments of the present invention, and details are not repeated herein.

For example, fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 18, the display device may be, for example, a cell phone, a tablet, a smart wearable device (e.g., a smart watch), and other electronic devices known to those skilled in the art.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register unit, comprising: a shift module and an enable module;

the shift module is used for receiving and latching a shift signal;

wherein at least the shifting module comprises a first inverter; the first inverter includes a first transistor and a second transistor; the first transistor is a P-type transistor, and the second transistor is an N-type transistor; a first electrode of the first transistor is electrically connected with a high-level signal, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor; a second electrode of the second transistor is electrically connected to a low level signal; the grid electrode of the first transistor and the grid electrode of the second transistor are input ends of the first inverter; a second electrode of the first transistor and a first electrode of the second transistor are output ends of the first inverter;

2. The shift register unit according to claim 1, wherein the signal conversion circuit comprises at least one first diode and at least one second diode;

wherein, each first diode is connected in series in sequence; the anode of the first diode is electrically connected with the grid electrode of the first transistor, and the cathode of the first diode is electrically connected with the clock signal input end;

all the second diodes are sequentially connected in series; and the anode of the second diode is electrically connected with the grid electrode of the second transistor, and the cathode of the second diode is electrically connected with the clock signal input end.

3. The shift register cell according to claim 1, wherein the signal conversion circuit includes a first resistor and a second resistor;

a first end of the first resistor is electrically connected with the clock signal input end, and a second end of the first resistor is electrically connected with a grid electrode of the first transistor;

a first end of the second resistor is electrically connected with the clock signal input end, and a second end of the second resistor is electrically connected with a grid electrode of the second transistor;

the threshold voltage of the first transistor is Vth1, the threshold voltage of the second transistor is Vth2, the divided voltage value of the first resistor is V1, and the divided voltage value of the second resistor is V2; wherein V1 > | Vth1| and V2 > Vth 2.

4. The shift register cell of claim 1, wherein the signal conversion circuit comprises a load unit;

a first end of the load unit is electrically connected with the clock signal input end, and a second end of the load unit is electrically connected with a grid electrode of the first transistor and a grid electrode of the second transistor;

wherein a potential difference between the first end of the load unit and the second end of the load unit is greater than a threshold voltage of the second transistor.

5. The shift register cell according to claim 4, wherein the load unit comprises at least one third resistor;

a first end of the third resistor is electrically connected to the clock signal input terminal, and a second end of the third resistor is electrically connected to the gate of the first transistor and the gate of the second transistor.

6. The shift register cell of claim 4, wherein the load cell comprises at least one third diode;

all the third diodes are sequentially connected in series; the anode of the third diode is electrically connected with the clock signal input end; a cathode of the third diode is electrically connected to a gate of the first transistor and a gate of the second transistor.

7. The shift register unit according to claim 1, wherein the signal conversion circuit comprises a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a coupling capacitor;

the first switch unit is electrically connected between the first end of the coupling capacitor and the clock signal input end; the second switch unit is electrically connected between the second end of the coupling capacitor and the clock signal input end; a first end of the coupling capacitor is electrically connected with a grid electrode of the first transistor and a grid electrode of the second transistor; the third switching unit is electrically connected between the second end of the coupling capacitor and the low-level signal; the fourth switching unit is electrically connected between the second end of the coupling capacitor and the high-level signal;

the first switch unit is used for conducting in a first stage and a third stage so as to write a clock signal of the clock signal input end of the first stage or the third stage into the first end of the coupling capacitor;

the second switch unit is used for conducting in a second stage and a fourth stage so as to write a clock signal of the clock signal input end of the second stage or the fourth stage into the second end of the coupling capacitor and raise or lower the potential of the first end of the coupling capacitor;

the third switching unit is used for conducting in the first stage so as to write the low-level signal into the second end of the coupling capacitor; the fourth switching unit is used for conducting in the third phase so as to write the high-level signal into the second end of the coupling capacitor

Wherein the first phase and the second phase are rising edge phases of the clock signal, the third phase and the fourth phase are falling edge phases of the clock signal, and the second phase and the third phase are located between the first phase and the fourth phase.

8. The shift register unit according to claim 7, wherein the first switching unit includes a third transistor, the second switching unit includes a fourth transistor, the third switching unit includes a fifth transistor, and the fourth switching unit includes a sixth transistor;

a first electrode of the third transistor is electrically connected with the clock signal input end, and a second electrode of the third transistor is electrically connected with a first end of the coupling capacitor; the grid electrode of the third transistor is electrically connected with a first grid electrode control signal;

a first electrode of the fourth transistor is electrically connected with the clock signal input end, a second electrode of the fourth transistor is electrically connected with a second end of the coupling capacitor, and a grid electrode of the fourth transistor receives a second grid control signal;

a first electrode of the fifth transistor is electrically connected with the low-level signal, a second electrode of the fifth transistor is electrically connected with a second end of the coupling capacitor, and a gate of the fifth transistor receives a third gate control signal;

a first electrode of the sixth transistor is electrically connected to the high-level signal, a second electrode of the sixth transistor is electrically connected to the second end of the coupling capacitor, and a gate of the sixth transistor receives a fourth gate control signal.

9. The shift register cell of claim 8, wherein the first gate control signal and the second gate control signal are the same gate control signal.

The third transistor is an N-type transistor, and the fourth transistor is a P-type transistor;

or, the third transistor is a P-type transistor, and the fourth transistor is an N-type transistor.

10. The shift register unit according to any one of claims 1 to 9, further comprising: a buffer and a gate drive signal output;

the buffer is electrically connected between the enabling module and the grid driving signal output end; the buffer is used for increasing the driving capability of the gate driving signal output by the enabling module and outputting the gate driving signal through the gate driving signal output end.

11. The shift register unit according to any one of claims 1 to 9, further comprising: a reset signal input terminal and a reset unit;

the reset unit is electrically connected between the reset signal input end and the shift module; the reset unit is used for resetting the shift signal of the shift module under the control of the reset signal input end.

12. A shift register, comprising: a shift register cell as claimed in any one of claims 1 to 11.

13. The shift register according to claim 12, comprising N of the shift register units; n shift register units are arranged in a cascade mode; wherein N is a positive integer;

the shift module of each stage of the shift register units from the second stage to the Nth stage receives and latches the shift signal output by the shift module in the shift register unit of the previous stage.

14. A display panel, comprising: a plurality of scan lines and the shift register according to any one of claims 12 to 13;

the output end of each shift register unit in the shift register is connected with one scanning line respectively.

15. A display device characterized by comprising the display panel according to claim 14.