CN113299223A - Display panel and display device - Google Patents
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- CN113299223A CN113299223A CN202110732575.2A CN202110732575A CN113299223A CN 113299223 A CN113299223 A CN 113299223A CN 202110732575 A CN202110732575 A CN 202110732575A CN 113299223 A CN113299223 A CN 113299223A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention provides a display panel and a display device. The display panel includes: the driving circuit comprises a plurality of cascaded shift registers; the shift register comprises a control module, a first output module and a second output module; the control module is used for controlling voltage signals of a control end of the first output module and a control end of the second output module; the first output module is used for outputting a first scanning signal under the control of a voltage signal of a control end of the first output module, and the first scanning signal is a low-level effective scanning signal; the second output module is used for outputting a second scanning signal under the control of the voltage signal of the control end of the second output module, and the second scanning signal is a scanning signal with high level and effective. The driving circuit in the embodiment of the invention can simultaneously provide enabling signals for the n-type transistor and the p-type transistor in the pixel circuit respectively, can reduce the number of the driving circuits, reduces the number of the transistors in a non-display area, and is beneficial to narrowing the frame of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
In semiconductor technology, the transistor types include p-type transistors and n-type transistors, and enable signals of the p-type transistors and the n-type transistors are different. However, if some pixel circuits include both p-type transistors and n-type transistors, driving circuits are required to be respectively provided for the p-type transistors and the n-type transistors to provide corresponding enable signals, so that the number of the driving circuits is increased, and the narrowing of the frame of the display panel is seriously affected.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, and aims to solve the problem of narrowing of a frame of the display panel.
An embodiment of the present invention provides a display panel, including: the driving circuit comprises a plurality of cascaded shift registers;
the shift register comprises a control module, a first output module and a second output module;
the control module is used for controlling voltage signals of a control end of the first output module and a control end of the second output module;
the first output module is used for outputting a first scanning signal under the control of a voltage signal of a control end of the first output module, and the first scanning signal is a low-level effective scanning signal;
the second output module is used for outputting a second scanning signal under the control of the voltage signal of the control end of the second output module, and the second scanning signal is a scanning signal with high level and effective.
The embodiment of the invention provides a display device which comprises the display panel provided by any embodiment of the invention.
The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: the cascaded shift register of the driving circuit comprises two output modules, wherein the first output module can output a first scanning signal for controlling the switching state of the p-type transistor under the control of the control module, and the second output module can output a second scanning signal for controlling the switching state of the n-type transistor under the control of the control module. The driving circuit can simultaneously provide enabling signals for the n-type transistor and the p-type transistor in the pixel circuit respectively, the number of the driving circuits can be reduced, the number of the transistors in a non-display area is reduced, and the narrowing of a frame of the display panel is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
FIG. 1 is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present invention;
FIG. 2 is a timing diagram of the pixel circuit of FIG. 1;
fig. 3 is a schematic diagram of a driving circuit according to an embodiment of the invention;
FIG. 4 is a diagram illustrating a shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram of the operation of the shift register;
FIG. 6 is a diagram illustrating a shift register according to an embodiment of the present invention;
FIG. 7 is a diagram of another shift register according to an embodiment of the present invention;
FIG. 8 is a diagram of another shift register according to an embodiment of the present invention;
FIG. 9 is another timing diagram of the operation of the shift register;
FIG. 10 is a diagram of another shift register according to an embodiment of the present invention;
FIG. 11 is a diagram of a driving circuit according to an embodiment of the present invention;
fig. 12 is a schematic view of a display device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The embodiment of the invention provides a display panel, which comprises a plurality of light-emitting devices and a plurality of pixel circuits, wherein the pixel circuits are electrically connected with the light-emitting devices and used for driving the light-emitting devices to emit light. The light emitting device includes a first electrode, a light emitting layer, and a second electrode stacked in this order. In one embodiment, the light emitting device is an organic diode light emitting device; in another embodiment, the light emitting device is an inorganic diode light emitting device.
Fig. 1 is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the invention, and fig. 2 is a timing diagram of the pixel circuit in fig. 1. As shown in fig. 1, the pixel circuit is a 7T1C circuit, and the seven transistors are respectively: a driving transistor Tm, a data writing transistor T1, a threshold compensating transistor T2, a first reset transistor T3, a second reset transistor T4, a first light emission controlling transistor T5, and a second light emission controlling transistor T6. The first reset transistor T3 is used for resetting the N1 node, i.e., the control terminal of the driving transistor Tm; the second reset transistor T4 is used to reset the first electrode of the light emitting device 10. Also shown in FIG. 1 are a power signal terminal P, a data signal terminal D, a reset signal terminal Ref, a first control terminal S1-n, a second control terminal S2-P, a third control terminal S2-n, and a light emission control terminal E.
The threshold compensation transistor T2 and the first reset transistor T3 are n-type transistors, and the other transistors are p-type transistors. Alternatively, the active layers of the threshold compensation transistor T2 and the first reset transistor T3 may be made of metal oxide, and the active layers of the other transistors may be made of silicon. In the embodiment, the leakage current of the threshold compensation transistor T2 and the first reset transistor T3 to the N1 node can be reduced, the potential stability of the N1 node in the light-emitting stage is ensured, the problem of display flicker under low-frequency driving is solved, and the display effect is improved.
In another pixel circuit, one of the threshold compensation transistor T2 and the first reset transistor T3 is an n-type transistor, and is not illustrated in the drawings.
As shown in the timing chart of fig. 2, in the operation period of the pixel circuit, it is necessary to supply control signals to the four control terminals of the pixel circuit, respectively. The signals of the first control terminal S1-n and the third control terminal S2-n can be provided by two adjacent stages of shift registers of the same driving circuit respectively. Then, in the conventional arrangement, three sets of driving circuits need to be arranged in the display panel and arranged in the non-display area of the display panel, which results in an increase in the frame of the display panel.
Based on this, embodiments of the present invention provide a driving circuit, which can simultaneously provide an enable signal of an n-type transistor and an enable signal of a p-type transistor during operation, so as to meet a driving requirement for a pixel circuit, reduce the number of the driving circuits, reduce the number of transistors in a non-display area, and facilitate narrowing of a frame of a display panel.
Fig. 3 is a schematic diagram of a driving circuit according to an embodiment of the present invention, and as shown in fig. 3, the driving circuit includes a plurality of cascaded shift registers 20. The shift register 20 includes a first output module 21, a second output module 22, and a control module 23. In fig. 3, an m-th stage shift register 20(m) and an m-1-th stage shift register 20(m-1) are illustrated, and m is an integer of not less than 2.
The control module 23 is configured to control voltage signals of a control terminal of the first output module 21 and a control terminal of the second output module 22.
The first output module 21 is configured to output a first scan signal under the control of a voltage signal at a control terminal thereof, where the first scan signal is an active low-level scan signal; the scan signal with low level is effective, that is, when the first scan signal is a low level signal, the scan signal can control the transistor connected to the output terminal of the first output module 21 to turn on, that is, the low level signal is an enable signal of the transistor connected to the output terminal of the first output module 21. The first scan signal output by the first output module 21 can control the switching state of the p-type transistor.
The second output module 22 is configured to output a second scan signal under the control of the voltage signal at the control terminal thereof, where the second scan signal is an active-high scan signal. The scan signal active at high level, i.e. when the second scan signal is a high level signal, can control the transistor connected to the second output module 22 to turn on, i.e. the high level signal is an enable signal of the transistor connected to the output terminal of the second output module 22. The second scan signal output by the second output module 22 can control the switch state of the n-type transistor.
Also illustrated in fig. 3 is a pixel circuit connected to the shift register.
For the pixel circuit driven by the m-th stage shift register 20(m), the output terminal of the first output block 21 is electrically connected to the second control terminal S2-p, and the first output block 21 provides the first scan signal to the second control terminal S2-p when the pixel circuit is driven to operate. The output terminal of the second output block 22 is electrically connected to the third control terminal S2-n, and the second output block 22 provides the second scan signal to the third control terminal S2-n when the driving pixel circuit is operated. The first control terminal S1-n of the pixel circuit is electrically connected to the output terminal of the second output block 22 of the m-1 th stage shift register 20(m-1), and the second output block 22 provides the second scan signal to the first control terminal S1-n.
Referring to the timing diagram illustrated in fig. 2, the duty cycle of the pixel circuit includes: a reset phase t1, a data write phase t2, and a light emission phase t 3.
At the reset phase t 1: the second output block 22 of the m-1 th stage shift register 20(m-1) provides the second scan signal to the first control terminal S1-n, and the high level second scan signal at this stage can control the first reset transistor T3 to turn on, and provide the signal of the reset signal terminal Ref to the control terminal of the driving transistor Tm, so as to reset the control terminal of the driving transistor Tm.
At the data writing stage t 2: the second output block 22 of the mth stage shift register 20(m) provides the second scan signal to the third control terminal S2-n, and the high level second scan signal at this stage can control the second reset transistor T4 to turn on, and provide the signal of the reset signal terminal Ref to the first electrode of the light emitting device 10 to reset the first electrode; the first output module 21 of the m-th stage shift register 20(m) provides the second control terminal S2-p with the first scan signal of low level, and the first scan signal of low level at this stage can control the data writing transistor T1 and the threshold compensating transistor T2 to turn on, write the data voltage into the control terminal of the driving transistor Tm, and compensate the threshold voltage of the driving transistor Tm.
In the light emission phase t 3: the light emitting control terminal E provides an active level signal to control both the first light emitting control transistor T5 and the second light emitting control transistor T6 to be turned on, and the driving transistor Tm provides a driving current to the light emitting device 10 to control the light emitting device 10 to emit light. In the display panel provided by the embodiment of the invention, the display panel further comprises a group of light-emitting driving circuits, and the light-emitting control end E is electrically connected with the light-emitting driving circuits.
In the display panel provided in the embodiment of the present invention, the cascaded shift register of the driving circuit includes two output modules, a first output module can output a first scan signal for controlling a switching state of the p-type transistor under the control of the control module, and a second output module can output a second scan signal for controlling a switching state of the n-type transistor under the control of the control module. The driving circuit can simultaneously provide enabling signals for the n-type transistor and the p-type transistor in the pixel circuit respectively, the number of the driving circuits can be reduced, the number of the transistors in a non-display area is reduced, and the narrowing of a frame of the display panel is facilitated.
Fig. 4 is a schematic diagram of a shift register according to an embodiment of the present invention, and as shown in fig. 4, the shift register 20 includes a first node N1 and a second node N2; the first node N1 and the second node N2 are electrically connected to the control module 23, respectively.
The first output module 21 includes a first output pull-down module 211, and a control terminal of the first output pull-down module 211 is electrically connected to the second node N2; the first output pull-down block 211 is for providing the low level signal of the first clock signal terminal CK1 to the output terminal OUT1 of the first output block 21 under the control of the voltage of the second node N2. That is, the first output pull-down module 211 is used for controlling the output terminal OUT1 of the first output module 21 to output a low-level signal of the first scan signal.
The second output module 22 includes a second output pull-up module 221, and control terminals of the second output pull-up module 221 are respectively electrically connected to the first node N1 and the second node N2; the second output pull-up block 221 is for providing the high level signal of the second clock signal terminal CK2 to the output terminal OUT2 of the second output block 22 under the control of the voltage of the first node N1 and the voltage of the second node N2. That is, the second output pull-up block 221 is configured to control the output terminal OUT2 of the second output block 22 to output a high level signal of the second scan signal.
Fig. 5 is a timing diagram of the operation of the shift register. As shown in fig. 5, the duty ratio of the clock signal supplied from the second clock signal terminal CK2 is smaller than the duty ratio of the clock signal supplied from the first clock signal terminal CK 1. The duty ratio is a ratio of a width of a high level to a period in one period. The arrangement enables the low-level signal output by the first output module 21 to be used as an enable signal of the p-type transistor, and the high-level signal output by the second output module 22 to be used as an enable signal of the n-type transistor, so as to meet the driving requirement of the pixel circuit.
As shown in fig. 4, the first output module 21 further includes a first output pull-up module 212, and a control of the first output pull-up module 212 is electrically connected to the first node N1; the first output pull-up block 212 is for providing the signal of the first constant voltage terminal V1 to the output terminal OUT1 of the first output block 21 under the control of the voltage of the first node N1. Wherein the first constant voltage terminal V1 provides a high level constant signal.
The first output pull-up module 212 is configured to cooperate with the first output pull-down module 211, and after the first output pull-down module 211 controls the output end OUT1 of the first output module 21 to output a low level signal of the first scan signal, the first output pull-up module 212 controls the output end OUT1 to output a high level signal of the first scan signal, and the high level signal of the first scan signal controls the p-type transistor to be turned off, so that the first scan signal can meet the driving requirement of the pixel circuit.
As shown in fig. 4, the first output pull-down module 211 includes a first transistor M1, a control terminal of the first transistor M1 is electrically connected to the second node N2, a first terminal of the first transistor M1 is electrically connected to the first clock signal terminal CK1, and a second terminal of the first transistor M1 is electrically connected to the output terminal OUT1 of the first output module 21; when the second node N2 is at a low voltage level, the first transistor M1 is turned on to provide the signal of the first clock signal terminal CK1 to the output terminal OUT1 of the first output block 21, and when the second node N2 is at a low voltage level and the signal of the first clock signal terminal CK1 is a low voltage level signal, the output terminal OUT1 of the first output block 21 outputs a low voltage level signal of the first scan signal.
The first output pull-up module 212 includes a second transistor M2, a control terminal of the second transistor M2 is electrically connected to the first node N1, a first terminal of the second transistor M2 is electrically connected to the first constant voltage terminal V1, and a second terminal of the second transistor M2 is electrically connected to the output terminal of the first output module 21. When the first node N1 is at a low level, the second transistor M2 is turned on, so that the signal at the first constant voltage terminal V1 is provided to the output terminal OUT1 of the first output block 21, and the output terminal OUT1 of the first output block 21 outputs a high level signal of the first scan signal.
As shown in fig. 4, the second output pull-up module 221 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5. A control terminal of the third transistor M3 is electrically connected to the second node N2, a first terminal of the third transistor M3 is electrically connected to the second clock signal terminal CK2, and a second terminal of the third transistor M3 is electrically connected to a first terminal of the fourth transistor M4. The control terminal of the fourth transistor M4 is electrically connected to the first node N1, and the second terminal of the fourth transistor M4 is electrically connected to the output terminal OUT2 of the second output block 22. A control terminal of the fifth transistor M5 is electrically connected to the second node N2, a first terminal of the fifth transistor M5 is electrically connected to the second clock signal terminal CK2, and a second terminal of the fifth transistor M5 is electrically connected to the output terminal OUT2 of the second output block 22.
When the first node N1 is low, the fourth transistor M4 is turned on; when the second node N2 is low, the third transistor M3 and the fifth transistor M5 are turned on. When the first node N1 and the second node N2 are both low, the third transistor M3 and the fourth transistor M4 are both turned on, so that the high-level signal of the second clock signal terminal CK2 can be provided to the output terminal OUT2 of the second output block 22, and the output terminal OUT2 of the second output block 22 outputs the high-level signal of the second scan signal. Meanwhile, when the second node N2 is at a low level and the second clock signal terminal CK2 is at a high level, the fifth transistor M5 is turned on, and a high level signal can be provided to the output terminal OUT2 of the second output block 22.
In another embodiment, fig. 6 is a schematic diagram of a shift register according to an embodiment of the present invention, as shown in fig. 6, the second output module 22 further includes a third node N3 and a second output pull-down module 222, and a control terminal of the second output pull-down module 222 is electrically connected to the third node N3; the second output pull-down module 222 is used for providing the signal of the second constant voltage terminal V2 to the output terminal OUT2 of the second output module 22 under the control of the voltage of the third node N3. Wherein the second constant voltage terminal V2 provides a low level constant signal. The constant voltage signal provided by the second constant voltage terminal V2 is smaller than the constant voltage signal provided by the first constant voltage terminal V1.
The second output pull-down module 222 is configured to cooperate with the second output pull-up module 221, and after the second output pull-up module 221 controls the output end OUT2 of the second output module 22 to output a high level signal of the second scan signal, the second output pull-down module 222 controls the output end OUT2 to output a low level signal of the second scan signal, and the low level signal of the second scan signal controls the n-type transistor to be turned off, so that the second scan signal can meet the driving requirement of the pixel circuit.
As shown in fig. 6, the second output pull-down module 222 includes an eighth transistor M8, a control terminal of the eighth transistor M8 is electrically connected to the third node N3, a first terminal of the eighth transistor M8 is electrically connected to the second constant voltage terminal V2, and a second terminal of the eighth transistor M8 is electrically connected to the output terminal OUT2 of the second output module 22. When the third node N3 is at the low level, the eighth transistor M8 is controlled to be turned on, and the low level signal of the second constant voltage terminal V2 is provided to the output terminal OUT2 of the second output block 22, so that the output terminal OUT2 of the second output block 22 outputs the low level signal of the second scan signal.
As shown in fig. 6, the second output module 22 further includes an auxiliary pull-down module 223, the auxiliary pull-down module 223 is electrically connected to the third node N3, and the auxiliary pull-down module 223 is used for stabilizing the potential of the third node N3 under the control of the signal of the second clock signal terminal CK2 and the signal of the first clock signal terminal CK 1.
In the embodiment of the present invention, the second scan signal output by the output terminal OUT2 of the second output module 22 can be used to drive the pixel circuit to operate, wherein a high level signal in the second scan signal is an active level signal. In order to ensure the driving pixel circuit to operate normally, after the second scan signal provides the high level signal once, the low level signal needs to be maintained for a longer time, where the longer time is compared with the duration of the high level signal in the second scan signal. The auxiliary pull-down module 223 is arranged to stabilize the potential of the third node N3, and when the second scan signal is required to be a low level signal, the second output pull-down module 222 can be controlled by the third node N3 to ensure that the second output pull-down module 222 continuously provides the low level signal to the output terminal OUT2 of the second output module 22.
Specifically, the auxiliary pull-down module 223 includes a sixth transistor M6, a seventh transistor M7, and a first capacitor C1; a control terminal of the sixth transistor M6 is electrically connected to the second clock signal terminal CK2, a first terminal of the sixth transistor M6 is electrically connected to the second constant voltage terminal V2, and a second terminal of the sixth transistor M6 is electrically connected to the third node N3; a control terminal of the seventh transistor M7 is electrically connected to the first clock signal terminal CK1, a first terminal of the seventh transistor M7 is electrically connected to the second constant voltage terminal V2, and a second terminal of the seventh transistor M7 is electrically connected to the third node N3; a first plate of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and a second plate of the first capacitor C1 is electrically connected to the third node N3.
As will be understood by referring to the timing chart shown in fig. 5, it can be understood from the above description of the embodiment that, at the time when the second clock signal terminal CK2 is at the high level (at the time t3 in fig. 5), the second output pull-up block 221 provides the high level signal of the second clock signal terminal CK2 to the output terminal OUT2 of the second output block 22 under the control of the voltage of the first node N1 and the voltage of the second node N2, and at this time, the output terminal OUT2 of the second output block 22 outputs the high level signal, which is the enable signal for driving the N-type transistor in the pixel circuit. That is, in the period of the shift register operation, the output terminal OUT2 of the second output module 22 needs to be controlled to output a low-level signal at a time other than the time t3, so as to meet the driving requirement of the second scan signal for the pixel circuit.
At time t4, the second clock signal terminal CK2 is a low level signal, the first clock signal terminal CK1 is a high level signal, the sixth transistor M6 is turned on, the seventh transistor M7 is turned off, and the sixth transistor M6 is turned on and then provides the low level signal of the second constant voltage terminal V2 to the third node N3, so that the output terminal OUT2 of the second output module 22 outputs the low level signal of the second scan signal by the second output pull-down module 222 providing the low level signal of the second constant voltage terminal V2 to the output terminal OUT2 of the second output module 22 under the control of the third node N3.
At time t5, the second clock signal terminal CK2 is a low level signal, the first clock signal terminal CK1 is a low level signal, and the sixth transistor M6 and the seventh transistor M7 are both turned on to provide the low level signal of the second constant voltage terminal V2 to the third node N3 to stabilize the potential of the third node N3.
At time t6, the second clock signal terminal CK2 and the first clock signal terminal CK1 are both high level signals, and at this time, the sixth transistor M6 and the seventh transistor M7 are both turned off, and at this time, the third node N3 can maintain a low level by virtue of the effect of the first capacitor C1 to control the second output pull-down module 222 to be turned on.
The second output module 22 outputs the high level signal of the second scan signal at time t3, and after outputting the high level signal, the second output module 22 outputs the low level signal of the second scan signal, and the output time of the low level signal is longer than that of the high level signal. The first output block 21 outputs a low level signal of the first scan signal at time t4, and after outputting the low level signal, the first output block 21 outputs a high level signal of the first scan signal, and the output time of the high level signal is longer than that of the low level signal. For the second output module 22, after t6, it still needs to maintain a long time to output the low level signal, and the output of the low level signal of the first scan signal can be ensured by the setting of the auxiliary pull-down module 223.
Further, fig. 7 is a schematic diagram of another shift register according to an embodiment of the invention, as shown in fig. 7, the second output module 22 further includes a first protection module 224, a control terminal of the first protection module 224 is electrically connected to the second node N2, a first terminal of the first protection module 224 is electrically connected to the second clock signal terminal CK2, and a second terminal of the first protection module 224 is electrically connected to the third node N3; the first protection module 224 is used to control the second output pull-down module 224 to be turned off at the moment when the second output pull-up module 221 is turned on. The first protection module 224 can ensure that the output end OUT2 of the second output module 22 can normally output a high level signal, and avoid the interference caused by the opening of the second output pull-down module 224 to the output of the high level signal when the second output pull-up module 221 operates.
As shown in fig. 7, the first protection module 224 includes a ninth transistor M9, a control terminal of the ninth transistor M9 is electrically connected to the second node N2, a first terminal of the ninth transistor M9 is electrically connected to the second clock signal terminal CK2, and a second terminal of the ninth transistor M9 is electrically connected to the third node N3. Based on the above embodiments, when the first node N1 and the second node N2 are both low, the third transistor M3 and the fourth transistor M4 are both turned on, so that the high-level signal of the second clock signal terminal CK2 can be provided to the output terminal OUT2 of the second output block 22, and the high-level signal of the second scan signal output by the output terminal OUT2 can be used as the enable signal of the N-type transistor in the pixel circuit. By providing the first protection module, when the second node N2 is at a low voltage level, the ninth transistor M9 can be controlled to be turned on, and then the ninth transistor M9 provides a high-level signal of the second clock signal terminal CK2 to the third node N3, so as to control the eighth transistor M8 to be in a turned-off state, thereby preventing the signal of the second constant voltage terminal V2 from being provided to the output terminal OUT2 of the second output module 22, and causing interference to the signal of the output terminal OUT2 of the second output module 22.
In another embodiment, fig. 8 is a schematic diagram of another shift register according to an embodiment of the present invention, and as shown in fig. 8, the control module 23 includes a first node control module 231 and a second node control module 232. Wherein,
the first node control module 231 is electrically connected with the input terminal IN of the shift register, the third clock signal terminal CK3, the second constant voltage terminal V2, and the second node N2; the first node control module 231 is used for controlling the voltage of the first node N1 according to the signal of the input terminal IN of the shift register, the signal of the third clock signal terminal CK3, the signal of the second constant voltage terminal V2 and the signal of the second node N2; wherein, the signal of the third clock signal terminal CK3 and the signal of the first clock signal terminal CK1 have the same period.
The second node control module 232 is electrically connected to the input terminal IN of the shift register, the first clock signal terminal CK1, and the first constant voltage terminal V1; the second node control module 232 is used for controlling the voltage of the second node N2 according to the signal of the input terminal IN of the shift register, the signal of the first clock signal terminal CK1, and the signal of the first constant voltage terminal V1.
The signal of the first clock signal terminal CK1, the signal of the third clock signal terminal CK3, the signal of the first constant voltage terminal V1, the signal of the second constant voltage terminal V2, and the signal of the input terminal IN of the shift register cooperate with each other to control the potential of the first node N1 and the potential of the second node N2, so that when the shift register is operated, the output terminal OUT1 of the first output block 21 can output a first scan signal, and the output terminal OUT2 of the second output block 22 can output a second scan signal, wherein a low level signal IN the first scan signal can be used as an enable signal of a p-type transistor IN the pixel circuit, and a high level signal IN the second scan signal can be used as an enable signal of an N-type transistor IN the pixel circuit. The realization can cooperate pixel circuit work through a set of drive circuit, provides enable signal respectively for n type transistor and p type transistor in the pixel circuit simultaneously, can reduce drive circuit's the number that sets up, reduces the transistor quantity in non-display area, is favorable to the narrowing of display panel frame.
As shown in fig. 8, the first node control module 231 includes a tenth transistor M10 and an eleventh transistor M11. A control terminal of the tenth transistor M10 is electrically connected to the third clock signal terminal CK3, a first terminal of the tenth transistor M10 is electrically connected to the second constant voltage terminal V2, and a second terminal of the tenth transistor M10 is electrically connected to the first node N1; a control terminal of the eleventh transistor M11 is electrically connected to the second node N2, a first terminal of the eleventh transistor M11 is electrically connected to the input terminal IN of the shift register, and a second terminal of the eleventh transistor M11 is electrically connected to the first node N1.
The second node control module 232 includes a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14; a control terminal of the twelfth transistor M12 is electrically connected to the third clock signal terminal, a first terminal of the twelfth transistor M12 is electrically connected to the input terminal IN of the shift register, and a second terminal of the twelfth transistor M12 is electrically connected to the second node N2; a control terminal of the thirteenth transistor M13 is electrically connected to the first clock signal terminal, a first terminal of the thirteenth transistor M13 is electrically connected to the second terminal of the fourteenth transistor M14, and a second terminal of the thirteenth transistor M13 is electrically connected to the second node N2; a control terminal of the fourteenth transistor M14 is electrically connected to the first node N1, and a first terminal of the fourteenth transistor M14 is electrically connected to the first constant voltage terminal V1.
As shown in fig. 8, the control module 23 further includes a fifteenth transistor M15, a second capacitor C2, and a third capacitor C3. A control terminal of the fifteenth transistor M15 is electrically connected to the second constant voltage terminal V2, a first terminal of the fifteenth transistor M15 is connected to the fourth node N4, and a second terminal of the fifteenth transistor M15 is connected to the second node N2. The fifteenth transistor M15 is in a normally-on state, and during the potential holding stage of the second node N2, the leakage current from the second node N2 to the fourth node N4 can be reduced. The second capacitor C2 is used to maintain the potential of the second node N2, and the third capacitor C3 is used to maintain the potential of the first node N1.
Fig. 9 is another timing diagram of the operation of the shift register. The operation of the shift register provided by the embodiment of the present invention is described below with reference to the timing sequence in fig. 9. As shown in figure 9 of the drawings,
at time t 1', the input terminal IN of the shift register receives the start signal, the first clock terminal CK1 provides a high signal, the second clock terminal CK2 provides a high signal, and the third clock terminal CK3 provides a low signal. The third clock signal terminal CK3 controls the tenth transistor M10 and the twelfth transistor M12 to be turned on; the tenth transistor M10 writes a low level signal of the second constant voltage terminal V2 to the first node N1 after being turned on; after the twelfth transistor M12 is turned on, a low level signal inputted from the input terminal IN is written into the fourth node N4, and the fifteenth transistor M15 is normally on, so that the low level signal is written from the fourth node N4 into the second node N2 (this is the reason for the potential drop of the second node N2 at the 1 position); meanwhile, the fourth node N4 controls the eleventh transistor M11 to be turned on, writing the low level signal inputted from the input terminal IN to the first node N1. The first node N1 and the second node N2 are both low during this stage, that is, the control module 23 controls the first node N1 and the second node N2 to be both low during this stage.
When both the first node N1 and the second node N2 are low, for the first output module 21: the first output pull-down module 211 and the first output pull-up module 212 are both turned on. The second transistor M2 is turned on under the control of the first node N1, and provides a high level signal of the first constant voltage terminal V1 to the output terminal OUT 1; the first transistor M1 is turned on under the control of the second node N1 to supply a high level signal of the first clock signal terminal CK1 to the output terminal OUT 1; at this time, the output terminal OUT1 of the first output block 21 outputs a high level signal of the first scan signal.
When both the first node N1 and the second node N2 are low, for the second output module 22: the second output pull-up module 221 is turned on and the second output pull-down module 222 is turned off. The fourth transistor M4 is turned on under the control of the first node N1, the third transistor M3 is turned on under the control of the second node N2, and the high level signal of the second clock signal terminal CK2 is provided to the output terminal OUT2 through the third transistor M3 and the fourth transistor M4; meanwhile, the second node N2 controls the fifth transistor M5 to be turned on, and provides a high level signal of the second clock signal terminal CK2 to the output terminal OUT 2; the output terminal OUT2 of the second output module 22 outputs the high level signal of the second scan signal. The high level signal of the second scan signal is an enable signal for controlling an n-type transistor in the pixel circuit. In addition, at this stage, the second node N2 controls the ninth transistor M9 to be turned on, and the high level signal of the second clock signal terminal CK2 is supplied to the third node N3, and at this time, the third node N3 is at a high level, and the eighth transistor M8 can be controlled to be turned off.
At time t 2', the third clock signal terminal CK1 is changed from a low level signal to a high level signal, and both the tenth transistor M10 and the twelfth transistor M12 are turned off. The second clock signal terminal CK2 changes from high level to low level, and the signal transition of the second clock signal terminal CK2 couples with the potential of the second node N2, so that the potential of the second node N2 is pulled low continuously, as shown in position 2 in fig. 9. Meanwhile, the signal transition of the second clock signal terminal CK2 has a coupling effect on the potential of the first node N1, so that the potential of the first node N1 is pulled low, as shown in position 3 in fig. 9. However, IN this stage, the fourth node N4 keeps the low level of the previous stage to control the eleventh transistor M11 to turn on, so that the high level signal at the input terminal IN is written into the first node N1, and therefore the potential of the first node N1 is pulled high again after being pulled low for a short time. Therefore, at this stage, the first node N1 is at a high voltage level, and the second node N2 is at a low voltage level. That is, the control module 23 controls the first node N1 to be high and the second node N2 to be low at this stage.
When the first node N1 is high and the second node N2 is low, for the first output block 21: the first output pull-down module 211 is turned on and the first output pull-up module 212 is turned off. The second transistor M2 is off; the first transistor M1 is turned on to provide the high level signal of the first clock signal terminal CK1 to the output terminal OUT1 of the first output block 21, and the output terminal OUT1 of the first output block 21 continues to output the high level signal of the first scan signal.
When the first node N1 is high and the second node N2 is low, for the second output module 22: the second node N2 controls the fifth transistor M5 and the ninth transistor M9 to be turned on, and the fifth transistor M5 provides a low level signal of the second clock signal terminal CK2 to the output terminal OUT 2; the ninth transistor M9 provides the low level signal of the second clock signal terminal CK2 to the third node N3, and the second clock signal terminal CK2 is low level to control the sixth transistor M6 to turn on, and provides the low level signal of the second constant voltage terminal V2 to the third node N3, at this stage, the third node N3 is low level, and maintains the low level by the action of the first capacitor C1, and controls the eighth transistor M8 to turn on, and provides the low level signal of the second constant voltage terminal V2 to the output terminal OUT 2. At this time, the output terminal OUT2 of the second output block 22 outputs a low level signal of the second scan signal.
At time t 3', the first clock terminal CK1 changes from high level to low level, the first clock terminal CK1 couples to the second node N2, and the second node N2 is pulled low when the first clock terminal CK1 makes a transition, as shown in position 4 in FIG. 9. At this time, the second node N2 is low, and the first node N1 is high at the previous time.
At this stage, for the first output module 21: the first clock terminal CK1 is a low level signal, the first transistor M1 is turned on under the control of the potential of the second node N2, and the low level signal of the first clock terminal CK1 is provided to the output terminal OUT1, at this time, the output terminal OUT1 of the first output block 21 outputs a low level signal of the first scan signal, and the low level signal of the first scan signal can be used as an enable signal of the p-type transistor in the pixel circuit.
At this stage, for the second output module 22: the low level of the second node N2 controls the fifth transistor M5 and the ninth transistor M9 to be turned on, and the fifth transistor M5 provides the low level signal of the second clock signal terminal CK2 to the output terminal OUT 2; the ninth transistor M9 provides the low level signal of the second clock signal terminal CK2 to the third node N3, and the first clock signal terminal CK1 is low to control the sixth transistor M6 to turn on, and provides the low level signal of the second constant voltage terminal V2 to the third node N3, and at this stage, the third node N3 is low to control the eighth transistor M8 to turn on, and provides the low level signal of the second constant voltage terminal V2 to the output terminal OUT 2. At this time, the output terminal OUT2 of the second output block 22 outputs a low level signal of the second scan signal.
At time t 4', the second node N2 is low, the first node N1 is high, the output terminal OUT1 of the first output block 21 outputs a high level signal of the first scan signal, and the output terminal OUT2 of the second output block 22 outputs a low level signal of the second scan signal. The switching state of each transistor in the shift register is substantially the same as the time t 2' in this period, and will not be described again.
At time t 5', the third clock signal terminal CK3 is a low level signal, the second clock signal terminal CK2 is a high level signal, and the first clock signal terminal CK1 is a high level signal. After the tenth transistor M10 is turned on under the control of the signal from the third clock signal terminal CK3, the low level signal from the second constant voltage terminal V2 is written into the first node N1, so that the first node N1 changes from high to low. After the twelfth transistor M12 is turned on under the control of the signal from the third clock signal terminal CK3, the high level signal from the input terminal IN is written into the second node N2, and the second node N2 changes from low to high. At this stage, the first node N1 is low, and the second node N2 is high.
When the first node N1 is low and the second node N2 is high, for the first output block 21: the first transistor M1 is turned off, the second transistor M2 is turned on under the control of the first node N1, a high level signal of the first constant voltage terminal V1 is provided to the output terminal OUT1 of the first output block 21, and the output terminal OUT1 of the first output block 21 outputs a high level signal of the first scan signal.
When the first node N1 is low and the second node N2 is high, for the second output module 22: when the third transistor M3 is turned off, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off, the second output pull-up module 221 is turned off; the ninth transistor M9 is also turned off. In this stage, the sixth transistor M6 and the seventh transistor M7 in the auxiliary pull-down module 223 are both turned off, the third node N3 is maintained at a low level by the first capacitor C1 to control the eighth transistor M8 to be turned on, and the eighth transistor M8 is turned on to provide a low level signal of the second constant voltage terminal V2 to the output terminal OUT 2. The output terminal OUT2 of the second output module 22 outputs a low level signal of the second scan signal.
In addition, at other times than the times t1 'to t 5', the auxiliary pull-down module 223 in the second output module 22 is configured to stabilize the potential of the third node N3 under the combined action of the signal of the first clock signal terminal CK1, the signal of the second clock signal terminal CK2 and the first capacitor C1, so that the third node N3 maintains a low level to control the eighth transistor M8 to be turned on, and a low level signal of the second constant voltage terminal V2 is provided to the output terminal OUT 2.
In addition, at other times than the times t1 'to t 5', when the first node N1 is at a low level and the first clock signal terminal CK1 is at a low level signal, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on simultaneously, and then the high level signal of the first constant voltage terminal V1 is provided to the fourth node N4, so that the second node N2 is at a high level and the potentials of the first node N1 and the second node N2 are opposite.
Through the analysis of the timing sequence shown in fig. 9, when the shift register according to the embodiment of the invention works, the first output module 21 can be controlled to output the first scan signal, which is an active low-level scan signal, and the second output module 22 can be controlled to output the second scan signal, which is an active high-level scan signal. Also, the output timing of the low level signal of the first scan signal is subsequent to the output timing of the high level signal of the second scan signal, so that the second scan signal can control the first reset transistor T3 and the threshold compensation transistor T2 in the pixel circuit as illustrated in fig. 1 to be turned on (the above-described embodiment illustrates that the second scan signal may be supplied from the shift register of the adjacent stage), and the first scan signal can control the data write transistor T1 and the second reset transistor T4 in the pixel circuit as illustrated in fig. 1 to be turned on. Therefore, the group of driving circuits can work in cooperation with the pixel circuit, enable signals are provided for the n-type transistor and the p-type transistor in the pixel circuit respectively, the number of the driving circuits can be reduced, the number of the transistors in a non-display area is reduced, and the narrowing of a frame of the display panel is facilitated.
As shown by the dotted line circle in fig. 9, in the embodiment of the present invention, when the shift register is driven to operate, the rising edge of the signal of the second clock signal terminal CK2 is delayed from the falling edge of the signal of the third clock signal terminal CK 3. Alternatively, the rising edge of the signal of the second clock signal terminal CK2 is delayed by about 1 μ s from the falling edge of the signal of the third clock signal terminal CK 3. At time t 5' illustrated in fig. 9, the voltage of the third clock signal terminal CK3 changes from high to low, and the potential of the second node N2 changes from low to high. In the initial period when the voltage of the third clock signal terminal CK3 is changed from high to low, the second node N2 is changed from low to high, if the signal of the second clock signal terminal CK2 is already high in the initial period, the ninth transistor M9 (the first protection module 224) is not turned off in time when the second node N2 is still at low level, and the high signal of the second clock signal terminal CK2 is provided to the third node N3, so that the third node N3 is turned high, and the eighth transistor M8 is turned off. Meanwhile, the second node N2 still being at a lower level may not turn off the fifth transistor M5 in time, so that a high level of the second clock signal terminal CK2 may be partially outputted to the output terminal OUT2 of the second output module 22, resulting in abnormal output of the second scan signal. In the embodiment of the present invention, by designing the timing sequence of the clock signal, the rising edge of the signal of the second clock signal terminal CK2 is set to be delayed from the falling edge of the signal of the third clock signal terminal CK3, and in the initial period of the time t 5', the second clock signal terminal CK2 provides a low level signal with a certain duration to control the sixth transistor M6 to turn on, and the low level signal of the second constant voltage terminal V2 is written into the third node N3, so that the eighth transistor M8 can be controlled to turn on in time, and the low level signal is output to the output terminal OUT2 of the second output module 22 in time, thereby ensuring that the output terminal OUT2 of the second output module 22 can continuously output the low level signal of the second scan signal in the period, and ensuring that the second scan signal is normally output.
In another embodiment, fig. 10 is a schematic diagram of another shift register according to an embodiment of the present invention, and as shown in fig. 10, on the basis of the embodiment of fig. 8, the second output module 22 further includes a sixteenth transistor M16 and a fourth capacitor C4. Wherein, the control terminal of the sixteenth transistor M16 is connected to the second constant voltage terminal V2, the first terminal of the sixteenth transistor M16 is connected to the first plate of the fourth capacitor C4, the second terminal of the sixteenth transistor M16 is connected to the output terminal OUT2 of the second output module 22, and the second plate of the fourth capacitor C4 is connected to the third node N3. The sixteenth transistor M16 is in a normally open state, and maintains a low potential at the third node N3 to control the eighth transistor M8 to be turned on, so that at the time of outputting a low level signal to the output terminal OUT2 of the second output module 23, the low level signal of the output terminal OUT2 is transmitted to the first plate of the fourth capacitor C4 through the sixteenth transistor M16, due to the bootstrap action of the fourth capacitor C4, the second plate of the fourth capacitor C4 is also in a low potential, and the second plate of the fourth capacitor C4 is connected to the third node N3, thereby assisting the third node N3 to maintain a low potential.
Fig. 11 is a schematic diagram of a driving circuit according to an embodiment of the present invention, and fig. 11 illustrates a cascade connection manner of the m-1 th stage shift register 20(m-1) to the m +2 th stage shift register 20(m + 2).
As shown in fig. 11, the display panel includes a first power line VGH, a second power line VGL, a first clock signal line 1CK, a second clock signal line 1XCK, a third clock signal line 2CK, and a second clock signal line 2 XCK. The first clock signal line 1CK and the second clock signal line 1XCK are a set of clock signal lines, and the third clock signal line 2CK and the second clock signal line 2XCK are a set of clock signal lines.
The first constant voltage terminal V1 of each stage of the shift register 20 is electrically connected to the first power line VGH, and the second constant voltage terminal V2 of each stage of the shift register 20 is electrically connected to the second power line VGL.
The example where m is an odd number will be described. The first clock signal terminals CK1 of the even-numbered stage shift registers 20 are electrically connected to the first clock signal line 1CK, the second clock signal terminals CK2 of the even-numbered stage shift registers 20 are electrically connected to the third clock signal line 2CK, and the third clock signal terminals CK3 of the even-numbered stage shift registers 20 are electrically connected to the second clock signal line 1 XCK. The first clock signal terminals CK1 of the odd-numbered shift registers 20 are electrically connected to the second clock signal line 1XCK, the second clock signal terminals CK2 of the odd-numbered shift registers 20 are electrically connected to the fourth clock signal line 2XCK, and the third clock signal terminals CK3 of the odd-numbered shift registers 20 are electrically connected to the first clock signal line 1 CK.
The input terminal IN of the 1 st stage shift register 20 is connected to the start signal terminal, the input terminal IN of the m-th stage shift register 20(m) is electrically connected to the output terminal OUT1 of the first output block 21 of the m-1 th stage shift register 20(m-1), and the input terminal IN of the m +1 th stage shift register 20(m +1) is electrically connected to the output terminal OUT1 of the first output block 21 of the m-th stage shift register 20 (m). That is, IN the cascaded shift registers, except for the shift register of the 1 st stage, the input terminal IN of the shift register is connected to the output terminal OUT1 of an output block 21 IN the shift register of the previous stage.
Fig. 12 is a schematic view of a display device according to an embodiment of the present invention, and as shown in fig. 12, the display device includes a display panel 100 according to any embodiment of the present invention. The display device in the embodiment of the invention can be any equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a television, an intelligent watch and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. A display panel, comprising: a driving circuit including a plurality of shift registers connected in cascade;
the shift register comprises a control module, a first output module and a second output module;
the control module is used for controlling voltage signals of the control end of the first output module and the control end of the second output module;
the first output module is used for outputting a first scanning signal under the control of a voltage signal of a control end of the first output module, and the first scanning signal is an effective scanning signal with low level;
the second output module is used for outputting a second scanning signal under the control of a voltage signal of a control end of the second output module, and the second scanning signal is a scanning signal with high level effective.
2. The display panel according to claim 1,
the shift register comprises a first node and a second node; the first node and the second node are respectively and electrically connected with the control module;
the first output module comprises a first output pull-down module, and a control end of the first output pull-down module is electrically connected with the second node; the first output pull-down module is used for providing a low-level signal of a first clock signal end to an output end of the first output module under the control of the second node voltage;
the second output module comprises a second output pull-up module, and the control end of the second output pull-up module is respectively and electrically connected with the first node and the second node; the second output pull-up module is used for providing a high-level signal of a second clock signal end to an output end of the second output module under the control of the first node voltage and the second node voltage;
wherein, the duty ratio of the clock signal provided by the second clock signal terminal is smaller than that of the clock signal provided by the first clock signal terminal.
3. The display panel according to claim 2,
the first output module further comprises a first output pull-up module, and the control of the first output pull-up module is electrically connected with the first node; the first output pull-up module is used for providing a signal of a first constant voltage end to an output end of the first output module under the control of the first node voltage.
4. The display panel according to claim 3,
the first output pull-down module comprises a first transistor, a control end of the first transistor is electrically connected with the second node, a first end of the first transistor is electrically connected with the first clock signal end, and a second end of the first transistor is electrically connected with an output end of the first output module;
the first output pull-up module comprises a second transistor, a control end of the second transistor is electrically connected with the first node, a first end of the second transistor is electrically connected with the first constant voltage end, and a second end of the second transistor is electrically connected with an output end of the first output module.
5. The display panel according to claim 2,
the second output pull-up module comprises a third transistor, a fourth transistor and a fifth transistor;
a control end of the third transistor is electrically connected to the second node, a first end of the third transistor is electrically connected to the second clock signal end, and a second end of the third transistor is electrically connected to a first end of the fourth transistor;
a control end of the fourth transistor is electrically connected with the first node, and a second end of the fourth transistor is electrically connected with an output end of the second output module;
the control end of the fifth transistor is electrically connected with the second node, the first end of the fifth transistor is electrically connected with the second clock signal end, and the second end of the fifth transistor is electrically connected with the output end of the second output module.
6. The display panel according to claim 2,
the second output module further comprises a third node and a second output pull-down module, and a control end of the second output pull-down module is electrically connected with the third node; the second output pull-down module is used for providing a signal of a second constant voltage end to the output end of the second output module under the control of the third node voltage.
7. The display panel according to claim 6,
the second output module further comprises an auxiliary pull-down module, the auxiliary pull-down module is electrically connected with the third node, and the auxiliary pull-down module is used for stabilizing the potential of the third node under the control of the signal of the second clock signal end and the signal of the first clock signal end.
8. The display panel according to claim 7,
the auxiliary pull-down module comprises a sixth transistor, a seventh transistor and a first capacitor;
a control end of the sixth transistor is electrically connected with the second clock signal end, a first end of the sixth transistor is electrically connected with the second constant voltage end, and a second end of the sixth transistor is electrically connected with the third node;
a control end of the seventh transistor is electrically connected to the first clock signal end, a first end of the seventh transistor is electrically connected to the second constant voltage end, and a second end of the seventh transistor is electrically connected to the third node;
the first electrode plate of the first capacitor is electrically connected with the first clock signal end, and the second electrode plate of the first capacitor is electrically connected with the third node.
9. The display panel according to claim 6,
the second output module further comprises a first protection module, a control end of the first protection module is electrically connected with the second node, a first end of the first protection module is electrically connected with the second clock signal end, and a second end of the first protection module is electrically connected with the third node;
the first protection module is used for controlling the second output pull-down module to be closed at the moment when the second output pull-up module is opened.
10. The display panel according to claim 9,
the second output pull-down module comprises an eighth transistor, and the first protection module comprises a ninth transistor;
a control end of the eighth transistor is electrically connected with the third node, a first end of the eighth transistor is electrically connected with the second constant voltage end, and a second end of the eighth transistor is electrically connected with an output end of the second output module;
the control end of the ninth transistor is electrically connected with the second node, the first end of the ninth transistor is electrically connected with the second clock signal end, and the second end of the ninth transistor is electrically connected with the third node.
11. The display panel according to claim 2,
the control module comprises a first node control module and a second node control module;
the first node control module is electrically connected with the input end of the shift register, the third clock signal end, the second constant voltage end and the second node; the first node control module is configured to control a voltage of the first node according to a signal of an input end of the shift register, a signal of the third clock signal end, a signal of the second constant voltage end, and a signal of the second node; wherein, the signal of the third clock signal end and the signal of the first clock signal end have the same period;
the second node control module is electrically connected with the input end of the shift register, the first clock signal end and the first constant voltage end; the second node control module is used for controlling the voltage of the second node according to the signal of the input end of the shift register, the signal of the first clock signal end and the signal of the first constant voltage end.
12. The display panel according to claim 11,
the first node control module includes a tenth transistor and an eleventh transistor;
a control end of the tenth transistor is electrically connected to the third clock signal end, a first end of the tenth transistor is electrically connected to the second constant voltage end, and a second end of the tenth transistor is electrically connected to the first node;
a control end of the eleventh transistor is electrically connected with the second node, a first end of the eleventh transistor is electrically connected with an input end of the shift register, and a second end of the eleventh transistor is electrically connected with the first node;
the second node control module comprises a twelfth transistor, a thirteenth transistor and a fourteenth transistor;
the control end of the twelfth transistor is electrically connected with the third clock signal end, the first end of the twelfth transistor is electrically connected with the input end of the shift register, and the second end of the twelfth transistor is electrically connected with the second node;
a control end of the thirteenth transistor is electrically connected to the first clock signal end, a first end of the thirteenth transistor is electrically connected to a second end of the fourteenth transistor, and a second end of the thirteenth transistor is electrically connected to the second node;
a control terminal of the fourteenth transistor is electrically connected to the first node, and a first terminal of the fourteenth transistor is electrically connected to the first constant voltage terminal.
13. The display panel according to claim 1,
in one duty cycle of the shift register: the output timing of the low level signal of the first scan signal is subsequent to the output timing of the high level signal of the second scan signal.
14. The display panel according to claim 1,
in the drive circuit:
the input end of the 1 st stage of the shift register is electrically connected with the initial signal end;
the input end of the m-th stage of the shift register is electrically connected with the output end of the first output module of the m-1 th stage of the shift register, and m is an integer not less than 2.
15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.
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| WO2024174776A1 (en) * | 2023-02-22 | 2024-08-29 | 京东方科技集团股份有限公司 | Display substrate, drive method therefor and display apparatus |
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