CN110347621B

CN110347621B - FPGA connected with PSRAM memory and storage system

Info

Publication number: CN110347621B
Application number: CN201910546627.XA
Authority: CN
Inventors: 汤博先; 刘烈; 韩志伟
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2019-06-24
Filing date: 2019-06-24
Publication date: 2020-09-29
Anticipated expiration: 2039-06-24
Also published as: CN110347621A

Abstract

The invention provides an FPGA and a storage system connected with a PSRAM (programmable gate array) memory, which can enable a user layer to communicate with the PSRAM through the FPGA, wherein the FPGA comprises a controller and a physical layer interface module, the controller is connected with a user design module, the physical layer interface module is connected with the PSRAM memory, the controller receives a command from the user layer and provides a signal meeting the requirements of time sequence and sequence to an interface of the PSRAM memory through the physical layer interface module.

Description

FPGA connected with PSRAM memory and storage system

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an FPGA (field programmable gate array) connected with a PSRAM (programmable system random access memory) and a storage system.

Background

An IP Core (Intellectual Property Core) refers to a module provided by a certain party and designed in the form of a logic unit or a chip. Designers can design the logic of an application specific integrated circuit or a field programmable gate array on the basis of an IP core so as to shorten the design period and improve the design quality and efficiency.

The PSRAM (Pseudo static random access memory) is a RAM device which is similar to an SRAM (static random access memory) by adopting a DRAM (dynamic random access memory) process and technology, compared with the SRAM adopting 6T technology, the PSRAM adopts 1T +1C technology, the PSRAM has much larger capacity than the SRAM, lighter volume, much lower price than the SRAM, and more competitive selling price, and the I/O interface protocol of the PSRAM is the same as that of the SRAM. Compared with the DRAM, the PSRAM adopts Self-Refresh (Self-Refresh), can store data stored in the PSRAM without a Refresh circuit, has complex control logic of the DRAM, and needs to be refreshed and charged once every a period of time; otherwise, the internal data will disappear, so the PSRAM has higher performance, and the PSRAM has a more simplified data access interface than the DRAM. The problem of how to use PSRAM to replace DRAM to communicate with FPGA exists in the prior art.

Disclosure of Invention

The invention aims to provide an FPGA (field programmable gate array) connected with a PSRAM (programmable system random access memory) and a storage system so as to realize communication between the PSRAM and the FPGA.

The invention is realized in such a way that a first aspect of the invention provides an FPGA connected with a PSRAM memory, wherein the FPGA comprises a controller and a physical layer interface module, the controller is connected with a user design module, and the physical layer interface module is connected with the PSRAM memory;

the controller acquires a write data command, an address and write data information sent by the user design module, processes the write data command and the address and sends the processed write data command and address to the physical layer interface module, and processes the write data information and sends the processed write data information to the physical layer interface module;

and after caching the write data information according to the write data command, the physical layer interface module performs clock domain conversion on the write data information, the write data command and the address and then sends the write data information, the write data command and the address to the PSRAM.

The invention provides a storage system, which comprises an FPGA, a user design module and a PSRAM (programmable system random access memory), wherein the FPGA comprises a controller and a physical layer interface module, the controller is connected with the user design module, and the physical layer interface module is connected with the PSRAM.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of an FPGA connected to a PSRAM memory according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an FPGA connected to a PSRAM memory according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a storage system according to a second embodiment of the present invention;

FIG. 4 is a schematic diagram of a write timing sequence of the custom designed module burst length 32 in the memory system according to the second embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a write timing sequence on a memory port bus in a memory system according to a second embodiment of the present invention;

fig. 6 is a schematic read timing diagram of a user design module burst length 32 in a memory system according to a second embodiment of the present invention;

fig. 7 is a schematic view of a read timing on a memory port bus in a memory system according to a second embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In order to explain the technical means of the present invention, the following description will be given by way of specific examples.

As shown in fig. 1, the FPGA20 connected to the PSRAM memory according to an embodiment of the present invention includes a controller 201 and a physical layer interface module 202, where the controller 201 is connected to the user design module 10, and the physical layer interface module 202 is connected to the PSRAM memory 30.

When the user design module 10 writes data to the PSRAM memory 30 through the FPGA20, the controller 201 obtains a write data command, an address, and write data information sent by the user design module 10, processes the write data command and the address, sends the processed write data command and address to the physical layer interface module 202, and sends the processed write data information to the physical layer interface module 202;

the physical layer interface module 202 performs a cache process on the write data information according to the write data command, performs a clock domain conversion on the write data information, the write data command, and the address, and then sends the data to the PSRAM memory 30.

The controller 201 is configured to communicate with the user design module 10, acquire a write data command, an address, and write data information sent by the user design module 10, where the write data command includes a clock signal and a reset signal, the write data information includes a write data enable signal, a write mask signal, and write data, the controller 201 converts the address, performs logical computation on the write data enable signal and the write data mask signal, acquires the write enable signal, and sends the write enable signal to the physical layer interface module 202, and the physical layer interface module 202 buffers data, performs clock domain conversion on the write data command, and the address, and sends the write data command, and the write data mask signal to the PSRAM memory 30, so as to store the data in the PSRAM memory 30.

Compared with an SRAM (static random access memory) memory, the PSRAM memory 30 has the advantages of large capacity, light volume, low price and the like, and compared with a DRAM (dynamic random access memory) memory, the PSRAM memory 30 has the advantages of simple logic, few used interfaces, low cost control, small memory chip area, low power consumption and high-speed transmission, and based on the market requirements and the storage characteristics of the PSRAM, the invention provides the FPGA20 connected with the PSRAM memory 30, so that a user layer can be communicated with the PSRAM through the FPGA20, the FPGA20 comprises a controller 201 and a physical layer interface module 202, the controller 201 is connected with a user design module 10, the physical layer interface module 202 is connected with the PSRAM memory 30, the controller 201 receives commands from the user layer, and signals meeting the requirements of time sequence and sequence are provided for an interface of the PSRAM memory 30 through the physical layer interface module 202; the invention is suitable for the double-rate PSRAM memory, and achieves the purpose of high-speed transmission while controlling the cost, simplifying the control logic and reducing the chip area.

As one embodiment, as shown in FIG. 2, the controller 201 includes a command module 212 and a write data module 211.

The command module 212 acquires the write data command and the address sent by the user design module 10, converts the address, combines the write data command and the address, and sends the converted address and the write data command to the physical layer interface module 202;

the write data module 211 obtains a write data enable signal, a write data mask signal, and write data, performs logical calculation on the write data enable signal and the write data mask signal to obtain a write enable signal, and sends the write data and the write enable signal to the physical layer interface module 202.

The command module 212 mainly functions to receive and store an address and a command sent by a user, and the command module 212 converts the address sent by the user, maps the address into a ROW address, an Upper Column address and a lowerplumn address corresponding to the PSRAM, and splits and recombines the command and the address sent by the user, for example, orders and addresses are sorted according to a preset rule and sent to the physical layer interface module 202.

The write data module 211 is mainly configured to receive and store a write data enable signal, a write data signal, and a write mask signal sent by a user, perform logic calculation on the write data enable signal and the write data mask signal to obtain the write enable signal, provide write data for the physical layer interface module 202 according to currently stored write data and a write command received by the controller 201, a configured burst length, and the like, and transmit the write enable signal to the physical layer interface module 202. For a memory with a depth of M and a width of N, stored data of each address of addresses 0-M corresponds to a mask signal with a bit number of N bits, each bit of the mask signal corresponds to each bit of the stored data of the corresponding address, and the mask signal is used for masking bits of the stored data which do not rewrite the value of the corresponding register or bits of the stored data which need to rewrite the value of the corresponding register. If the mask is high effective, namely the bit with 1 mask is masked and the value of the corresponding bit register is not rewritten; similarly, if the mask is active low, the bits with a mask of 0 will be masked without overwriting the value of the corresponding bit register. The memory also has a write enable signal with a single bit wide for controlling whether the memory can write data. Because the write enable signal is single-bit, the binary representation of the write enable signal is 0 or 1, the write enable signal is low and effective, namely the memory can write data when the write enable signal is 0; the write enable signal is active high, i.e., the memory can write data when the write enable signal is 1. Before performing logic operation with a mask signal of multiple bits, firstly, a write enable signal is expanded to a write enable signal with the same bit width as the mask signal, and then the expanded write enable signal is subjected to logic operation with the mask signal to obtain a write enable signal with the same bit width as the mask signal. Specifically, if the mask signal and the write enable signal are both high-effective, the multi-bit mask signal is first bit-inverted, and then bit-and-operated with the expanded write enable signal, respectively, to obtain an expanded write enable signal with the same bit width as the write data and the mask signal.

The physical layer interface module 202 includes, as one embodiment, a data path module 221, a control path module 222, and an I/O logic module 223;

the control path module 222 obtains a write data command and an address, obtains a delay parameter according to the write data command, sends the delay parameter to the data path module 221, and sends the write data command and the address to the I/O logic module 223;

the data path module 221 performs cache processing on data in the write data information according to the delay parameter, and sends the write data information to the I/O logic module 223;

the I/O logic 223 performs clock domain conversion on the write data information, write data command, and address and sends the result to the PSRAM memory 30.

When writing data, the data path module 221 receives data and a write enable signal from the controller 201, performs buffering processing on the data according to the delay parameter, and then sends the data and the write enable signal to the I/O logic module 223.

The control path module 222 is a unidirectional path, receives the command and the address signal sent by the controller 201, cooperates with the data path module 221, processes the delay parameter of the write data, sends the delay parameter to the data path module 221, and sends the command to the I/O logic module 223.

The I/O logic module 223 mainly performs clock domain conversion on the data, command, and address signals transmitted from the data path module 221 and the control path module 222, and converts the data, command, and address signals from the clk _ x1 clock domain to the clk _ x2 clock domain, so as to generate signals required by the PSRAM memory 30.

As another embodiment, when the user design module 10 reads data from the PSRAM memory 30 through the FPGA20, the controller 201 acquires the read data command signal sent by the user design module 10, and sends the read data command signal to the physical layer interface module 202;

the physical layer interface module 202 receives the read data indication signal sent by the PSRAM memory 30, selects corresponding data from the data sent by the PSRAM memory 30 according to the read data indication signal, generates a read valid signal, sends the read valid signal and the selected data to the controller 201, and the controller 201 sends the selected data to the user design module 10.

Further, as shown in fig. 2, the controller 201 further includes a read data module 213;

the read data module 213 acquires the read data command signal sent by the user design module 10, and sends the read data command signal to the physical layer interface module 202;

the read data module 213 receives the read data when detecting the first read valid signal sent by the physical layer interface module 202, generates a second read valid signal according to the read data, and sends the second read valid signal to the user design module 10.

The main function of the read data module 213 is to receive the read data returned by the physical layer interface module 202 and send it to the user design module 10; when the physical layer interface module 202 returns read data, it provides corresponding read valid signal, the read data module 213 receives the read data when the read signal is valid, arranges the data and sends it to the user, and generates suitable read valid signal for the user design module 10, and the user design module 10 receives the read data when the read signal is valid.

During reading data, the control path module 222 in the physical layer interface module 202 obtains a read data command signal and sends the read data command signal to the PSRAM memory 30 through the I/O logic module 223.

The I/O logic block 223 receives the read data indication signal from the PSRAM memory 30 and sends the read data indication signal to the control path block 222.

The control path module 222 controls the data path module 221 to select corresponding data from the data transmitted by the PSRAM memory 30 according to the read data indication signal, generates a first read valid signal, and transmits the first read valid signal to the controller 201.

When reading data, the physical layer interface module 202 selects the data transferred by the I/O logic module 223 according to the data indication signal sent by the I/O logic module 223, and sends the data to the controller 201.

Further, the physical layer interface module 202 further includes an initialization module 224;

the initialization module 224 initializes the PSRAM granules upon power up according to the PSRAM protocol standard.

As shown in fig. 1, the storage system in the embodiment of the present invention includes an FPGA20, a user design module 10, and a PSRAM memory 30, where the FPGA20 includes a controller 201 and a physical layer interface module 202, the controller 201 is connected to the user design module 10, and the physical layer interface module 202 is connected to the PSRAM memory 30.

As shown in fig. 3, when writing data, the user design module 10 transmits a clock signal, a reset signal, write data information, and an address signal to the FPGA20, the FPGA20 transmits a clock signal, a differential signal, a chip select signal, a reset signal, and a data signal to the PSRAM memory 30, when reading data, the PSRAM memory 30 transmits a data signal and a data indication signal to the FPGA20, the FPGA20 receives data according to the data indication signal and transmits read data and a read data valid signal to the user design module 10, and the user design module 10 performs a read data operation when receiving the read data valid signal.

FIG. 4 is a diagram of a write timing diagram of the custom designed module 10 with an output length of 32, where CLK is a clock signal, _ addr is an address signal, CMD is a write command signal, CMD _ EN is a command valid signal, WR _ DATA is write DATA, and DATA _ MASK is a write MASK signal.

Fig. 5 is a schematic diagram of write timing on the port bus of the PSRAM memory, where PSRAM _ CK is a clock signal, PSRAM _ DQ is data, PSRAM _ CS _ N is a chip select signal, PSRAM _ RWDS is a write mask signal, and PSRAM _ RESET _ N is a RESET signal.

Fig. 6 is a schematic diagram of a read sequence of the user-designed module burst length 32, where CLK is a clock signal, CMD is a read command signal, CMD _ EN is a command VALID signal, RD _ DATA _ VALID is a read VALID signal, and RD _ DATA is read DATA.

Fig. 7 is a schematic diagram of a read sequence on a port bus of a PSRAM memory, where PSRAM _ CK is a clock signal, PSRAM _ DQ is data, PSRAM _ CS _ N is a chip select signal, PSRAM _ RWDS is a read indication signal, and PSRAM _ RESET _ N is a RESET signal.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. The FPGA is connected with a PSRAM memory and is characterized by comprising a controller and a physical layer interface module, wherein the controller is connected with a user design module, and the physical layer interface module is connected with the PSRAM memory;

the controller acquires a write data command, an address and write data information sent by the user design module, processes the write data command and the address and sends the processed write data command and the address to the physical layer interface module, and sends the processed write data information to the physical layer interface module, wherein the write data command comprises a clock signal and a reset signal, the write data information comprises a write data enable signal, a write data mask signal and write data, and the controller converts the address and performs logic calculation on the write data enable signal and the write data mask signal to acquire the write enable signal;

after caching the write data information according to the write data command, the physical layer interface module performs clock domain conversion on the write data information, the write data command and the address and then sends the write data information, the write data command and the address to the PSRAM;

the controller also comprises a data reading module;

the data reading module acquires a data reading command signal sent by the user design module and sends the data reading command signal to the physical layer interface module;

and the data reading module receives read data when detecting the first read effective signal sent by the physical layer interface module, generates a second read effective signal according to the read data, and sends the second read effective signal to the user design module.

2. The FPGA of claim 1, wherein: the controller acquires a read data command signal sent by the user design module and sends the read data command signal to the physical layer interface module;

the physical layer interface module receives the read data indicating signals sent by the PSRAM, selects corresponding data from the data sent by the PSRAM according to the read data indicating signals, generates read effective signals, sends the read effective signals and the selected data to the controller, and the controller sends the selected data to the user design module.

3. The FPGA of claim 2, wherein: the controller comprises a command module and a data writing module;

the command module acquires a write data command and an address sent by the user design module, converts the address, combines the write data command and the address and sends the converted address and the write data command to the physical layer interface module;

the data writing module acquires a data writing enable signal, a data writing mask signal and data writing, performs logic calculation on the data writing enable signal and the data writing mask signal to obtain a data writing enable signal, and sends the data writing enable signal and the data writing enable signal to the physical layer interface module.

4. The FPGA of claim 3, wherein: the command module maps the address to a ROW address, an Upper Column address and a Lower Column address corresponding to the PSRAM.

5. The FPGA of claim 3, wherein: the physical layer interface module comprises a data path module, a control path module and an I/O logic module;

the control path module acquires the write data command and the address, acquires a time delay parameter according to the write data command, sends the time delay parameter to the data path module, and sends the write data command and the address to the I/O logic module;

the data access module caches data in the write data information according to the time delay parameter and sends the write data information to the I/O logic module;

and the I/O logic module performs clock domain conversion on the write data information, the write data command and the address and then sends the data information, the write data command and the address to the PSRAM.

6. The FPGA of claim 5, wherein: the control channel module acquires the read data command signal and sends the read data command signal to the PSRAM through the I/O logic module;

the I/O logic module receives a read data indicating signal sent by the PSRAM and sends the read data indicating signal to the control channel module;

and the control path module controls the data path module to select corresponding data from the data sent by the PSRAM according to the read data indication signal, generates a read effective signal and sends the read effective signal to the controller.

7. The FPGA of claim 5, wherein: the physical layer interface module also comprises an initialization module;

the initialization module initializes the PSRAM particles when the power is on according to the PSRAM protocol standard.

8. A storage system comprising the FPGA of any one of claims 1 to 7, a custom design module, and a PSRAM memory, the FPGA comprising a controller and a physical layer interface module, the controller being coupled to the custom design module, the physical layer interface module being coupled to the PSRAM memory.