CN110347621A - The FPGA and storage system being connect with PSRAM memory - Google Patents
The FPGA and storage system being connect with PSRAM memory Download PDFInfo
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- CN110347621A CN110347621A CN201910546627.XA CN201910546627A CN110347621A CN 110347621 A CN110347621 A CN 110347621A CN 201910546627 A CN201910546627 A CN 201910546627A CN 110347621 A CN110347621 A CN 110347621A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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Abstract
The invention proposes a kind of FPGA connecting with PSRAM memory and storage systems, family layer is able to use to be in communication with each other by FPGA and PSRAM, FPGA includes controller and physical layer interface module, controller connects user and designs module, physical layer interface module connects PSRAM memory, controller receives the order from client layer, the signal for meeting timing and sequence requirement is provided by physical layer interface module to the interface of PSRAM memory, the present invention with PSRAM memory by connecting, it can control product cost, simplified control logic and reduction chip area, achieve the purpose that high-speed transfer simultaneously.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of FPGA connecting with PSRAM memory and storages
System.
Background technique
IP kernel (Intellectual Property Core, IP core) refers to that the form that one party provides is logic
The module of unit, chip design.Designer can carry out specific integrated circuit or field programmable logic based on IP kernel
The logical design of gate array, to shorten the design cycle, improve designing quality and efficiency.
PSRAM(Pseudo static random access memory, pseudo-static random access memory) it is using DRAM
Technique and technology, realize and be similar to the same RAM device of SRAM, compared with SRAM is using the technology of 6T, PSRAM using
The technology of 1T+1C, PSRAM capacity ratio SRAM is much larger, and volume is more light and handy, and price ratio SRAM is cheap very much, and price has more
Competitiveness, and the I/O interface protocol of PSRAM is identical as SRAM.Compared with DRAM, PSRAM is using voluntarily refreshing
(Self-Refresh), the data of its storage inside can be saved by not needing refresh circuit, and DRAM control logic is complicated, every
For a period of time, refresh charge primary；Otherwise internal data can disappear, therefore PSRAM has higher performance, and
PSRAM possesses the data access interface more simplified than DRAM.It how exists in the prior art using PSRAM memory substitution DRAM
The problem of being communicated with FPGA.
Summary of the invention
The purpose of the present invention is to provide a kind of FPGA connecting with PSRAM memory and storage systems, to realize PSRAM
It is communicated between memory and FPGA.
The invention is realized in this way first aspect present invention provides a kind of FPGA connecting with PSRAM memory, it is described
FPGA includes controller and physical layer interface module, and the controller connection user designs module, the physical layer interface module
Connect PSRAM memory；
What the controller obtained that the user designs that module sends writes data command, address and writes data information, will be described
Write data command and the address handled after be sent to the physical layer interface module, and write data information is carried out
The physical layer interface module is sent to after processing；
It, will be described after the physical layer interface module carries out caching process to write data information according to write data order
It writes after data information, write data order and the address carry out clock domain conversion and is sent to the PSRAM memory.
Second aspect of the present invention provides a kind of storage system, the storage system include FPGA, user design module and
PSRAM memory, the FPGA include controller and physical layer interface module, and the controller connection user designs module, institute
State physical layer interface module connection PSRAM memory.
The invention proposes a kind of FPGA connecting with PSRAM memory and storage systems, are able to use family layer and pass through
FPGA is in communication with each other with PSRAM, and FPGA includes controller and physical layer interface module, and controller connects user and designs mould
Block, physical layer interface module connect PSRAM memory, and controller receives the order from client layer, passes through physical layer interface mould
Block provides the signal for meeting timing and sequence requirement to the interface of PSRAM memory, and the present invention with PSRAM memory by connecting
It connects, can control product cost, simplified control logic and reduces chip area, while achieving the purpose that high-speed transfer.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram for FPGA connecting with PSRAM memory that the embodiment of the present invention one provides；
Fig. 2 is a kind of concrete structure schematic diagram for FPGA connecting with PSRAM memory that the embodiment of the present invention one provides；
Fig. 3 is a kind of structural schematic diagram of storage system provided by Embodiment 2 of the present invention；
Fig. 4 is that the timing of writing of user's design module burst-length 32 in a kind of storage system provided by Embodiment 2 of the present invention is shown
It is intended to；
Fig. 5 is to write time diagram in the port memory bus in a kind of storage system provided by Embodiment 2 of the present invention；
Fig. 6 is that the reading timing of user's design module burst-length 32 in a kind of storage system provided by Embodiment 2 of the present invention is shown
It is intended to；
Fig. 7 is the reading time diagram in the port memory bus in a kind of storage system provided by Embodiment 2 of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In order to illustrate technical solution of the present invention, the following is a description of specific embodiments.
The embodiment of the present invention one provides a kind of FPGA20 connecting with PSRAM memory, as shown in Figure 1, FPGA 20 includes
Controller 201 and physical layer interface module 202, controller 201 connect user and design module 10, and physical layer interface module 202 connects
Connect PSRAM memory 30.
When user, which designs module 10, writes data to PSRAM memory 30 by FPGA20, controller 201 obtains user and sets
What meter module 10 was sent writes data command, address and writes data information, will write data command and address handled after send
To physical layer interface module 202, and it will write after data information is handled and be sent to physical layer interface module 202；
After physical layer interface module 202 is according to data command is write to data information progress caching process is write, data information will be write, write
Data command and address are sent to PSRAM memory 30 after carrying out clock domain conversion.
Wherein, controller 201 is used to design module 10 with user and communicate, and obtains user and designs writing for the transmission of module 10
Data command, address and data information is write, writing data command includes clock signal and reset signal, and writing data information includes writing
Data enable signal writes mask signal and writes data, and controller 201 converts address, writes data enable signal to after
Logic calculation acquisition write enable signal is carried out with data masking signals are write, and is sent to physical layer interface module 202, physical layer connects
Mouth mold block 202 to data carry out cache and data information will be write, write data command and address carry out clock domain conversion after send
To PSRAM memory 30, to store data in PSRAM memory 30.
PSRAM memory 30 compared to SRAM memory has that capacity is big, volume is light and handy and advantages and the phase such as cheap
Than the voluntarily refreshing of DRAM memory and simplified interface advantage, and PSRAM memory 30 is simple with logic, uses interface
Less, cost control is low, small, low in energy consumption, high-speed transfer the advantage of storage chip area, based on the above-mentioned market demand and PSRAM
Storage characteristics, the invention proposes a kind of FPGA 20 connecting with PSRAM memory 30, are able to use family layer and pass through FPGA 20
It is in communication with each other with PSRAM, FPGA 20 includes controller 201 and physical layer interface module 202, and controller 201 connects user
Module 10 is designed, physical layer interface module 202 connects PSRAM memory 30, and controller 201 receives the order from client layer,
The signal for meeting timing and sequence requirement is provided by physical layer interface module 202 to the interface of PSRAM memory 30；And this hair
It is bright to be suitable for Double Data Rate PSRAM memory, while controlling cost, simplified control logic and reducing chip area, reach
The purpose of high-speed transfer.
As an implementation, as shown in Fig. 2, controller 201 includes command module 212 and writes data module 211.
What the acquisition user's design module 10 of command module 212 was sent writes data command and address, is converted simultaneously to address
Physical layer interface module 202 is sent to after data command is combined with writing；
It writes the acquisition of data module 211 to write data enable signal, write data masking signals and write data, to writing data enable signal
Write enable signal is obtained with writing after data masking signals carry out logic calculation, and data will be write and write enable signal is sent to physics
Layer interface module 202.
Wherein, 212 major function of command module is to receive and store address and the order of user's transmission, command module 212
The address sent to user is converted, and the corresponding address ROW PSRAM, the address Upper Column, Lower are mapped as
The address Column, and the order sent to user and address split, recombinate, for example, according to preset rules sequentialize commands and
Address is simultaneously sent to physical layer interface module 202.
Wherein, writing 211 major function of data module is to receive and store writing data enable signal, writing data for user's transmission
Signal and mask signal is write, obtains writing enabled letter to writing data enable signal and writing after data masking signals carry out logic calculation
Number, and according to write order, the burst-length of configuration etc. writing data and received with controller 201 stored at present, it is physical layer
Data are write in the offer of interface module 202, and transmit write enable signal to physical layer interface module 202.It wherein, is M wide for depth
Degree is for the memory of N, and the mask that the corresponding bit number of the storing data of each address in 0~M of address is N is believed
Number, each bit of mask signal corresponds to each bit of appropriate address store data inside, for covering up in storing data
The bit of the value of corresponding registers is not rewritten or need to rewrite the bit of the value of corresponding registers.If mask is high effectively, that is, cover
The value that the bit that code is 1 can be covered up without rewriting corresponding bits register；Similarly, if mask is low effectively, i.e., mask is 0
Bit can by be covered up without rewrite corresponding bits register value.It is that writing for single-bit is enabled that memory, which also has a bit wide,
Signal, for controlling whether memory can write data.Since write enable signal is single-bit, be represented in binary as 0 or
1, write enable signal is low effective, i.e., memory can write data when write enable signal is 0；Write enable signal is Gao Youxiao, i.e.,
Memory can write data when write enable signal is 1.It is first before it will carry out logical operation with the mask signal of more bits
First, write enable signal is extended to write enable signal identical with mask signal bit wide, write enable signal is extended to mask letter
After number bit wide is identical, then by after extension write enable signal and mask signal carry out logical operation, obtain and mask signal bit wide
Identical write enable signal.Specifically, as mask signal and write enable signal be it is high effectively, then first by more bit-masks signals
Step-by-step negates, then respectively with after extension write enable signal carry out step-by-step and operation, obtain one extension with write data and
The write enable signal of mask signal same bit-width.
As an implementation, physical layer interface module 202 includes data path module 221, control access module 222
And I/O logic module 223；
Data command and address are write in the acquisition of control access module 222, obtain delay parameter according to data command is write, and by time delay
Parameter is sent to data path module 221, and will write data command and address is sent to I/O logic module 223；
After data path module 221 carries out caching process to the data write in data information according to delay parameter, and data will be write
Information is sent to I/O logic module 223；
I/O logic module 223 will write data information, write data command and address carry out clock domain conversion after be sent to PSRAM
Memory 30.
Wherein, data path module 221 receives data and write enable signal from controller 201 when writing data, and
Caching process is carried out to data according to delay parameter, then sends I/O logic module 223 for data and write enable signal.
Wherein, control access module 222 is one-way passage, the order and address signal that reception controller 201 is sent, and with
Data path module 221 cooperates, and the delay parameter of process write data is simultaneously sent to data path module 221, and order is sent
To I/O logic module 223.
Wherein, I/O logic module 223 is mainly the number passed over to data path module 221 and control access module 222
According to, order, address signal carry out clock domain conversion, clk_x2 clock domain is transformed into from clk_x1 clock domain, to generate
The signal that PSRAM memory 30 needs.
As another embodiment, when user, which designs module 10, reads data from PSRAM memory 30 by FPGA20,
Controller 201 obtains user and designs the reading data command signal that module 10 is sent, and will read data command signal and is sent to physical layer
Interface module 202；
Physical layer interface module 202 receives the reading data indication signal that PSRAM memory 30 is sent, according to reading data indication signal
Corresponding data are selected in the data that PSRAM memory 30 is sent, and generate reading useful signal, useful signal and selected will be read
The data selected are sent to controller 201, and selected data are sent to user and design module 10 by controller 201.
Further, as indicated with 2, controller 201 further includes data reading module 213；
Data reading module 213 obtains user and designs the reading data command signal that module 10 is sent, and will read data command signal and sends
To physical layer interface module 202；
Data reading module 213 detects that physical layer interface module 202 is sent first reads to receive reading data when useful signal, and root
The second reading useful signal is generated according to data are read, and the second reading useful signal is sent to user and designs module 10.
Wherein, 213 major function of data reading module be receive physical layer interface module 202 return reading data, and by its
It is sent to user and designs module 10；Physical layer interface module 202 can provide corresponding reading useful signal when returning back read data,
Data reading module 213 is received when read signal is effective reads data, user will be sent to after data preparation, and design module for user
10 generate suitable reading useful signal, and user designs module 10 and receives reading data when read signal is effective.
During reading data, the control access module 222 in physical layer interface module 202, which obtains, reads data command letter
Number, data command signal will be read by I/O logic module 223 and be sent to PSRAM memory 30.
I/O logic module 223 receives the reading data indication signal that PSRAM memory 30 is sent, and is sent to control access
Module 222.
Control access module 222 controls data path module 221 in the hair of PSRAM memory 30 according to data indication signal is read
Corresponding data are selected in the data sent, and generates first and reads useful signal, and the first reading useful signal is sent to controller
201。
Wherein, when reading data, physical layer interface module 202 is indicated according to the data that I/O logic module 223 sends over
Signal sends the data to controller 201 data that select it to pass over.
Further, physical layer interface module 202 further includes initialization module 224；
Initialization module 224 initializes PSRAM particle when powering on according to PSRAM consensus standard.
A kind of storage system of two-body of the embodiment of the present invention, as shown in Figure 1, storage system includes FPGA20, user's design
Module 10 and PSRAM memory 30, FPGA20 include controller 201 and physical layer interface module 202, and controller 201 connects
User designs module 10, and physical layer interface module 202 connects PSRAM memory 30.
As shown in figure 3, when writing data, user design module 10 to FPGA20 tranmitting data register signal, reset signal, write number
It is believed that breath and address signal, FPGA20 believes to 30 tranmitting data register signal of PSRAM memory, differential signal, chip selection signal, reset
Number and data-signal, when reading data, PSRAM memory 30 sends data-signal and data indication signal to FPGA20,
FPGA20 receives data according to data indication signal, and designs the transmission of module 10 reading data to user and read data valid signal,
User designs module 10 and carries out reading data manipulation when receiving and reading data valid signal.
It is 32 to write time diagram as Fig. 4 designs module 10 to export length for user, wherein CLK is clock signal, _
Addr is address signal, and CMD is write command signal, and CMD_EN is order useful signal, and WR_DATA is to write data, DATA_MASK
To write mask signal.
If Fig. 5 is to write time diagram in PSRAM port memory bus, wherein PSRAM_CK is clock signal,
PSRAM_DQ is data, and PSRAM_CS_N is chip selection signal, and PSRAM_RWDS is to write mask signal, and PSRAM_RESET_N is multiple
Position signal.
As Fig. 6 designs for user the reading time diagram of module burst-length 32, wherein CLK is clock signal, and CMD is
Read command signal, CMD_EN are order useful signal, and RD_DATA_VALID is to read useful signal, and RD_DATA is reading
According to.
If Fig. 7 is the reading time diagram in PSRAM port memory bus, wherein PSRAM_CK is clock signal,
PSRAM_DQ is data, and PSRAM_CS_N is chip selection signal, and PSRAM_RWDS is to read indication signal, and PSRAM_RESET_N is multiple
Position signal.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution should all include
Within protection scope of the present invention.
Claims (9)
1. a kind of FPGA being connect with PSRAM memory, which is characterized in that the FPGA includes controller and physical layer interface mould
Block, the controller connection user design module, and the physical layer interface module connects PSRAM memory；
What the controller obtained that the user designs that module sends writes data command, address and writes data information, will be described
Write data command and the address handled after be sent to the physical layer interface module, and write data information is carried out
The physical layer interface module is sent to after processing；
It, will be described after the physical layer interface module carries out caching process to write data information according to write data order
It writes after data information, write data order and the address carry out clock domain conversion and is sent to the PSRAM memory.
2. the FPGA according to claim 1, it is characterised in that: the controller obtains the user and designs module transmission
Reading data command signal, the reading data command signal is sent to the physical layer interface module；
The physical layer interface module receives the reading data indication signal that the PSRAM memory is sent, according to the reading data
Indication signal selects corresponding data in the data that the PSRAM memory is sent, and generates reading useful signal, by the reading
Useful signal and selected data are sent to the controller, and selected data are sent to the user by the controller
Design module.
3. FPGA according to claim 2, it is characterised in that: the controller includes command module and writes data module；
What the command module obtained that the user designs that module sends writes data command and address, converts to the address
And the physical layer interface module is sent to after being combined with write data order；
The acquisition of write data module writes data enable signal, writes data masking signals and writes data, makes to write data
Can signal and write data mask signal carry out obtaining write enable signal after logic calculation, and by write data and described write
Enable signal is sent to the physical layer interface module.
4. FPGA according to claim 3, it is characterised in that: the address of cache is described by the command module
The corresponding address ROW of PSRAM memory, the address Upper Column and the address Lower Column.
5. FPGA according to claim 3, it is characterised in that: the controller further includes data reading module；
The data reading module obtains the user and designs the reading data command signal that module is sent, and the reading data command is believed
Number it is sent to the physical layer interface module；
The data reading module detects that the physical layer interface module is sent first reads to receive reading data when useful signal, and
Second is generated according to the reading data and reads useful signal, and the second reading useful signal is sent to the user and designs mould
Block.
6. FPGA according to claim 3, it is characterised in that: the physical layer interface module include data path module,
Control access module and I/O logic module；
The control access module obtains write data order and the address, obtains time delay according to write data order
Parameter, and the delay parameter is sent to the data path module, and by write data order and the address
It is sent to the I/O logic module；
After the data path module carries out caching process to the data in write data information according to the delay parameter, and
Write data information is sent to the I/O logic module；
Write data information, write data order and the address are carried out clock domain conversion by the I/O logic module
After be sent to the PSRAM memory.
7. FPGA according to claim 6, it is characterised in that: the control access module obtains the reading data command letter
Number, the reading data command signal is sent to the PSRAM memory by the I/O logic module；
The I/O logic module receives the reading data indication signal that the PSRAM memory is sent, and it is logical to be sent to the control
Road module；
The control access module controls the data path module according to the reading data indication signal and stores in the PSRAM
Corresponding data are selected in the data that device is sent, and generate reading useful signal, the reading useful signal is sent to the control
Device.
8. FPGA according to claim 6, it is characterised in that: the physical layer interface module further includes initialization module；
The initialization module initializes PSRAM particle when powering on according to PSRAM consensus standard.
9. a kind of storage system, which is characterized in that the storage system includes FPGA, user designs module and PSRAM is stored
Device, the FPGA include controller and physical layer interface module, and the controller connection user designs module, and the physical layer connects
Mouth mold block connects PSRAM memory.
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| CN110347621B (en) | 2020-09-29 |
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