CN109450435B - LVDS interface circuit - Google Patents
LVDS interface circuit Download PDFInfo
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- CN109450435B CN109450435B CN201811388791.4A CN201811388791A CN109450435B CN 109450435 B CN109450435 B CN 109450435B CN 201811388791 A CN201811388791 A CN 201811388791A CN 109450435 B CN109450435 B CN 109450435B
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- nmos tube
- pmos tube
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- RFVBBELSDAVRHM-UHFFFAOYSA-N 9,10-dinaphthalen-2-yl-2-phenylanthracene Chemical compound C1=CC=CC=C1C1=CC=C(C(C=2C=C3C=CC=CC3=CC=2)=C2C(C=CC=C2)=C2C=3C=C4C=CC=CC4=CC=3)C2=C1 RFVBBELSDAVRHM-UHFFFAOYSA-N 0.000 claims abstract description 14
- PMAYSDOKQDPBDC-UHFFFAOYSA-N [3-hexadecanoyloxy-2-(2-phenylacetyl)oxypropyl] hexadecanoate Chemical compound CCCCCCCCCCCCCCCC(=O)OCC(COC(=O)CCCCCCCCCCCCCCC)OC(=O)CC1=CC=CC=C1 PMAYSDOKQDPBDC-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000005540 biological transmission Effects 0.000 claims abstract description 12
- 230000000630 rising effect Effects 0.000 claims abstract description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses an LVDS interface circuit, which comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the sources of the first PMOS tube and the second PMOS tube are connected with a power supply VDDIO; the grid electrodes of the first PMOS tube and the second PMOS tube receive a control signal BiasP through a switch; the grid electrodes of the first PMOS tube and the second PMOS tube are connected with a power supply VDDIO through switches; the source electrodes of the first NMOS tube and the second NMOS tube are grounded VSSIO; the grid electrodes of the first NMOS tube and the second NMOS tube receive a control signal BiasN through a switch; and the grid electrodes of the first NMOS tube and the second NMOS tube are connected with the ground VSSIO through a switch. The invention realizes the 50 ohm impedance on the rising and falling edge of PADP/PADN, matches with the impedance of the transmission line, and reduces the reflection.
Description
Technical Field
The present invention relates to LVDS interface circuits.
Background
LVDS (Low Voltage Differential Signaling) is a low voltage differential signaling technology interface. In the LVDS interface circuit, the signal integrity problem becomes an important problem to be solved because the higher the speed of signal transmission is, the longer the cable is. As shown in fig. 2, in the high-speed LVDS interface circuit with a conventional structure, the constant current sources E, F controlled by the signals BiasP and BiasN are respectively arranged at the top and bottom, the switch pairs ABCD and AB/CD controlled by the signals DIN and DINB are alternately opened in the middle, when the differential signal pairs PADP/PADN and AB are opened, the output impedance is AE in series seen from the output terminal PADP, and the constant current source E is controlled in the saturation region by the BiasP and is high-impedance. Similarly, the output impedance seen from the output terminal PADN is also high, and is not matched with the 50 ohm characteristic impedance of the cable, and the reflection is serious.
Disclosure of Invention
The invention aims to provide an LVDS interface circuit, which realizes the impedance of 50 ohms on the rising and falling edges of PADP/PADN, and the impedance is matched with the impedance of a transmission line, so that the reflection is reduced.
The technical scheme for achieving the purpose is as follows:
an LVDS interface circuit comprises a first PMOS tube (P-type metal oxide semiconductor field effect tube), a second PMOS tube, a first NMOS tube (N-type metal oxide semiconductor field effect tube) and a second NMOS tube,
the source electrodes of the first PMOS tube and the second PMOS tube are connected with a power supply VDDIO;
the grid electrodes of the first PMOS tube and the second PMOS tube receive a control signal BiasP through a switch;
the grid electrodes of the first PMOS tube and the second PMOS tube are connected with a power supply VDDIO through switches;
the source electrodes of the first NMOS tube and the second NMOS tube are grounded VSSIO;
the grid electrodes of the first NMOS tube and the second NMOS tube receive a control signal BiasN through a switch;
the grid electrodes of the first NMOS tube and the second NMOS tube are connected with the ground VSSIO through a switch;
the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube to form an output end PADP;
and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube to form an output end PADN.
Preferably, when the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, or the second NMOS transistor is turned on, the power supply VDDIO or the ground VSSIO is turned off;
the first PMOS tube, the second PMOS tube, the first NMOS tube or the second NMOS tube is opened when the control signal BiasP or the control signal BiasN is connected.
Preferably, the control signal BiasP is formed by superimposing a power supply VDDIO signal and a biasp_pre signal via two transmission gates;
the control signal BiasN is formed by superimposing the power supply VDDIO signal and the biasn_pre signal via two transmission gates.
Preferably, the control signal of the transmission gate receiving the power supply VDDIO signal is cntlA, where cntlA is 1 at the falling edge of the output terminal PADP or the rising edge of the output terminal PADN, and at this time, the falling edge of the output terminal PADP or the rising edge of the output terminal PADN generates 50 ohm impedance.
Preferably, the biasp_pre signal or the biasn_pre signal is 3.5ma.
The beneficial effects of the invention are as follows: the invention realizes the 50 ohm impedance on the rising edge of PADP/PADN and the impedance matching of the transmission line by the effective structural design, reduces the reflection and simultaneously realizes the pre-emphasis function aiming at the problems of signal integrity and the like in the high-speed lvds interface.
Drawings
Fig. 1 is a circuit diagram of an LVDS interface circuit of the present invention;
fig. 2 is a circuit diagram of a high-speed LVDS interface circuit of a conventional structure;
FIG. 3 is a circuit diagram of the generation of the control signal BiasN in the present invention;
fig. 4 is a waveform diagram of the control signal BiasN according to the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Referring to fig. 1, the LVDS interface circuit of the present invention includes a first PMOS MP1, a second PMOS MP2, a first NMOS MN1 and a second NMOS MN2.
The source electrodes of the first PMOS tube MP1 and the second PMOS tube MP2 are connected with a power supply VDDIO. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 receive the control signal BiasP through the switch. The grid electrodes of the first PMOS tube MP1 and the second PMOS tube MP2 are connected with a power supply VDDIO through a switch.
The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded VSSIO. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 receive the control signal BiasN through the switch. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to the ground VSSIO through a switch.
The drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube MN1 to form an output end PADP.
The drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2 to form an output end PADN.
The first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, or the second NMOS transistor MN2 is turned off when the power supply VDDIO or the ground VSSIO is turned on. When the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, or the second NMOS transistor MN2 is turned on the control signal BiasP or the control signal BiasN. As shown in fig. 1, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, and the second PMOS transistor MP2 and the first NMOS transistor MN1 are turned off.
The control signal BiasP is formed by superimposing the power supply VDDIO signal and the biasp_pre signal via two transmission gates. The control signal BiasN is formed by superimposing the power supply VDDIO signal and the biasn_pre signal via two transmission gates. Taking BiasN as an example, as shown in fig. 3, the control signal of the transmission gate receiving the VDDIO signal is cntlA, cntlA is 1 at the falling edge of the output terminal PADP or the rising edge of the output terminal PADN, the control signal BiasN generates the area of area in the BiasN waveform in fig. 4, then cntlA is turned off, biasN is stabilized to biasn_pre, and the second NMOS transistor MN2 thus generates the required 50 ohm impedance in the linear area of area first, that is, 50 ohm impedance at the rising edge of PADP and PADN, and forms a pre-emphasis waveform, and then stably generates 3.5mA of biasn_pre. The pre-emphasis waveform is used to increase the high frequency component of the signal.
In fig. 3, cntlA and cntlAB are differential signal pairs, and DIN and DINB are differential signal pairs.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the present invention, and thus all equivalent technical solutions should be defined by the claims.
Claims (2)
1. An LVDS interface circuit is characterized by comprising a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein,
the source electrodes of the first PMOS tube and the second PMOS tube are connected with a power supply VDDIO;
the grid electrodes of the first PMOS tube and the second PMOS tube receive a control signal BiasP through a switch;
the grid electrodes of the first PMOS tube and the second PMOS tube are connected with a power supply VDDIO through switches;
the source electrodes of the first NMOS tube and the second NMOS tube are grounded VSSIO;
the grid electrodes of the first NMOS tube and the second NMOS tube receive a control signal BiasN through a switch;
the grid electrodes of the first NMOS tube and the second NMOS tube are connected with the ground VSSIO through a switch;
the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube to form an output end PADP;
the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube to form an output end PADN;
the first PMOS tube, the second PMOS tube, the first NMOS tube or the second NMOS tube is closed when the power supply VDDIO or the ground VSSIO is connected;
the first PMOS tube, the second PMOS tube, the first NMOS tube or the second NMOS tube is opened when the control signal BiasP or the control signal BiasN is connected;
the control signal BiasP is formed by superposing a power supply VDDIO signal and a BiasP_pre signal through two transmission gates;
the control signal BiasN is formed by superposing a power supply VDDIO signal and a BiasN_pre signal through two transmission gates;
the control signal of the transmission gate receiving the power supply VDDIO signal is cnt lA, where cnt lA is 1 at the falling edge of the output terminal PADP or the rising edge of the output terminal PADN, and at this time, the falling edge of the output terminal PADP or the rising edge of the output terminal PADN generates 50 ohm impedance.
2. The LVDS interface circuit of claim 1, wherein the biasp_pre signal or the biasn_pre signal is 3.5ma.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811388791.4A CN109450435B (en) | 2018-11-21 | 2018-11-21 | LVDS interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811388791.4A CN109450435B (en) | 2018-11-21 | 2018-11-21 | LVDS interface circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109450435A CN109450435A (en) | 2019-03-08 |
| CN109450435B true CN109450435B (en) | 2024-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811388791.4A Active CN109450435B (en) | 2018-11-21 | 2018-11-21 | LVDS interface circuit |
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Citations (12)
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| US6288581B1 (en) * | 2001-01-05 | 2001-09-11 | Pericom Semiconductor Corp. | Low-voltage differential-signalling output buffer with pre-emphasis |
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| JP2006060416A (en) * | 2004-08-18 | 2006-03-02 | Sony Corp | Interface circuit |
| WO2006117860A1 (en) * | 2005-04-28 | 2006-11-09 | Thine Electronics, Inc. | Differential driving circuit and electronic device incorporating the same |
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| CN101394377A (en) * | 2008-09-24 | 2009-03-25 | 硅谷数模半导体（北京）有限公司 | Pre-loading device and low voltage differential signal transmitter |
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| US7208993B2 (en) * | 2003-03-11 | 2007-04-24 | Texas Instruments Incorporated | Input current leakage correction for multi-channel LVDS front multiplexed repeaters |
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2018
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| CN109450435A (en) | 2019-03-08 |
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Address after: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
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