CN108062938B

CN108062938B - Shifting register unit and driving method thereof, grid driving circuit and display device

Info

Publication number: CN108062938B
Application number: CN201810012061.8A
Authority: CN
Inventors: 徐飞; 吕磊
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2018-01-05
Filing date: 2018-01-05
Publication date: 2020-06-19
Anticipated expiration: 2038-01-05
Also published as: CN108062938A

Abstract

The disclosure provides a shift register unit, a driving method thereof, a grid driving circuit and a display device, and relates to the technical field of display. The shift register unit includes: an input module responding to an input signal to transmit a first power signal to a pull-up node; the reset module responds to the delayed reset signal to transmit a second power supply signal to the pull-up node; the output module responds to the signal of the pull-up node to transmit the clock signal to the signal output end; the first pull-down control module responds to a signal of the pull-up node to transmit a third power supply signal to the pull-down node; the second pull-down control module responds to the fourth power supply signal to transmit the fourth power supply signal to the pull-down node; the pull-down module responds to the signal of the pull-down node to transmit a third power supply signal to the pull-up node and the signal output end respectively; the shift register unit is a shift register unit corresponding to the touch scanning line. The method and the device can solve the problem that the gate driving signal corresponding to the touch scanning line is slowly reduced.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.

Background

A TFT-LCD (Thin Film Transistor-Liquid Crystal Display) displays an image in a progressive scanning manner using an M × N matrix of pixels. The display driver of the TFT-LCD mainly includes a gate driver and a data driver, wherein the gate driver can convert a clock signal through a shift register to be applied to gate lines of the liquid crystal display panel, so that a gate driving signal can be output to the corresponding gate lines to implement a progressive scanning function thereof.

In applications such as 120Hz TDDI (Touch and Display Driver integration) products, Touch signal lines are added to specific rows of the gate Driver circuit, which results in several rows of shift register units to be kept in the current state during the Touch phase until the Touch end can resume normal operation. However, during this period, the pull-up node is not sufficiently opened due to leakage generated by the charge capacitor in the holding device, such as the shift register unit, and therefore, the waveform of the gate driving signal corresponding to the row clock signal is distorted; meanwhile, the pull-down node does not reach the working voltage, that is, the whole shift register unit cannot perform noise release action, but the output transistor is turned off, so that the signal output end at the moment is in a floating state, and the waveform of the gate driving signal is more seriously distorted, such as slow decline.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a shift register unit, a driving method thereof, a gate driving circuit, and a display device, so as to solve the problem that a gate driving signal of the shift register unit corresponding to a touch scan line is slowly decreased.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a shift register unit including:

the input module is connected with the input signal end, the first power supply signal end and the pull-up node and used for responding to an input signal so as to transmit the first power supply signal to the pull-up node;

the reset module is connected with a reset signal end, a second power signal end, a third power signal end and the pull-up node and comprises a reset unit and a delay unit, the delay unit is connected between the reset signal end and the third power signal end to delay a reset signal, and the reset unit is used for responding to the delayed reset signal to transmit a second power signal to the pull-up node;

the output module is connected with the pull-up node, the clock signal end and the signal output end and used for responding to the voltage signal of the pull-up node so as to transmit the clock signal to the signal output end;

the first pull-down control module is connected with the pull-up node, the third power signal end and the pull-down node and used for responding to a voltage signal of the pull-up node so as to transmit a third power signal to the pull-down node;

the second pull-down control module is connected with a fourth power signal end and the pull-down node and used for responding to a fourth power signal so as to transmit the fourth power signal to the pull-down node;

the pull-down module is connected with the pull-down node, the third power signal terminal, the pull-up node and the signal output terminal, and is used for responding to a voltage signal of the pull-down node to transmit the third power signal to the pull-up node and the signal output terminal respectively;

the shift register unit is a shift register unit corresponding to the touch scanning line.

In an exemplary embodiment of the present disclosure, the reset unit includes a reset switch element, a control terminal of the reset switch element is connected to the reset signal terminal, a first terminal of the reset switch element is connected to the second power signal terminal, and a second terminal of the reset switch element is connected to the pull-up node;

the delay unit includes a delay capacitor connected between the reset signal terminal and the third power signal terminal.

In an exemplary embodiment of the present disclosure, the input module includes an input switch element, a control end of the input switch element is connected to the input signal end, a first end of the input switch element is connected to the first power signal end, and a second end of the input switch element is connected to the pull-up node.

In an exemplary embodiment of the present disclosure, the output module includes an output switching element and a charging capacitor;

the control end of the output switch element is connected with the pull-up node, the first end of the output switch element is connected with the clock signal end, and the second end of the output switch element is connected with the signal output end;

the charging capacitor is connected between the pull-up node and the signal output end.

In an exemplary embodiment of the present disclosure, the first pull-down control module includes a first control switching element and a second control switching element;

the control end of the first control switch element is connected with the pull-up node, the first end of the first control switch element is connected with the third power signal end, and the second end of the first control switch element is connected with the pull-down control node;

and the control end of the second control switch element is connected with the pull-up node, the first end of the second control switch element is connected with the third power signal end, and the second end of the second control switch element is connected with the pull-down node.

In one exemplary embodiment of the present disclosure, the second pull-down control module includes a third control switching element and a fourth control switching element;

the control end and the first end of the third control switch element are connected with the fourth power signal end, and the second end of the third control switch element is connected with the pull-down control node;

and the control end of the first control switch element is connected with the pull-down control node, the first end of the first control switch element is connected with the fourth power signal end, and the second end of the first control switch element is connected with the pull-down node.

In an exemplary embodiment of the present disclosure, the pull-down module includes a first pull-down switching element and a second pull-down switching element;

the control end of the first pull-down switch element is connected with the pull-down node, the first end of the first pull-down switch element is connected with the third power signal end, and the second end of the first pull-down switch element is connected with the pull-up node;

and the control end of the second pull-down switch element is connected with the pull-down node, the first end of the second pull-down switch element is connected with the third power signal end, and the second end of the second pull-down switch element is connected with the signal output end.

In an exemplary embodiment of the present disclosure, all the switching elements are N-type transistors or are P-type transistors.

According to an aspect of the present disclosure, a driving method of a shift register unit is provided for driving the shift register unit; the driving method includes:

transmitting, by the input module, a first power signal to the pull-up node in response to the input signal;

delaying a reset signal through a delay unit in a reset module, and responding to the delayed reset signal through a reset unit in the reset module to transmit a second power supply signal to the pull-up node;

responding to the voltage signal of the pull-up node through an output module to transmit a clock signal to a signal output end;

responding to a voltage signal of the pull-up node through a first pull-down control module to transmit a third power supply signal to the pull-down node;

transmitting, by a second pull-down control module, a fourth power signal to the pull-down node in response to the fourth power signal;

and responding to the voltage signal of the pull-down node through a pull-down module so as to transmit the third power supply signal to the pull-up node and the signal output end respectively.

According to an aspect of the present disclosure, a gate driving circuit is provided, which includes the shift register unit.

According to an aspect of the present disclosure, a display device is provided, which includes the gate driving circuit.

In the shift register unit, the driving method thereof, the gate driving circuit, and the display device according to the exemplary embodiment of the present disclosure, a delay unit is added in the reset module to delay the reset signal, so that the time for transmitting the stop signal to the pull-up node PU and the signal Output terminal Output can be delayed, and thus the voltage of the signal Output terminal Output can be pulled down by the clock signal before the pull-up node PU is reset, and the pull-down node can quickly reach the working voltage while the Output signal is turned off, so that noise reduction can be quickly performed on the signal Output terminal by the pull-down module. Therefore, the problem that the waveform distortion, such as too slow reduction, of the gate driving signal of the shift register unit corresponding to the touch scanning line is caused by the waveform distortion of the pull-up node and the pull-down node can be solved by delaying the reset signal, and the method has no influence on the charging time of the charging capacitors of all the other rows, so that the gate driving signal can be quickly reduced to obtain a stable output waveform.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 schematically shows a circuit configuration diagram of a conventional shift register unit;

FIG. 2 is a schematic diagram showing the waveform changes of pull-up nodes and pull-down nodes in a conventional shift register unit;

FIG. 3 schematically illustrates a distorted waveform of a gate driving signal in a conventional shift register cell;

fig. 4 schematically illustrates a circuit configuration diagram of a shift register unit in an exemplary embodiment of the present disclosure;

fig. 5 schematically illustrates an effect improvement contrast diagram of a gate driving signal in an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates a distribution diagram of shift register cells in a TDDI product in an exemplary embodiment of the disclosure;

fig. 7 schematically illustrates a flow chart of a driving method of a shift register unit in an exemplary embodiment of the present disclosure;

FIG. 8 schematically illustrates a timing diagram of driving signals of a shift register unit in an exemplary embodiment of the present disclosure;

fig. 9 schematically shows a cascade structure of the gate driving circuit in an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The thicknesses and shapes of the layers in the drawings are not to be construed as true scale, but merely as a matter of convenience for illustrating the disclosure. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.

Fig. 1 shows a circuit configuration diagram of a conventional shift register unit 10. Referring to fig. 1, the shift register unit 10 mainly includes: an Input block 101 composed of an Input transistor T1 for charging a pull-up node PU in response to an Input signal Input; an Output module 102 composed of an Output transistor T2 and a charging capacitor C, for outputting the clock signal CLK through a signal Output terminal Output in response to the voltage signal of the pull-up node PU; a Reset block 103 composed of a Reset transistor T3 for outputting a turn-off signal to the pull-up node PU and the signal Output terminal Output in response to a Reset signal Reset; a control module 104 for controlling the voltage of the pull-down node PD according to the pull-up node PU and a power supply voltage VGH; and the pull-down module 105 is configured to perform noise amplification on the pull-up node PU and the signal Output terminal Output in response to the voltage signal of the pull-down node PD.

Based on this, in applications such as 120Hz TDDI (Touch and Display Driver integration) products, Touch signal lines are added to specific rows of the gate driving circuit, which results in that several rows of shift register units need to maintain the current state during the Touch phase until the Touch end can resume normal operation. However, in the meantime, as shown in fig. 2 and fig. 3, since the charge capacitor C in the holding device, such as the shift register unit 10, generates leakage, the pull-up node PU is not opened sufficiently, and thus the waveform of the gate driving signal corresponding to the row clock signal CLK is distorted; meanwhile, the voltage of the pull-down node PD does not rise to the high level VGH yet, that is, the entire shift register unit 10 cannot perform noise release operation, but the Output transistor T2 is turned off, which causes the signal Output terminal Output at this moment to be in a floating state, thereby causing more serious distortion of the waveform of the gate driving signal, such as slow drop.

Specifically, when a touch operation is performed, the shift register unit 10 corresponding to the touch scan line is in a dead state, and at this time, the charging capacitor C generates a leakage current to make the output transistor T2 not be sufficiently turned on, which causes a slow rise of the output signal, resulting in a slow reset of the previous stage shift register unit 10, so that the noise release mechanism of the previous stage shift register unit 10 is delayed and the output signal is delayed and cannot be turned off, and finally, the waveform distortion of the gate driving signal in fig. 3 occurs.

One solution to the above problem may be to directly reduce the duty cycles of all the row clock signals CLK, for example, delay the rising edge time of the clock signal CLK, so as to delay the reset time, and first pull the gate driving signal at the signal Output terminal Output to a low level through the clock signal CLK. However, this reduces the charging time of all the row charging capacitors C, which causes the output transistor T2 to turn on more slowly, which has a negative effect on the turn-on of the gate driving signal.

Based on this, the present exemplary embodiment provides a shift register unit 40 applied to a gate driving circuit of a TDDI product; specifically, the shift register unit 40 can be used as a shift register unit corresponding to a touch scan line in a gate driving circuit of a TDDI product.

As shown in fig. 4, the shift register unit 40 may include:

the Input module 401 is connected to the Input signal terminal, the first power signal terminal, and the pull-up node PU, and configured to respond to the Input signal Input to transmit the first power signal VDD to the pull-up node PU, so as to charge the pull-up node PU;

a Reset module 402 connected to the Reset signal terminal, the second power signal terminal, the third power signal terminal, and the pull-up node PU, where the Reset module 402 may include a Reset unit and a delay unit, where the delay unit may be connected between the Reset signal terminal and the third power signal terminal to delay a Reset signal Reset, and the Reset unit may be configured to respond to the delayed Reset signal Reset to transmit the second power signal VSS to the pull-up node PU, so as to Reset the pull-up node PU, and during a delay period of the Reset signal, the clock signal CLK is at a low level, so that the signal Output terminal Output may be directly Reset;

an Output module 403, connected to the pull-up node PU, the clock signal terminal, and the signal Output terminal Output, for responding to a voltage signal of the pull-up node PU to transmit the clock signal CLK to the signal Output terminal Output, so as to Output to a corresponding gate line as a gate driving signal;

a first pull-down control module 404, connected to the pull-up node PU, the third power signal terminal, and the pull-down node PD, for responding to the voltage signal of the pull-up node PU to transmit the third power signal VGL to the pull-down node PD;

a second pull-down control module 405 connected to the fourth power signal terminal and the pull-down node PD, and configured to respond to the fourth power signal GCH to transmit the fourth power signal GCH to the pull-down node PD;

the pull-down module 406 is connected to the pull-down node PD, the third power signal terminal, the pull-up node PU, and the signal Output terminal Output, and configured to respond to a voltage signal of the pull-down node PD to transmit the third power signal VGL to the pull-up node PU and the signal Output terminal Output, respectively.

In the shift register unit 40 provided in the exemplary embodiment of the present disclosure, a delay unit is added in the Reset module 402 to delay the Reset signal Reset, so that the time for transmitting the off signal to the pull-up node PU and the signal Output terminal Output can be delayed, so that the voltage of the signal Output terminal Output can be pulled down by the clock signal before the pull-up node PU is Reset, and the pull-down node PD can quickly reach the working voltage while the Output signal is turned off, so as to quickly reduce the noise of the signal Output terminal Output by the pull-down module 406. Based on this, fig. 5 is a diagram illustrating the effect of improving the waveform of the gate driving signal obtained by using the shift register unit in the present exemplary embodiment. Therefore, the problem that the waveform distortion of the gate driving signal, for example, the waveform distortion of the gate driving signal is too slow to drop due to the waveform distortion of the pull-up node and the pull-down node of the shift register unit corresponding to the touch scanning line can be solved by delaying the reset signal, and the method has no influence on the charging time of the charging capacitors of all the rest rows, so that the gate driving signal can be rapidly reduced to obtain a stable output waveform.

It is to be emphasized that: the shift register unit 40 provided in the present exemplary embodiment is a shift register unit corresponding to a touch scan line, as shown in fig. 6, there are many common shift register units 60 not corresponding to a touch scan line in the TDDI product, and these common shift register units 60 may be, for example, shift register units excluding delay units.

In this example embodiment, referring to fig. 4, the Input module 401 may include an Input switch element M1, where a control terminal of the Input switch element M1 is connected to the Input signal terminal, a first terminal of the Input switch element is connected to the first power signal terminal, and a second terminal of the Input switch element is connected to the pull-up node PU, and is configured to respond to the Input signal Input to transmit the first power signal VDD to the pull-up node PU, so as to charge the pull-up node PU.

In this example embodiment, as shown with reference to fig. 4, the reset module 402 may include a reset unit and a delay unit; the delay unit may include a delay capacitor C1, and the delay capacitor C1 may be connected between the Reset signal terminal and a low level signal terminal, e.g., a third power signal terminal, for delaying the Reset signal Reset; the Reset unit may include a Reset switch element M2, a control terminal of the Reset switch element M2 is connected to the Reset signal terminal, a first terminal thereof is connected to the second power signal terminal, and a second terminal thereof is connected to the pull-up node PU, for transmitting the second power signal VSS to the pull-up node PU in response to the delayed Reset signal Reset, thereby resetting the pull-up node PU, and the clock signal CLK is at a low level during a delay period of the Reset signal Reset, so that the signal Output terminal Output can be directly Reset.

In the present exemplary embodiment, as shown with reference to fig. 4, the output module 403 may include an output switching element M3 and a charging capacitor C2; the control end of the Output switching element M3 is connected to the pull-up node PU, the first end is connected to the clock signal end, and the second end is connected to the signal Output end Output, and is configured to respond to the voltage signal of the pull-up node PU to transmit the clock signal CLK to the signal Output end Output, so as to Output a gate driving signal to a corresponding gate line; the charging capacitor C2 is disposed between the pull-up node PU and the signal Output terminal Output.

In the present example embodiment, as shown with reference to fig. 4, the first pull-down control module 404 may include a first control switching element M4 and a second control switching element M5; the control end of the first control switch element M4 is connected to the pull-up node PU, the first end is connected to the third power signal end, and the second end is connected to the pull-down control node PD-CN, and is configured to respond to the voltage signal of the pull-up node PU to transmit the third power signal VGL to the pull-down control node PD-CN; the control terminal of the second control switch element M5 is connected to the pull-up node PU, the first terminal thereof is connected to the third power signal terminal, and the second terminal thereof is connected to the pull-down node PD, for responding to the voltage signal of the pull-up node PU to transmit the third power signal VGL to the pull-down node PD.

In the present exemplary embodiment, as shown with reference to fig. 4, the second pull-down control module 405 may include a third control switching element M6 and a fourth control switching element M7; the control terminal and the first terminal of the third control switch element M6 are connected to the fourth power signal terminal, the second terminal is connected to the pull-down control node PD-CN, and the third control switch element M6 is configured to respond to the fourth power signal CGH to transmit the fourth power signal CGH to the pull-down control node PD-CN; the control end of the fourth control switch element is connected with the pull-down control node PD-CN, the first end of the fourth control switch element is connected with the fourth power signal end, and the second end of the fourth control switch element is connected with the pull-down node PD, and the fourth control switch element is used for responding to a voltage signal of the pull-down control node PD-CN to transmit a fourth power signal CGH to the pull-down node PD.

It should be noted that: the first pull-down control module 404 and the second pull-down control module 405 are both used to control the voltage of the pull-down node PD, and in this embodiment, the ratio of the third control switch element M6 to the fourth control switch element M7 is designed to control the voltage of the pull-down node PD when the pull-down node PD is pulled high.

In the present example embodiment, as shown with reference to fig. 4, the pull-down module 406 may include a first pull-down switching element M8 and a second pull-down switching element M9; the control end of the first pull-down switching element M8 is connected to the pull-down node PD, the first end is connected to the third power signal end, and the second end is connected to the pull-up node PU, and is configured to respond to a voltage signal of the pull-down node PD to transmit the third power signal VGL to the pull-up node PU, so as to perform noise cancellation on the pull-up node PU; the control end of the second pull-down switch element M9 is connected to the pull-down node PD, the first end is connected to the third power signal end, and the second end is connected to the signal Output end Output, and is configured to respond to the voltage signal of the pull-down node PD to transmit the third power signal VGL to the signal Output end Output, so as to perform noise cancellation on the signal Output end Output.

In this exemplary embodiment, referring to fig. 4, the shift register unit 40 may further include a total reset switch element M10, where a control terminal of the total reset switch element M10 is connected to the fifth power signal terminal, a first terminal of the total reset switch element is connected to the third power signal terminal, and a second terminal of the total reset switch element is connected to the signal Output terminal Output, and is configured to raise the fifth power signal GCL to high after the one-frame image is scanned line by line, so as to perform total reset on the signal Output terminal Output of each shift register unit (including the shift register unit 40 and the normal shift register unit 60 corresponding to the touch signal line).

Based on the shift register unit 40, all the switching elements may employ P-type transistors or N-type transistors. The embodiment of the invention adopts uniform transistor types, which is helpful to simplify the process and reduce the manufacturing cost.

The present exemplary embodiment also provides a driving method of a shift register unit, which is used for driving the shift register unit. As shown in fig. 7, the driving method includes:

s1, responding to the Input signal Input through the Input module 401 to transmit the first power signal VDD to the pull-up node PU;

s2, delaying the Reset signal Reset through the delay unit in the Reset module 402, and responding to the delayed Reset signal Reset through the Reset unit in the Reset module 402 to transmit the second power signal VSS to the pull-up node PU;

s3, responding to the voltage signal of the pull-up node PU through the Output module 403 to transmit the clock signal CLK to the signal Output terminal Output;

s4, transmitting the third power signal VGL to the pull-down node PD through the first pull-down control module 404 in response to the voltage signal of the pull-up node PU;

s5, responding to the fourth power signal CGH through the second pull-down control module 405 to transmit the fourth power signal CGH to the pull-down node PD;

s6, the pull-down module 406 responds to the voltage signal of the pull-down node PD to transmit the third power signal VGL to the pull-up node PU and the signal Output terminal Output, respectively.

In the driving method of the shift register unit 40 provided in the exemplary embodiment of the present disclosure, the Reset signal Reset is delayed by the delay unit in the Reset module 402, so that the time for transmitting the stop signal to the pull-up node PU and the signal Output terminal Output can be delayed, and thus the pull-down node PD can quickly reach the working voltage while the Output signal is turned off, so as to quickly reduce the noise of the signal Output terminal Output by the pull-down module 406. Based on this, fig. 5 is a diagram illustrating the effect of improving the waveform of the gate driving signal obtained by using the shift register unit in the present exemplary embodiment. Therefore, the problem that the grid driving signal is too slow to fall due to waveform distortion of the pull-up node and the pull-down node of the shift register unit corresponding to the touch scanning line can be solved by delaying the reset signal, and the charging time of the charging capacitors of all the other lines is not influenced by the method, so that the grid driving signal can be quickly reduced to obtain a stable output waveform.

The operation of the shift register unit 40 will be described in detail with reference to the signal timing diagram shown in fig. 8, taking an example in which all the switching elements are N-type transistors.

At the first t1 stage, the Input signal Input is at a high level, the first power signal VDD is at a high level, the clock signal CLK is at a low level, the Input switch element M1 is turned on, the first power signal VDD is transmitted to the pull-up node PU and charges the charging capacitor C2, the first control switch element M4 and the second control switch element M5 are turned on under the action of the pull-up node PU, so that the pull-down node PD is at a low level at this moment, and the first pull-down switch element M8 and the second pull-down switch element M9 are turned off.

At the second t2 stage, the Input signal Input is at a low level, the clock signal CLK is at a high level, the Input switch element M1 is turned off, the Output switch element M3 is turned on under the action of the pull-up node PU, and the action of the pull-up node PU is further increased due to the bootstrap effect of the capacitor, so that the Output switch element M3 is fully turned on, and the clock signal CLK is transmitted to the signal Output terminal Output to Output the gate driving signal. At this time, the first control switch element M4 and the second control switch element M5 are still in the on state, and thus the first pull-down switch element M8 and the second pull-down switch element M9 are still in the off state, so that the stability of signal output can be ensured.

At the third stage t3, the Output signal G (n +1), i.e., the Reset signal Reset, at the next stage is at a high level, and the Reset signal Reset charges the delay capacitor C1 before the Reset switch element M2 is fully turned on due to the existence of the delay capacitor C1, and the Reset switch element M2 is fully turned on after the delay capacitor C1 is fully charged, so as to transmit a turn-off signal to the pull-up node PU and the signal Output terminal Output through the second power signal VSS, thereby discharging the pull-up node PU and the signal Output terminal Output.

At the fourth t4 stage, the fourth power signal GCH is at a high level, and since the pull-up node PU and the signal Output terminal Output have been discharged at the previous stage, the first control switch element M4 and the second control switch element M5 are turned off, and therefore the pull-down node PD is not discharged any more; at this time, under the action of the fourth power signal CGH, the third control switch element M6 and the fourth control switch element M7 are turned on to pull up the potential of the pull-down node PD, and then the first pull-down switch element M8 and the second pull-down switch element M9 are turned on to realize noise amplification on the pull-up node PU and the signal Output terminal Output, so that the coupling noise generated by the clock signal CLK is eliminated, thereby realizing low voltage Output and ensuring the stability of signal Output.

Based on the above process, in the exemplary embodiment, the Reset signal Reset is delayed by the delay capacitor C1, so as to improve the problem that the gate driving signal drops too slowly due to the waveform distortion of the pull-up node PU and the pull-down node PD in the scan line corresponding to the fixed touch signal line, and the charging time of the charging capacitors C2 in all other rows is not affected, so that the problem that the gate driving signal is turned off slowly can be improved.

It should be noted that: the specific details of the driving method of the shift register unit have been described in detail in the structure of the corresponding shift register unit, and are not described herein again.

The present exemplary embodiment also provides a gate driving circuit, as shown in fig. 9, including a plurality of cascaded shift register units 40 as described above.

The Input signal Input of each stage of the shift register unit 40 is the output signal of the previous stage of the shift register unit 40, and the Reset signal Reset of each stage of the shift register unit 40 is the output signal of the next stage of the shift register unit 40.

In this exemplary embodiment, the Gate driving circuit may be disposed in the display panel in a COF (Chip on Film) or COG (Chip on Glass) packaging manner, or may be integrated in the display panel in a GOA (Gate on array) circuit manner. The gate driving circuit formed by the GOA technology can reduce processes to improve productivity and reduce cost.

The gate driving circuit integrates a display driving function and a touch driving function, so that noise can be effectively reduced, and the display quality of the touch display device can be improved.

The display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register cell, comprising:

2. The shift register unit according to claim 1, wherein the reset unit includes a reset switch element, a control terminal of the reset switch element is connected to the reset signal terminal, a first terminal of the reset switch element is connected to the second power signal terminal, and a second terminal of the reset switch element is connected to the pull-up node;

3. The shift register unit according to claim 1, wherein the input module comprises an input switch element, a control terminal of the input switch element is connected to the input signal terminal, a first terminal of the input switch element is connected to the first power signal terminal, and a second terminal of the input switch element is connected to the pull-up node.

4. The shift register cell of claim 1, wherein the output module comprises an output switching element and a charging capacitor;

5. The shift register unit according to claim 1, wherein the first pull-down control module includes a first control switching element and a second control switching element;

6. The shift register cell of claim 5, wherein the second pull-down control module comprises a third control switching element and a fourth control switching element;

and the control end of the fourth control switch element is connected with the pull-down control node, the first end of the fourth control switch element is connected with the fourth power signal end, and the second end of the fourth control switch element is connected with the pull-down node.

7. The shift register cell of claim 1, wherein the pull-down module comprises a first pull-down switching element and a second pull-down switching element;

8. The shift register cell according to any one of claims 1 to 7, wherein all the switching elements are N-type transistors or P-type transistors.

9. A method of driving a shift register cell, for driving a shift register cell according to any one of claims 1 to 8; characterized in that the driving method comprises:

10. A gate drive circuit comprising a shift register cell according to any one of claims 1 to 8.

11. A display device comprising the gate driver circuit according to claim 10.