CN107909960B - Shift register unit, shift register circuit and display panel - Google Patents
Shift register unit, shift register circuit and display panel Download PDFInfo
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- CN107909960B CN107909960B CN201810003043.3A CN201810003043A CN107909960B CN 107909960 B CN107909960 B CN 107909960B CN 201810003043 A CN201810003043 A CN 201810003043A CN 107909960 B CN107909960 B CN 107909960B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The disclosure relates to a shift register unit, a shift register circuit and a display panel thereof, and relates to the technical field of display. The shift register unit includes: the input module comprises more than two switching elements and is used for transmitting a first power supply signal to a pull-up node under the control of an input signal; the output module is used for transmitting a clock signal to a signal output end under the control of the voltage signal of the pull-up node; the pull-down module is used for transmitting a second power supply signal to the pull-up node and the signal output end under the control of a voltage signal of a pull-down node; and the storage capacitor is connected between the pull-up node and the signal output end. The display device and the display method can avoid poor display caused by output waveform distortion.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, and a display panel thereof.
Background
With the development of optical technology and semiconductor technology, flat panel displays represented by Liquid Crystal Displays (LCDs) and Organic Light Emitting Diode (OLED) displays have the characteristics of lightness, thinness, low energy consumption, fast response speed, good color purity, high contrast ratio and the like, and have a leading position in the Display field.
Display devices have been developed to have high integration and low cost in recent years. Taking a Gate Driver on Array (GOA) technology as a representative example, the Gate driving circuit is integrated in a peripheral region of the Array substrate by using the GOA technology, so that the integration of the display device is effectively improved and the manufacturing cost thereof is reduced while the narrow frame design is realized.
The output end of each stage of shift register unit in the GOA circuit is connected with a corresponding grid line and used for outputting a grid scanning signal to the grid line so as to realize the function of scanning line by line. The gate number of the GOA is increasing due to the higher resolution, so the requirement for charging the storage capacitor is more and more demanding.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a shift register unit, a shift register circuit and a display panel thereof, which overcome the problem of distortion of a circuit output waveform due to the limitations and disadvantages of the related art, at least to a certain extent.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to an aspect of the present disclosure, there is provided a shift register unit including:
the input module comprises more than two switching elements and is used for transmitting a first power supply signal to a pull-up node under the control of an input signal;
the output module is used for transmitting a clock signal to a signal output end under the control of the voltage signal of the pull-up node;
the pull-down module is used for transmitting a second power supply signal to the pull-up node and the signal output end under the control of a voltage signal of a pull-down node;
and the storage capacitor is connected between the pull-up node and the signal output end.
In an exemplary embodiment of the present disclosure, the input module includes:
a first switch element, a control terminal of which receives the input signal, a first terminal of which receives the first power signal, and a second terminal of which is connected to the pull-up node;
and the control end of the second switch element receives the input signal, the first end of the second switch element receives the first power supply signal, and the second end of the second switch element is connected with the pull-up node.
In an exemplary embodiment of the present disclosure, the input module includes:
a first switch element, a control terminal of which receives the input signal, a first terminal of which receives the first power signal, and a second terminal of which is connected to the pull-up node;
a second switch element, a control end of which receives the input signal, a first end of which receives the first power supply signal, and a second end of which is connected with a first end of a third switch element;
and a first end of the third switching element is connected with a second end of the second switching element, and a second end of the third switching element is connected with the pull-up node.
In an exemplary embodiment of the present disclosure, the first switching element is connected in parallel with the second switching element.
In an exemplary embodiment of the present disclosure, the output module includes:
and the control end of the fourth switching element is connected with the pull-up node, the first end of the fourth switching element receives the clock signal, and the second end of the fourth switching element is connected with the signal output end.
In an exemplary embodiment of the present disclosure, the pull-down module includes:
a fifth switching element having a control terminal connected to the pull-down node, a first terminal receiving the second power signal, and a second terminal connected to the signal output terminal;
and the control end of the sixth switching element is connected with the pull-down node, the first end of the sixth switching element receives the second power supply signal, and the second end of the sixth switching element is connected with the pull-up node.
In an exemplary embodiment of the present disclosure, further comprising:
the reset module is used for transmitting the second power supply signal to the pull-up node under the control of a reset signal;
the reset module includes:
and the control end of the seventh switching element is connected with the reset signal, the first end of the seventh switching element receives the second power supply signal, and the second end of the seventh switching element is connected with the pull-up node.
In an exemplary embodiment of the present disclosure, further comprising:
a pull-up module for transmitting the second power signal to the pull-down node under control of a voltage signal of the pull-up node;
the pull-down control module is used for transmitting a first voltage signal to the pull-down node under the control of the first voltage signal;
and the output control module is used for transmitting the second power supply signal to the signal output end under the control of a second voltage signal.
According to an aspect of the present disclosure, there is provided a shift register circuit comprising a plurality of cascaded shift register cells as described in any one of the above;
the output signal of the signal output end of the M-th stage shift register unit is the input signal of the M + 1-th stage shift register unit.
According to an aspect of the present disclosure, there is provided a display panel including a display area and a peripheral area; wherein the peripheral region is provided with any one of the shift register circuits described above.
According to the shift register unit, the shift register circuit and the display panel thereof provided by the exemplary embodiment of the disclosure, on the basis of an input module of a traditional shift register unit structure, the number of switch elements in the input module is increased, it can be ensured that when an input signal is at a high level, the charging speed of a storage capacitor can be increased through the input module, the magnitude of leakage current flowing through a first switch element cannot be increased, the output distortion condition of a GOA circuit is improved, the stability of the GOA circuit is improved, and poor display caused by the leakage current is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic diagram of a prior art shift register unit;
FIG. 2 is a schematic diagram showing a timing diagram of the operation of a shift register unit in the prior art;
FIG. 3 schematically illustrates a structural schematic diagram of a shift register cell in an exemplary embodiment of the present disclosure;
FIG. 4 schematically illustrates a waveform comparison diagram of a shift register cell in an exemplary embodiment of the present disclosure;
fig. 5 schematically shows a cascade structure of the shift register circuit in the exemplary embodiment of the present disclosure.
Reference numerals:
M1-M12 first to twelfth transistors
C1 storage capacitor
Input first Input signal
Output signal Output terminal
PU pull-up node
PD pull-down node
CLK clock signal
RST reset signal
VDD first power supply signal
VSS/VGL second power supply signal
GCH first voltage signal
GCL second voltage signal
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
For example, referring to the shift register unit shown in fig. 1, if the size of the first switch element M1 is increased, although the speed of charging the capacitor can be increased, the leakage current flowing through the first switch element M1 is increased at the same time, which may cause the GOA circuit to output incorrectly or distort the output, so that various defects may occur in the shift register circuit, which may cause abnormal display.
In conjunction with the shift register unit of the related art shown in fig. 1 and the timing diagram shown in fig. 2, the operation of the shift register unit is as follows:
in the first stage t1, when the Input signal Input is a high-level signal, the Input signal Input is a voltage signal of the signal Output terminal Output of the previous stage, and the first switching element M1 is turned on under the action of the high level of the Input signal; when the clock signal CLK is a low-level signal, the level of the pull-up node PU is pulled up by a high-level signal of the signal input terminal, and then the storage capacitor C1 is charged, meanwhile, M8 and M6 are turned on under the action of the high level of the pull-up node PU, and the pull-down node PD is made to be a low level by designing the ratio of M5 to M9, so that M10 and M4 are turned off, and stable output of signals is ensured.
In the second phase t2, when the Input signal Input is at a low level, the first switching element M1 is turned off, the pull-up node PU continues to be kept at a high level by the storage capacitor C1, and the third switching element M3 is kept in a turned-on state. The clock signal CLK is a high-level signal, the voltage of the pull-up node PU is amplified by the pull-up node PU due to the bootstrap effect, and finally a driving signal is transmitted to the output end; at this time, the pull-up node PU is a high level signal, and M6 is turned on, so that M10 and M4 are continuously turned off, and stable output of the signal is ensured.
In the third stage t3, the voltage signal of the Output of the next stage signal Output terminal, i.e. the reset signal, so that the reset signal RST is at a high level, M2 is turned on under the control of the high level of the reset signal, and transmits a low level signal to the pull-up node PU and the signal Output terminal Output through the reset signal, M3 is turned off, and the Output signal is pulled to the VGL potential, so as to ensure the stable Output of the signal.
In the fourth period t4, the GCH is always high. At this time, in the third stage, the pull-up node PU and the signal Output terminal Output are already discharged through M2, and at this time, M6 is in an off state, so that the pull-down node PD is not discharged; since GCH is high potential, M9 and M5 are turned on, and the potential of the pull-down node PD is pulled high at this time, so as to open the discharge tubes M10 and M4, and to perform noise amplification on the pull-up node PU and the signal Output terminal Output, so that the Coupling noise voltage generated by CLK is eliminated, thereby ensuring low voltage Output and the stability of signal Output.
At the next time, GCH is high all the time, and the Coupling noise generated by CLK is in the noise-released state all the time until the row is turned on for the next frame.
Therefore, the shift register unit can only ensure the output of a general Gate waveform, but has no function of improving the distortion of the Gate waveform.
In order to avoid the above-described problems, the present exemplary embodiment proposes a shift register unit for supplying a gate scan signal; as shown in fig. 3, the shift register unit may specifically include:
an Input module 10, including two or more switching elements, for transmitting a first power signal VDD to a pull-up node PU under the control of an Input signal Input;
an Output module 20, configured to transmit a clock signal CLK to a signal Output terminal Output under the control of the voltage signal of the pull-up node PU;
the pull-down module 30 is configured to transmit a second power signal VGL to the pull-up node PU and the signal Output terminal Output under the control of a voltage signal of the pull-down node PD;
and the storage capacitor C1 is connected between the pull-up node PU and the signal Output end Output.
In addition, the shift register unit may further include:
a reset module 40, configured to transmit the second power signal VSS to the pull-up node PU under the control of a reset signal RST.
According to the shift register unit provided by the exemplary embodiment of the disclosure, on the basis of an input module of a traditional shift register unit structure, the number of the switch elements in the input module is increased, so that when an input signal is at a high level, the charging speed of the storage capacitor can be increased through the input module, the magnitude of leakage current flowing through the first switch element cannot be increased, the output distortion of a GOA circuit is improved, and poor display caused by the output distortion is avoided.
In this exemplary embodiment, the Input module 10 may specifically include more than two switching elements, and all the switching elements are used for transmitting the first power signal VDD to the pull-up node PU under the control of the Input signal Input.
It should be noted that: the purpose of adjusting the input module 10 in this exemplary embodiment is to increase the charging speed of the storage capacitor C1, avoid increasing the leakage current flowing through the switching element M1, and avoid the circuit output distortion caused by the large leakage current, so as long as the above effects can be achieved, the input module 10 may be provided with two switching elements or a plurality of switching elements, which is not specifically limited herein.
The shift register unit in the present exemplary embodiment is described in detail below with reference to fig. 3. As shown in fig. 4, taking the first to twelfth switching elements as an example of an N-type transistor, the control terminal may be a gate of the transistor, the first terminal may be a source of the transistor, and the second terminal may be a drain of the transistor; however, since the source and the drain of the transistor are not strictly distinguished, the first terminal may be the drain of the transistor and the second terminal may be the source of the transistor. Wherein:
in the present exemplary embodiment, all the switching elements may employ MOS transistors (Metal oxide semiconductor field effect transistors) or transistors, and specifically, each of the first to twelfth switching elements may employ an N-type MOS transistor. In addition, the first to twelfth switching elements may be P-type MOS transistors. It should be noted that: the level signals of the respective signal terminals require a corresponding adjustment change for different transistor types.
Specifically, the input module 10 may include: a first switch element M1, having a control terminal receiving the Input signal Input, a first terminal receiving the first power signal VDD, and a second terminal connected to the pull-up node PU; the second switch element M2 has a control terminal receiving the Input signal Input, a first terminal receiving the first power signal VDD, and a second terminal connected to the pull-up node PU. It is noted that the first switching element may be connected in parallel with the second switching element to reduce the resistance in the input module 10 and increase the total current flowing through the input module 10, thereby increasing the charging speed of the storage capacitor C1.
Further, the input module 10 may also have another structure, which specifically includes: a first switch element M1, having a control terminal receiving the Input signal Input, a first terminal receiving the first power signal VDD, and a second terminal connected to the pull-up node PU; a second switch element M2, having a control terminal receiving the Input signal Input, a first terminal receiving the first power signal VDD, and a second terminal connected to the first terminal of the third switch element M3; a third switching element M3 has a first terminal connected to the second terminal of the second switching element M2, and a second terminal connected to the pull-up node PU.
It should be noted that the second switch element may be connected in series with the third switch element, for example, the drain of the second switch element is connected to the drain of the third switch element, the source of the second switch element receives the first power signal VDD, the source of the third switch element is connected to the pull-up node PU, and the first switch element M1 may be connected in parallel with the second switch element and the third switch element after being connected in series, so as to reduce the resistance in the input module 10, increase the total current flowing through the input module 10, and improve the charging speed of the storage capacitor C1; in addition, the second switching element and the third switching element are connected in series to reduce the leakage current flowing through the first switching element M1, thereby avoiding abnormal output of the GOA circuit. The number of the series switching elements is not limited to two, and can be specifically set according to actual requirements.
The output module 20 may include: a control terminal of the fourth switching element M4 is connected to the pull-up node PU, a first terminal receives the clock signal CLK, and a second terminal is connected to the signal Output terminal Output.
The pull-down module 30 may include: a control end of the fifth switching element M5 is connected to the pull-down node PD, a first end of the fifth switching element M5 receives the second power signal VGL, and a second end of the fifth switching element M5 is connected to the signal Output end Output; the pull-down module 30 may further include: a control terminal of the sixth switching element M6 is connected to the pull-down node PD, a first terminal receives the second power signal VGL, and a second terminal is connected to the pull-up node PU.
The reset module 40 may include: the seventh switching element M7 has a control terminal connected to the reset signal RST, a first terminal receiving the first power signal VSS, and a second terminal connected to the pull-up node PU.
The shift register provided in this example may further include: a pull-up module 50, configured to transmit a second power signal VGL to the pull-down node PD under the control of the voltage signal of the pull-up node PU; a pull-down control module 60, configured to transmit the first voltage signal GCH to the pull-down node PD under the control of the first voltage signal GCH; the Output control module 70 is configured to transmit the second power signal VGL to the signal Output terminal Output under the control of the second voltage signal GCL. M12
The pull-up module 50 may specifically include: an eighth switching element M8 having a control terminal connected to the pull-up node PU, a first terminal receiving the second power signal VGL, and a second terminal connected to the second terminal of the tenth switching element M10 to be connected to the pull-down node PD through the tenth switching element and the eleventh switching element; a control terminal of the ninth switching element M9 is connected to the pull-down node PU, a first terminal thereof receives the second power signal VGL, and a second terminal thereof is connected to the pull-down node PD.
The pull-down control module 60 may specifically include: a tenth switching element M10 having a control terminal and a first terminal both receiving the first voltage signal GCH, a second terminal connected to the pull-down node PD and to the second terminal of the eighth switching element, and also connected to the control terminal of the eleventh switching element M11 to connect to the pull-down node PD through the eleventh switching element; and an eleventh switching element M11 having a control terminal connected to the second terminal of the tenth switching element, a first terminal receiving the first voltage signal GCH, and a second terminal connected to the pull-down node PD.
The output control module 70 may specifically include: a control terminal of the twelfth switching element M12 receives the second voltage signal GCL, a first terminal thereof receives the second power signal VGL, and a second terminal thereof is connected to the signal Output terminal Output.
The operation principle of the shift register unit in which the control timing is executed to each stage will be described in detail with reference to the operation timing chart shown in fig. 2. The first power signal VDD is a high level signal, the second power signal VGL/VSS is a low level signal, the first voltage signal GCH is a high level signal, and the second voltage signal GCL is a low level signal.
The working process of the shift register circuit specifically comprises the following stages:
first, it should be noted that the first voltage signal GCH is always a high level signal, so that the tenth switching element and the eleventh switching element are kept in a conductive state, and the pull-down node PD is kept at a high level, so that the fifth switching element and the sixth switching element are kept in a conductive state.
First stage t 1: when the Input signal Input is a high-level signal, the Input signal Input is a voltage signal of the signal Output terminal Output of the previous stage, and the first switching element M1 is turned on under the action of the high level of the Input signal; when the clock signal CLK is a low level signal, the level of the pull-up node PU is pulled up by a high level signal at the signal Input terminal, and the storage capacitor C1 is charged, and meanwhile, the second switching element M2 and the third switching element M3 are also turned on under the action of the high level of the Input signal Input, and the charging current is 2 times that in the conventional shift register unit, so that the storage capacitor C1 can be rapidly charged to the high level.
In the second phase t2, when the Input signal Input is at a low level, the switching elements M1, M2, and M3 are all turned off, the pull-up node PU continues to maintain at a high level under the action of the storage capacitor C1, and the fourth switching element M4 maintains a conducting state. The clock signal CLK is a high-level signal, the voltage of the pull-up node PU is amplified by the pull-up node PU due to the bootstrap effect, and finally a driving signal is transmitted to the output end; the storage capacitor C1 after being filled has better bootstrap effect than the storage capacitor in the conventional shift register unit shown in fig. 1, and the voltage after bootstrap is close to 2 times the VGH voltage, so that the stable output of the signal can be ensured.
In the third stage t3, the voltage signal at the Output terminal Output of the next stage is the reset signal, so the reset signal RST is at a high level, M7 is turned on under the control of the high level of the reset signal, the second power signal VSS is transmitted to the pull-up node PU through the reset signal, M4 is turned off, and since the first voltage signal GCH is always at a high level, the first voltage signal GCH is transmitted to the pull-down node PD through the tenth switching element M10 and the eleventh switching element M11, so that the fifth switching element M5 and the sixth switching element M6 are turned on to transmit the second power signal VGL to the Output terminal Output, thereby ensuring stable Output of the signal.
In the fourth stage t4, since the GCH is always high and the pull-up node PU and the signal Output terminal Output have been discharged through M7 in the second stage, at this time, M9 is in the off state, the pull-down node PD is not discharged; since GCH is high potential, M10 and M11 are turned on, and the potential of the pull-down node PD is pulled high at this time, so as to open the discharge tubes M5 and M6, and to perform noise amplification on the pull-up node PU and the signal Output terminal Output, so that the Coupling noise voltage generated by CLK is eliminated, thereby ensuring low voltage Output and the stability of signal Output. At this time, both M1 and M2 are turned off, and there is no potential difference between both ends of M3, so the leakage current passing through M2 is very small and can be ignored.
The work flow of the next moment is the same as that of the conventional shift register unit, and is not described herein again.
It should be noted that: after the fourth stage t4, the shift register units of each stage may repeat the first stage t1 and the fourth stage t4 according to actual conditions.
In order to verify the distortion of the output signal of the shift register unit, the description will be made with reference to the output waveform diagram shown in fig. 4. As can be seen from diagram a in fig. 4: output waveforms of the pull-up node PU and the pull-down node PD have certain rising edges or falling edges, and output waveforms of output signals G (n) and G (n + 1) have certain rising edges, so that the output waveform is distorted; compared with the graph a, in the output waveform in the graph B in fig. 4, the amplitude of the rising edge or the falling edge in the output waveforms of the pull-up node PU and the pull-down node PD is reduced, and the rising edges existing in the output waveforms of the output signals G (n) and G (n + 1) disappear, so that it can be illustrated that the shift register unit provided in this example can improve the distortion of the output signals and improve the stability of the output signals.
Based on the above process, in the exemplary embodiment, by adding the second switching element and the third switching element to the input module 10, not only the charging speed of the storage capacitor C1 is increased, but also the leakage current flowing through the first switching element M1 is prevented from increasing, the output distortion of the circuit due to the large leakage current is prevented, the stability of the GOA circuit is improved, and the display failure caused by the output distortion is prevented.
The present exemplary embodiment also provides a shift register circuit, which can be applied to a GOA circuit including one or more clock signals CLK as a gate driving circuit; as shown in fig. 5, the shift register circuit may include a plurality of cascaded shift register units; the Output signal of the signal Output end Output of the M-th stage shift register unit is the Input signal Input of the M + 1-th stage shift register unit. For example, the reset signal in the first shift register unit SR1 may be the output signal of the second shift register unit SR2, and the input signal in the first shift register unit SR1 may be a start signal STV.
On the basis, the scanning mode of the shift register circuit can comprise forward scanning or reverse scanning. When the forward direction scanning is adopted, the Input signal Input of the first stage shift register unit is a starting signal. When the reverse scanning is adopted, the Input signal Input of the last stage of shift register unit is the initial signal.
It should be noted that: the specific details of each module unit in the shift register circuit have been described in detail in the corresponding shift register unit, and are not described herein again.
The present exemplary embodiment also provides a display panel including a display region and a peripheral region, and the shift register circuit described above is provided in the peripheral region.
Therefore, in the present embodiment, the shift register circuit is integrated on the periphery of the display panel by using the GOA technology, so as to implement the design of the narrow-bezel panel and reduce the manufacturing cost of the display panel.
The Display Panel may be specifically an LCD Display Panel, an OLED Display Panel, a PLED (polymer light-Emitting Diode) Display Panel, a PDP (Plasma Display Panel), and the like, and the application of the Display Panel is not particularly limited herein.
The present exemplary embodiment also provides a display device including the display panel described above. The display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (8)
1. A shift register cell, comprising:
an input module including two or more switching elements for transmitting a first power signal to a pull-up node under control of an input signal by increasing the number of the switching elements included in the input module;
the output module is used for transmitting a clock signal to a signal output end under the control of the voltage signal of the pull-up node;
the pull-down module is used for transmitting a second power supply signal to the pull-up node and the signal output end under the control of a voltage signal of a pull-down node;
a storage capacitor connected between the pull-up node and the signal output terminal;
wherein the input module comprises:
a first switch element, a control terminal of which receives the input signal, a first terminal of which receives the first power signal, and a second terminal of which is connected to the pull-up node;
a second switch element, a control end of which receives the input signal, a first end of which receives the first power supply signal, and a second end of which is connected with a first end of a third switch element;
and the control end of the third switching element receives the input signal, the first end of the third switching element is connected with the second end of the second switching element, and the second end of the third switching element is connected with the pull-up node.
2. The shift register cell of claim 1, wherein the first switching element is connected in parallel with the second switching element.
3. The shift register cell of claim 1, wherein the output module comprises:
and the control end of the fourth switching element is connected with the pull-up node, the first end of the fourth switching element receives the clock signal, and the second end of the fourth switching element is connected with the signal output end.
4. The shift register cell of claim 1, wherein the pull-down module comprises:
a fifth switching element having a control terminal connected to the pull-down node, a first terminal receiving the second power signal, and a second terminal connected to the signal output terminal;
and the control end of the sixth switching element is connected with the pull-down node, the first end of the sixth switching element receives the second power supply signal, and the second end of the sixth switching element is connected with the pull-up node.
5. The shift register cell of claim 1, further comprising:
the reset module is used for transmitting the second power supply signal to the pull-up node under the control of a reset signal;
the reset module includes:
and the control end of the seventh switching element is connected with the reset signal, the first end of the seventh switching element receives the second power supply signal, and the second end of the seventh switching element is connected with the pull-up node.
6. The shift register cell of claim 1, further comprising:
a pull-up module for transmitting the second power signal to the pull-down node under control of a voltage signal of the pull-up node;
the pull-down control module is used for transmitting a first voltage signal to the pull-down node under the control of the first voltage signal;
and the output control module is used for transmitting the second power supply signal to the signal output end under the control of a second voltage signal.
7. A shift register circuit comprising a plurality of cascaded shift register cells of any of claims 1-6;
the output signal of the signal output end of the M-th stage shift register unit is the input signal of the M + 1-th stage shift register unit.
8. A display panel includes a display region and a peripheral region; wherein the peripheral region is provided with the shift register circuit according to claim 7.
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| CN108766383B (en) | 2018-06-12 | 2020-12-11 | 京东方科技集团股份有限公司 | Shift register unit, shift register circuit and display device |
| CN108877716B (en) * | 2018-07-20 | 2021-01-26 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN111210786B (en) * | 2020-01-22 | 2021-12-24 | 合肥鑫晟光电科技有限公司 | Shifting register unit, grid driving circuit, display substrate and display device |
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| JP2006344306A (en) * | 2005-06-09 | 2006-12-21 | Mitsubishi Electric Corp | Shift register |
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| CN106910470A (en) * | 2017-04-19 | 2017-06-30 | 京东方科技集团股份有限公司 | Shift register cell, shift-register circuit, display panel |
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| TWI400686B (en) * | 2009-04-08 | 2013-07-01 | Au Optronics Corp | Shift register of lcd devices |
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| CN102254503A (en) * | 2010-05-19 | 2011-11-23 | 北京京东方光电科技有限公司 | Shift register unit, grid driving device used for display and liquid crystal display |
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