CN106910451B - Gate drive circuit and drive method of gate drive circuit - Google Patents
Gate drive circuit and drive method of gate drive circuit Download PDFInfo
- Publication number
- CN106910451B CN106910451B CN201710295905.XA CN201710295905A CN106910451B CN 106910451 B CN106910451 B CN 106910451B CN 201710295905 A CN201710295905 A CN 201710295905A CN 106910451 B CN106910451 B CN 106910451B
- Authority
- CN
- China
- Prior art keywords
- pull
- module
- electrically connected
- transistor
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 8
- 201000005569 Gout Diseases 0.000 description 35
- 238000010586 diagram Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 4
- 230000002035 prolonged effect Effects 0.000 description 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
The embodiment of the invention discloses a gate drive circuit and a driving method of the gate drive circuit, wherein the gate drive circuit comprises: each stage of driving unit comprises a pre-charging module, a pull-up module, a reset module, a pull-down control module and a pull-down module; the pull-up module is used for outputting a scanning signal at a first output end of the driving unit; the reset module is used for pulling down the potential of the control node; the first control signal input ends of two adjacent stages of driving units input opposite signals; the pull-down module is used for pulling down the control node of the current-stage driving unit and the potential of the first output end; the third output end of the pull-down module is electrically connected with the control node of the previous-stage driving unit, the fourth output end of the pull-down module is electrically connected with the first output end of the previous-stage driving unit, and the pull-down module is also used for pulling down the control node of the previous-stage driving unit and the potential of the first output end. The technical scheme provided by the embodiment of the invention can save circuit elements and reduce power consumption.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a driving method of the gate driving circuit.
Background
The display panel needs to provide a scanning signal to perform scanning display line by line in the display process, and the scanning signal is generally provided by a gate driving circuit.
The gate driving circuit generally includes a multi-stage driving unit, for example, a shift register including a cascade of a plurality of stages. The output end of each driving unit corresponds to one gate line, and the driving units provide scanning signals to the corresponding gate lines step by step. Two pull-down systems are designed in the existing driving unit, namely a first pull-down system and a second pull-down system, circuit elements of the first pull-down system and the second pull-down system are the same, and the two pull-down systems work alternately. For example, in a first frame, the first pull-down system of the driving unit is operated, and the second pull-down system is not operated; in a second frame, a second pull-down system of the driving unit works, and a first pull-down system does not work; and in a third frame, the first pull-down system of the driving unit works, the second pull-down system does not work, and the operation is cyclically alternated. The first pull-down system and the second pull-down system of the driving unit work alternately, so that the service life of the pull-down system is prolonged, and the service life of the whole circuit is prolonged. However, this results in the use of more circuit elements and the power consumption of the circuit is also greater.
Disclosure of Invention
The invention provides a gate driving circuit and a driving method of the gate driving circuit, which are used for simplifying the structure of the gate driving circuit, saving the circuit area and reducing the power consumption.
In a first aspect, an embodiment of the present invention provides a gate driving circuit, where the gate driving circuit includes: the driving units at each stage comprise a pre-charging module, a pull-up module, a reset module, a pull-down control module and a pull-down module;
the output end of the pre-charging module is electrically connected with the control node and is used for pre-charging the control node;
the control end of the pull-up module is electrically connected with the control node, the input end of the pull-up module is electrically connected with the first clock signal input end of the driving unit, and the first output end of the pull-up module is electrically connected with the first output end of the driving unit and is used for outputting a scanning signal at the first output end of the driving unit;
the output end of the reset module is electrically connected with the control node and used for pulling down the potential of the control node;
a first control end of the pull-down control module is electrically connected with the control node, a second control end of the pull-down control module is electrically connected with a first control signal input end of the driving unit, and an input end of the pull-down control module is electrically connected with a first level signal input end of the driving unit; the first control signal input ends of two adjacent stages of driving units input opposite signals;
the control end of the pull-down module is electrically connected with the output end of the pull-down control module, the input end of the pull-down module is electrically connected with the second level signal input end of the driving unit, the first output end of the pull-down module is electrically connected with the control node, the second output end of the pull-down module is electrically connected with the first output end of the driving unit, and the pull-down module is used for pulling down the control node and the potential of the first output end of the driving unit;
the third output end of the pull-down module is electrically connected with the control node of the previous-stage driving unit, the fourth output end of the pull-down module is electrically connected with the first output end of the previous-stage driving unit, and the pull-down module is also used for pulling down the control node of the previous-stage driving unit and the potential of the first output end.
In a second aspect, an embodiment of the present invention further provides a driving method of a gate driving circuit, where the gate driving circuit includes: the driving units at each stage comprise a pre-charging module, a pull-up module, a reset module, a pull-down control module and a pull-down module;
the output end of the pre-charging module is electrically connected with the control node;
the control end of the pull-up module is electrically connected with the control node, the input end of the pull-up module is electrically connected with the first clock signal input end of the driving unit, and the first output end of the pull-up module is electrically connected with the first output end of the driving unit;
the output end of the reset module is electrically connected with the control node;
a first control end of the pull-down control module is electrically connected with the control node, a second control end of the pull-down control module is electrically connected with a first control signal input end of the driving unit, and an input end of the pull-down control module is electrically connected with a first level signal input end of the driving unit; the first control signal input ends of two adjacent stages of driving units input opposite signals;
the control end of the pull-down module is electrically connected with the output end of the pull-down control module, the input end of the pull-down module is electrically connected with the second level signal input end of the driving unit, the first output end of the pull-down module is electrically connected with the control node, and the second output end of the pull-down module is electrically connected with the first output end of the driving unit;
the third output end of the pull-down module is electrically connected with the control node of the previous-stage driving unit, and the fourth output end of the pull-down module is electrically connected with the first output end of the previous-stage driving unit;
the driving method includes:
a pre-charging stage, controlling the pre-charging module to pull up the potential of the control node;
in the pull-up stage, the pull-up module is controlled to output a scanning signal at a first output end of the drive unit of the current stage;
in the resetting stage, the pull-up module is controlled to stop outputting scanning signals, and the potential of the control node is pulled down;
a pull-down maintaining stage, controlling the pull-down module to pull down the control node of the current-stage driving unit and the potential of the first output end according to the first control signal input by the first control signal input end, and to maintain the pull-down module in a low level state, and controlling the pull-down module to pull down the control node of the previous-stage driving unit and the potential of the first output end, and to maintain the pull-down module in a low level state;
and stopping working according to a second control signal input by the first control signal input end.
According to the technical scheme provided by the embodiment of the invention, the pull-down module not only can pull down the control node of the drive unit of the current stage and the electric potential of the first output end, but also can pull down the control node P of the drive unit of the previous stage and the electric potential of the first output end. That is, the control node of the present stage driving unit and the potential of the first output terminal may be alternately pulled down to a low potential by the pull-down module of the present stage driving unit and the pull-down module of the next stage driving unit, and maintained at the low potential. Compared with the prior art, on the basis of ensuring the service life of the circuit, each stage of driving unit only needs to be provided with one set of pull-down system (pull-down module), so that the pull-down effect can be realized, the area of the circuit can be saved, and the power consumption can be reduced.
Drawings
Fig. 1 is a circuit structure diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 2A is a circuit structure diagram of another gate driving circuit according to an embodiment of the invention;
fig. 2B is a circuit structure diagram of another gate driving circuit according to an embodiment of the invention;
fig. 2C is a circuit structure diagram of another gate driving circuit according to an embodiment of the invention;
fig. 3A is a circuit structure diagram of another gate driving circuit according to an embodiment of the invention;
fig. 3B is a driving timing diagram according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a circuit structure diagram of a gate driving circuit according to an embodiment of the present invention. Referring to fig. 1, the gate driving circuit includes:
the driving unit comprises a plurality of cascaded driving units, wherein each driving unit comprises a pre-charging module 11, an upward-pulling module 12, a resetting module 13, a downward-pulling control module 14 and a downward-pulling module 15;
the output end of the pre-charging module 11 is electrically connected with the control node P and is used for pre-charging the control node P;
the control end of the pull-up module 12 is electrically connected to the control node P, the input end of the pull-up module 12 is electrically connected to the first clock signal input end CK1 of the driving unit, and the first output end of the pull-up module 12 is electrically connected to the first output end GOUT of the driving unit, and is configured to output a scan signal at the first output end GOUT of the driving unit;
the output end of the reset module 13 is electrically connected with the control node and used for pulling down the potential of the control node;
a first control end of the pull-down control module 14 is electrically connected with the control node P, a second control end of the pull-down control module 14 is electrically connected with a first control signal input end VIN of the driving unit, and a first input end of the pull-down control module 14 is electrically connected with a first level signal input end VSQ of the driving unit; the first control signal input end VIN of the adjacent two stages of driving units inputs opposite signals;
the control end of the pull-down module 15 is electrically connected to the output end of the pull-down control module 14, the input end of the pull-down module is electrically connected to the second level signal input end VGL of the driving unit, the first output end a1 of the pull-down module 15 is electrically connected to the control node P, the second output end a2 of the pull-down module 15 is electrically connected to the first output end GOUT of the driving unit, and the pull-down module 15 is configured to pull down the potentials of the control node P and the first output end GOUT of the driving unit of the current stage;
the third output end A3 of the pull-down module 15 is electrically connected to the control node P of the previous stage of driving unit, the fourth output end a4 of the pull-down module 15 is electrically connected to the first output end GOUT of the previous stage of driving unit, and the pull-down module 15 is further configured to pull down the potentials of the control node P and the first output end GOUT of the previous stage of driving unit.
According to the technical solution provided by the embodiment of the present invention, the pull-down module 15 can pull down the control node P of the current-stage driving unit and the potential of the first output terminal GOUT, and can also pull down the control node P of the previous-stage driving unit and the potential of the first output terminal GOUT. That is, the control node of the present stage driving unit and the potential of the first output terminal may be alternately pulled down to a low potential by the pull-down module of the present stage driving unit and the pull-down module of the next stage driving unit, and maintained at the low potential. Compared with the prior art, on the basis of ensuring the service life of the circuit, each stage of driving unit only needs to be provided with one set of pull-down system (pull-down module), so that the pull-down effect can be realized, the area of the circuit can be saved, and the power consumption can be reduced.
Fig. 2A is a circuit structure diagram of another gate driving circuit according to an embodiment of the present invention. Referring to fig. 2A, on the basis of the gate driving circuit shown in fig. 1, in the gate driving circuit provided in the embodiment of the present invention, the pull-up module 12 further includes a second output terminal, and the pull-down module 15 further includes a fifth output terminal a5 and a sixth output terminal a 6;
the fifth output end a5 of the pull-down module 15 and the second output end of the pull-up module 12 are electrically connected to the second output end ZOUT of the current-stage driving unit, and the pull-down module 15 is further configured to pull down the potential of the second output end ZOUT of the current-stage driving unit;
the sixth output end a6 of the pull-down module 15 is electrically connected to the second output end ZOUT of the previous stage of driving unit, and the pull-down module 15 is further configured to pull down the potential of the second output end ZOUT of the previous stage of driving unit.
Fig. 2B is a circuit structure diagram of another gate driving circuit according to an embodiment of the present invention. Based on the gate driving circuit shown in fig. 2A, in the gate driving circuit provided in the embodiment of the present invention, the input terminal GN of the pre-charge module 11 is electrically connected to the first output terminal GOUT of the previous nth stage driving unit, and the control terminal ZN of the pre-charge module 11 is electrically connected to the second output terminal ZOUT of the previous nth stage driving unit; wherein N is a positive integer. That is, the pre-charge module 11 of the current stage driving unit can pre-charge the control node P of the current stage according to the signals output by the first output terminal GOUT and the second output terminal ZOUT of the previous N-pole driving unit. For example, the pre-charge module 11 of the driving unit of the current stage may pre-charge the control node P of the driving unit of the current stage according to the signals output by the first output terminal GOUT and the second output terminal ZOUT of the driving units of the previous two stages of the driving unit of the current stage. The present-stage driving pre-charge module 11 pre-charges the control node P of the present-stage driving unit according to the signals output by the previous-stage driving units, and does not need to use external signals for control, thereby saving external control signals and reducing cost.
The pre-charge module 11 may include a first transistor M1, a control terminal of the first transistor M1 is electrically connected to a control terminal ZN of the pre-charge module 11, a first pole of the first transistor M1 is electrically connected to an input terminal GN of the pre-charge module 11, and a second pole of the first transistor M1 is electrically connected to an output terminal of the pre-charge module 11.
With continued reference to fig. 2B, in the gate driving circuit provided in the embodiment of the present invention, the reset module 13 includes an input terminal and a control terminal GM; the control end GM of the reset module 13 is electrically connected to the first output end GOUT of the M-th driving unit, and the input end of the reset module 13 is electrically connected to the second clock signal input end CK2 of the driving unit, where M is a positive integer. That is to say, the reset module 13 of the current-stage driving unit can pull down the potential of the current-stage control node P according to the signal output by the first output terminal GOUT of the last M-pole driving unit. For example, the reset module 13 of the driving unit of the current stage may pull down the potential of the control node P of the driving unit of the current stage according to the signal output by the first output terminal GOUT of the driving unit of the next two stages of the driving unit of the current stage. The reset module 13 of the driving unit of this stage pulls down the potential of the control node P according to the signal output by the first output end of the driving units of the next stages, and does not need to use an external signal for control, thereby saving an external control signal and reducing the cost.
Further, the reset module 13 further includes a second transistor M2;
the gate of the second transistor M2 is electrically connected to the control terminal GM of the reset module 13, the first pole of the second transistor M2 is electrically connected to the input terminal of the reset module 13, that is, to the second clock signal input terminal CK2 of the driving unit of the current stage, and the second pole of the second transistor is electrically connected to the output terminal of the reset module 13. The reset module 13 can be turned on and off according to the signal input by the control terminal thereof, and when the reset module 13 is turned on, the signal input by the input terminal thereof is transmitted to the control node P to reset the control node P, for example, the low level signal input by the input terminal thereof is transmitted to the control node P, and the potential of the control node P is pulled down.
In an embodiment of the present invention, the pull-up module 12 may include a third transistor M3, a fourth transistor M4, and a first capacitor C1.
The gate of the third transistor M3 is electrically connected to the control end of the pull-up module 12, the first pole of the third transistor M3 is electrically connected to the input end of the pull-up module 12, that is, the first pole of the third transistor M3 is electrically connected to the first clock signal input end CK1 of the present stage driving unit, and the second pole of the third transistor M3 is electrically connected to the first output end of the pull-up module 12;
the gate of the fourth transistor M4 is electrically connected to the control terminal of the pull-up module 12, the first electrode of the fourth transistor M4 is electrically connected to the input terminal of the pull-up module 12, that is, the first electrode of the fourth transistor M4 is electrically connected to the first clock signal input terminal CK1 of the driving unit, and the second electrode of the fourth transistor M4 is electrically connected to the second output terminal of the pull-up module 12.
A first pole of the first capacitor C1 is electrically connected to the control node P, and a second pole of the first capacitor C1 is electrically connected to the first output terminal GOUT of the present stage of driving unit.
In an embodiment of the present invention, the pull-down control module 14 may include a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7;
the gate of the fifth transistor M5 is electrically connected to the first control end of the pull-down control module 14, the first electrode of the fifth transistor M5 is electrically connected to the input end of the pull-down control module 14, and the second electrode of the fifth transistor M5 is electrically connected to the output end of the pull-down control module 14;
the gate and the first pole of the sixth transistor M6 are electrically connected to the second control end of the pull-down control module 14, and the second pole of the sixth transistor M6 is electrically connected to the gate of the seventh transistor M7;
a first electrode of the seventh transistor M7 is electrically connected to the second control terminal of the pull-down control module 14, and a second electrode of the seventh transistor M7 is electrically connected to the output terminal of the pull-down control module 14.
Optionally, with continued reference to fig. 2B, in the gate driving circuit provided in the embodiment of the invention, the pull-down module 15 may include an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;
the gate of the eighth transistor M8 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the eighth transistor M8 is electrically connected to the input terminal of the pull-down module 15, and the second electrode of the eighth transistor M8 is electrically connected to the first output terminal of the pull-down module 15;
the gate of the ninth transistor M9 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the ninth transistor M9 is electrically connected to the input terminal of the pull-down module 15, and the second electrode of the ninth transistor M9 is electrically connected to the second output terminal of the pull-down module 15;
a gate of the tenth transistor M10 is electrically connected to the control terminal of the pull-down module 15, a first electrode of the tenth transistor M10 is electrically connected to the input terminal of the pull-down module 15, and a second electrode of the tenth transistor M10 is electrically connected to the fifth output terminal of the pull-down module 15;
a gate of the eleventh transistor M11 is electrically connected to the control terminal of the pull-down module 15, a first electrode of the eleventh transistor M11 is electrically connected to a second electrode of the eighth transistor M8, and a second electrode of the eleventh transistor M11 is electrically connected to the third output terminal of the pull-down module 15;
the gate of the twelfth transistor M12 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the twelfth transistor M12 is electrically connected to the second electrode of the ninth transistor M9, and the second electrode of the twelfth transistor M12 is electrically connected to the fourth output terminal of the pull-down module 15;
the gate of the thirteenth transistor M13 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the thirteenth transistor M13 is electrically connected to the second electrode of the tenth transistor M10, and the second electrode of the thirteenth transistor M13 is electrically connected to the sixth output terminal of the pull-down module 15.
Referring to fig. 2C, fig. 2C is a circuit structure diagram of another gate driving circuit according to an embodiment of the present invention. In this circuit, the pull-down module 15 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;
the gate of the eighth transistor M8 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the eighth transistor M8 is electrically connected to the input terminal of the pull-down module 15, and the second electrode of the eighth transistor M8 is electrically connected to the first output terminal of the pull-down module 15;
the gate of the ninth transistor M9 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the ninth transistor M9 is electrically connected to the input terminal of the pull-down module 15, and the second electrode of the ninth transistor M9 is electrically connected to the second output terminal of the pull-down module 15;
a gate of the tenth transistor M10 is electrically connected to the control terminal of the pull-down module 15, a first electrode of the tenth transistor M10 is electrically connected to the input terminal of the pull-down module 15, and a second electrode of the tenth transistor M10 is electrically connected to the fifth output terminal of the pull-down module 15;
a gate of the eleventh transistor M11 is electrically connected to the control terminal of the pull-down module 15, a first electrode of the eleventh transistor M11 is electrically connected to the input terminal of the pull-down module 15, and a second electrode of the eleventh transistor M11 is electrically connected to the third output terminal of the pull-down module 15;
the gate of the twelfth transistor M12 is electrically connected to the control terminal of the pull-down module 15, the first electrode of the twelfth transistor M12 is electrically connected to the input terminal of the pull-down module 15, and the second electrode of the twelfth transistor M12 is electrically connected to the fourth output terminal of the pull-down module 15;
the gate of the thirteenth transistor is electrically connected to the control terminal of the pull-down module 15, the first electrode of the thirteenth transistor M13 is electrically connected to the input terminal of the pull-down module 15, and the second electrode of the thirteenth transistor M13 is electrically connected to the sixth output terminal of the pull-down module 15.
Fig. 3A is a driving timing diagram provided by an embodiment of the present invention, and fig. 3B is a driving timing diagram provided by an embodiment of the present invention, in which circuit connections of a kth stage driving unit and a (k +1) th stage driving unit are exemplarily shown. The operation of the gate driving circuit according to the embodiment of the present invention is described below by taking the kth stage driving unit and the (k +1) th stage driving unit as examples, where k is an integer. Referring to fig. 3A and 3B, CLK1 represents the clock signal input from the first clock signal input terminal CK1 of the kth-stage driving unit, and CLK2 is the clock signal input from the second clock signal input terminal CK2 of the kth-stage driving unit and the first clock signal input terminal CK1 of the (k +1) -th-stage driving unit; the CLK3 is a clock signal input from the second clock signal input terminal CK2 of the (k +1) th stage driving unit. GN (k)/ZN (k) represents signals input from the input terminal GN and the control terminal ZN of the precharge module 11 of the kth stage driving unit, GOUT (k)/ZOUT (k) represents signals output from the first output terminal GOUT and the second output terminal ZOUT of the kth stage driving unit, and GM (k) represents a signal input from the control terminal GM of the reset module 13 of the kth stage driving unit. PU1 represents the potential of the control node P1 of the kth stage drive unit. GN (k +1)/ZN (k +1) denotes signals input from the input terminal GN and the control terminal ZN of the precharge module 11 of the (k +1) -th stage driving unit, GOUT (k +1)/ZOUT (k +1) denotes signals output from the first output terminal GOUT and the second output terminal ZOUT of the (k +1) -th stage driving unit, and GM (k +1) denotes a signal input from the control terminal GM of the reset module of the (k +1) -th stage driving unit. PU2 represents the potential of the control node P2 of the k +1 th stage drive unit. The first level signal input terminal VSQ and the second level signal input terminal VGL input low level signals. The first control signal input terminal V1 of the kth stage driving unit inputs a low level signal, and the second control signal input terminal V2 of the (k +1) th stage driving unit inputs a high level signal.
Illustratively, the first control signal input terminal VIN of the kth stage driving unit inputs a low level signal, and the first control signal input terminal VIN of the (k +1) th stage driving unit inputs a high level signal. The input end and the control end of a precharge module of the kth-stage driving unit are respectively and electrically connected with the first output end and the second output end of the kth-2-stage driving unit. The control end of the reset module of the kth stage driving unit is electrically connected to the first output end of the (k + 2) th stage driving unit, and the working process of the kth stage driving unit in the gate driving circuit may include the following stages:
in the first stage t1, also called as the precharge stage, the first output terminal and the second output terminal of the k-2 stage driving unit output high level signals, that is, the control terminal ZN and the input terminal GN of the precharge module 11 both input high level signals, the first transistor M1 is turned on, the high level signal input by the first stage of the first transistor M1 is transmitted to the control node P1 through the turned-on first transistor M1, the control node P1 is charged, the potential of the control node P1 becomes high level, the third transistor M3 and the fourth transistor M4 are turned on, the low level signal input by the first clock signal input terminal CK1 is transmitted to the first output terminal GOUT of the driving unit through the turned-on third transistor M3, and is transmitted to the second output terminal ut of the driving unit through the turned-on fourth transistor M4, and the first output terminal GOUT and the second output terminal ZOUT of the driving unit output low level signals.
In the second stage t2, also called the pull-up stage, the high level signal is input from the first clock signal input terminal CK1, the high level signal input from the first clock signal input terminal CK1 is transmitted to the first output terminal GOUT of the driving unit through the turned-on third transistor M3, and is transmitted to the second output terminal ZOUT of the driving unit through the fourth transistor M4 of the turn-on transistor, and the first output terminal GOUT and the second output terminal ZOUT of the driving unit output the high level signal. And the potential of the control node P1 will rise due to the bootstrap effect of the first capacitor C1. The high-level potential of the control node P1 can make the third transistor M3 and the fourth transistor M4 turn on more fully, improving the driving capability of the driving unit.
In the third stage t3, also called the reset stage, the first output terminal of the (k + 2) th stage driving unit outputs a high-level signal, and the second transistor M2 is turned on. In the first half period of the period, the second clock signal input terminal CK2 inputs a high level signal, the high level signal input from the second clock signal input terminal CK2 is transmitted to the control node P1 through the turned-on second transistor M2, and the potential of the control node P1 is at a high level. The third transistor M3 is turned on continuously, the first clock signal input terminal CK1 inputs a low level signal, the low level signal input from the first clock signal input terminal CK1 is transmitted to the first output terminal GOUT of the driving unit through the turned-on third transistor M3, and is transmitted to the second output terminal ZOUT of the driving unit through the turned-on fourth transistor M4, the first output terminal GOUT and the second output terminal ZOUT of the driving unit output low level signals, and the potential of the control node P1 is pulled down to a certain extent due to the bootstrap effect of the first capacitor C1. In the second half period of the period, the second clock signal input terminal CK2 inputs a low level signal, the potential of the control node P1 is pulled low, and the potential of the control node P1 is at a low level. The third transistor M3 and the fourth transistor M4 are turned off, and the first output terminal GOUT and the second output terminal ZOUT of the driving unit output low level signals.
In the fourth phase t4, also called the pull-down sustain phase, the control node P2 in the (k +1) th stage driving unit is at a low level, and the fifth transistor M5 in the (k +1) th stage driving unit is turned off. Since the first control signal input terminal V2 of the (k +1) th stage driving unit inputs a high level signal, the sixth transistor M6 and the seventh transistor M7 of the (k +1) th stage driving unit are turned on, the second pole of the seventh transistor M7 outputs a high level signal, the high level signal controls the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 in the (k +1) -th stage driving unit to be turned on, a low level signal input by the second level signal input terminal VGL of the (k +1) -th stage driving unit is transmitted to the control node P2, the first output terminal GOUT and the second output terminal ZOUT of the stage driving unit through the turned-on eighth transistor M8, the ninth transistor M9 and the tenth transistor M10, respectively, and the potentials of the control node P2, the first output terminal GOUT and the second output terminal ZOUT of the stage driving unit are pulled down. The low level signal input from the second level signal input terminal of the (k +1) -th stage driving unit is transmitted to the control node P1, the first output terminal GOUT and the second output terminal ZOUT of the kth stage driving unit through the turned-on eleventh transistor M11, twelfth transistor M12 and thirteenth transistor M13, respectively, the potentials of the control node P1, the first output terminal GOUT and the second output terminal ZOUT of the kth stage driving unit are pulled down, and the potentials of the control node P1, the first output terminal GOUT and the second output terminal GOUT of the kth stage driving unit are maintained at a low level. In the above description, the driving unit refers to a k-th stage driving unit, as not particularly limited.
It should be noted that the signal inputted from the first control signal input terminal V1 of the kth stage driving unit is opposite to the signal inputted from the first control signal input terminal V2 of the (k +1) th stage driving unit, and remains unchanged within one frame, and cyclically alternates from frame to frame. For example, in the first frame, the first control signal input terminal V1 of the kth-stage driving unit inputs a high level signal, the first control signal input terminal V2 of the (k +1) -stage driving unit inputs a low level signal, in the second frame, the first control signal input terminal V1 of the kth-stage driving unit inputs a low level signal, and the first control signal input terminal V2 of the (k +1) -stage driving unit inputs a high level signal; in the third frame, the first control signal input terminal V1 of the kth-stage driving unit inputs a high level signal, and the first control signal input terminal V2 of the (k +1) -th-stage driving unit inputs a low level signal. The above steps are cyclically and alternately changed.
Illustratively, taking the 8-stage driving module as an example, the maintaining process of controlling the potentials of the node, the first output terminal and the second output terminal in the pull-down maintaining stage is described.
TABLE 1
TABLE 2
It can be seen that the pull-down template of the (k +1) th stage driving unit can not only pull down the potentials of the control node, the first output terminal and the second output terminal of the present stage in the pull-down maintaining stage. And the potentials of the control node, the first output terminal and the second output terminal of the kth stage driving unit may be pulled down. Each stage of driving unit only needs to be provided with one set of pull-down system (pull-down module), so that the normal work of the whole grid driving circuit can be realized, circuit elements are saved, and the circuit area is reduced. Each stage of driving unit only has one set of pull-down maintaining system, and between frames, the pull-down systems of odd-stage driving units and the pull-down systems of even-stage driving units work alternately, so that only the pull-down systems of odd-stage or even-stage are working in one frame time, and the pull-down maintaining function of the driving unit of the previous stage can be driven at the same time, therefore, the circuit can not only display normally, but also ensure the service life of the circuit. In addition, the pull-down system of the one-stage circuit is used for maintaining the pull-down low potential of the two-stage driving unit within one frame time, and the power consumption of the circuit is reduced.
It should be noted that, in the embodiment of the present invention, the first pole and the second pole of any transistor are source-drain poles, that is, for any transistor, when the first pole is the source pole, the second pole is the drain pole; the first pole is the drain, the second pole is the source.
The embodiment of the invention also provides a driving method of the gate driving circuit, wherein the gate driving circuit comprises:
each stage of driving unit comprises a pre-charging module, a pull-up module, a reset module, a pull-down control module and a pull-down module;
the output end of the pre-charging module is electrically connected with the control node;
the control end of the pull-up module is electrically connected with the control node, the input end of the pull-up module is electrically connected with the first clock signal input end of the driving unit, and the first output end of the pull-up module is electrically connected with the first output end of the driving unit;
the output end of the reset module is electrically connected with the control node;
the control end of the pull-down control module is electrically connected with the control node, the input end of the pull-down control module is electrically connected with the first level signal input end of the driving unit, and the second input end of the pull-down control module is electrically connected with the second level signal input end of the driving unit; the first level signal input ends of two adjacent stages of driving units input opposite signals;
the control end of the pull-down module is electrically connected with the output end of the pull-down control module, the first output end of the pull-down module is electrically connected with the control node, the second output end of the pull-down module is electrically connected with the first output end of the driving unit, the third output end of the pull-down module is electrically connected with the control node of the previous driving unit, and the fourth output end of the pull-down module is electrically connected with the first output end of the previous driving unit;
the driving method provided by the embodiment of the invention can be used for driving the gate driving circuit provided by any embodiment of the invention.
The driving method includes:
a precharge stage, controlling the precharge module 11 to pull up the potential of the control node P;
in the pull-up stage, the pull-up module 12 is controlled to output a scan signal at the first output terminal GOUT of the current-stage driving unit;
in the reset stage, the pull-up module 12 is controlled to stop outputting the scanning signal, and the potential of the control node P is pulled down;
a pull-down maintaining stage, controlling the pull-down module 15 to pull down the control node P of the current-stage driving unit and the potential of the first output terminal GOUT according to a first control signal input by the first control signal input terminal, and maintaining the pull-down module at a low level state, and controlling the pull-down module 15 to pull down the control node P of the previous-stage driving unit and the potential of the first output terminal GOUT, and maintaining the pull-down module at the low level state;
and stopping working according to a second control signal input by the first control signal input end.
The first level signal and the second level signal are opposite signals, for example, the first level signal is a high level signal, and the second level signal is a low level signal. Or the first level signal is a low level signal and the second level signal is a high level signal.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A gate drive circuit, comprising: the driving units at each stage comprise a pre-charging module, a pull-up module, a reset module, a pull-down control module and a pull-down module;
the output end of the pre-charging module is electrically connected with the control node and is used for pre-charging the control node;
the control end of the pull-up module is electrically connected with the control node, the input end of the pull-up module is electrically connected with the first clock signal input end of the driving unit, and the first output end of the pull-up module is electrically connected with the first output end of the driving unit and is used for outputting a scanning signal at the first output end of the driving unit;
the output end of the reset module is electrically connected with the control node and used for pulling down the potential of the control node;
a first control end of the pull-down control module is electrically connected with the control node, a second control end of the pull-down control module is electrically connected with a first control signal input end of the driving unit, and an input end of the pull-down control module is electrically connected with a first level signal input end of the driving unit; the first control signal input ends of two adjacent stages of driving units input opposite signals;
the control end of the pull-down module is electrically connected with the output end of the pull-down control module, the input end of the pull-down module is electrically connected with the second level signal input end of the driving unit, the first output end of the pull-down module is electrically connected with the control node, the second output end of the pull-down module is electrically connected with the first output end of the driving unit, and the pull-down module is used for pulling down the control node and the potential of the first output end of the driving unit;
the third output end of the pull-down module is electrically connected with the control node of the previous-stage driving unit, the fourth output end of the pull-down module is electrically connected with the first output end of the previous-stage driving unit, and the pull-down module is also used for pulling down the control node of the previous-stage driving unit and the potential of the first output end.
2. The circuit of claim 1, wherein the pull-up module further comprises a second output, and wherein the pull-down module further comprises a fifth output and a sixth output;
the fifth output end of the pull-down module and the second output end of the pull-up module are electrically connected with the second output end of the current-stage driving unit, and the pull-down module is further used for pulling down the potential of the second output end of the current-stage driving unit;
and the sixth output end of the pull-down module is electrically connected with the second output end of the previous-stage driving unit, and the pull-down module is also used for pulling down the potential of the second output end of the previous-stage driving unit.
3. The circuit of claim 2, wherein the input terminal of the pre-charge module is electrically connected to the first output terminal of the previous nth stage driving unit, and the control terminal of the pre-charge module is electrically connected to the second output terminal of the previous nth stage driving unit; wherein N is an integer;
the pre-charging module comprises a first transistor, a grid electrode of the first transistor is electrically connected with a control end of the pre-charging module, a first electrode of the first transistor is electrically connected with an input end of the pre-charging module, and a second electrode of the first transistor is electrically connected with an output end of the pre-charging module.
4. The circuit of claim 1, wherein the reset module comprises an input terminal and a control terminal; the control end of the reset module is electrically connected with the first output end of the rear Mth-stage driving unit, the input end of the reset module is electrically connected with the second clock signal input end of the current-stage driving unit, and M is a positive integer.
5. The circuit of claim 4, wherein the reset module further comprises a second transistor;
the grid electrode of the second transistor is electrically connected with the control end of the reset module, the first electrode of the second transistor is electrically connected with the input end of the reset module, and the second electrode of the second transistor is electrically connected with the output end of the reset module.
6. The circuit of claim 2, wherein the pull-up module comprises a third transistor, a fourth transistor, and a first capacitor;
the grid electrode of the third transistor is electrically connected with the control end of the pull-up module, the first electrode of the third transistor is electrically connected with the input end of the pull-up module, and the second electrode of the third transistor is electrically connected with the first output end of the pull-up module;
a grid electrode of the fourth transistor is electrically connected with the control end of the pull-up module, a first electrode of the fourth transistor is electrically connected with the input end of the pull-up module, and a second electrode of the fourth transistor is electrically connected with the second output end of the pull-up module;
the first pole of the first capacitor is electrically connected with the control node, and the second pole of the first capacitor is electrically connected with the first output end of the current-stage driving unit.
7. The circuit of claim 2, wherein the pull-down control module comprises a fifth transistor, a sixth transistor, and a seventh transistor;
a grid electrode of the fifth transistor is electrically connected with a first control end of the pull-down control module, a first electrode of the fifth transistor is electrically connected with an input end of the pull-down control module, and a second electrode of the fifth transistor is electrically connected with an output end of the pull-down control module;
the grid electrode and the first electrode of the sixth transistor are electrically connected with the second control end of the pull-down control module, and the second electrode of the sixth transistor is electrically connected with the grid electrode of the seventh transistor;
and a first electrode of the seventh transistor is electrically connected with the second control end of the pull-down control module, and a second electrode of the seventh transistor is electrically connected with the output end of the pull-down control module.
8. The circuit of claim 2, wherein the pull-down module comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
a grid electrode of the eighth transistor is electrically connected with the control end of the pull-down module, a first electrode of the eighth transistor is electrically connected with the input end of the pull-down module, and a second electrode of the eighth transistor is electrically connected with the first output end of the pull-down module;
the grid electrode of the ninth transistor is electrically connected with the control end of the pull-down module, the first electrode of the ninth transistor is electrically connected with the input end of the pull-down module, and the second electrode of the ninth transistor is electrically connected with the second output end of the pull-down module;
a gate of the tenth transistor is electrically connected with the control end of the pull-down module, a first electrode of the tenth transistor is electrically connected with the input end of the pull-down module, and a second electrode of the tenth transistor is electrically connected with a fifth output end of the pull-down module;
a gate of the eleventh transistor is electrically connected with the control end of the pull-down module, a first electrode of the eleventh transistor is electrically connected with a second electrode of the eighth transistor, and the second electrode of the eleventh transistor is electrically connected with a third output end of the pull-down module;
a gate of the twelfth transistor is electrically connected with the control end of the pull-down module, a first electrode of the twelfth transistor is electrically connected with a second electrode of the ninth transistor, and the second electrode of the twelfth transistor is electrically connected with a fourth output end of the pull-down module;
the gate of the thirteenth transistor is electrically connected to the control end of the pull-down module, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the tenth transistor, and the second electrode of the thirteenth transistor is electrically connected to the sixth output end of the pull-down module.
9. The circuit of claim 2, wherein the pull-down module comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
a grid electrode of the eighth transistor is electrically connected with the control end of the pull-down module, a first electrode of the eighth transistor is electrically connected with the input end of the pull-down module, and a second electrode of the eighth transistor is electrically connected with the first output end of the pull-down module;
the grid electrode of the ninth transistor is electrically connected with the control end of the pull-down module, the first electrode of the ninth transistor is electrically connected with the input end of the pull-down module, and the second electrode of the ninth transistor is electrically connected with the second output end of the pull-down module;
a gate of the tenth transistor is electrically connected with the control end of the pull-down module, a first electrode of the tenth transistor is electrically connected with the input end of the pull-down module, and a second electrode of the tenth transistor is electrically connected with a fifth output end of the pull-down module;
a grid electrode of the eleventh transistor is electrically connected with a control end of the pull-down module, a first electrode of the eleventh transistor is electrically connected with an input end of the pull-down module, and a second electrode of the eleventh transistor is electrically connected with a third output end of the pull-down module;
a grid electrode of the twelfth transistor is electrically connected with the control end of the pull-down module, a first electrode of the twelfth transistor is electrically connected with the input end of the pull-down module, and a second electrode of the twelfth transistor is electrically connected with the fourth output end of the pull-down module;
the grid electrode of the thirteenth transistor is electrically connected with the control end of the pull-down module, the first electrode of the thirteenth transistor is electrically connected with the input end of the pull-down module, and the second electrode of the thirteenth transistor is electrically connected with the sixth output end of the pull-down module.
10. A driving method of a gate driving circuit, the gate driving circuit comprising:
the driving units at each stage comprise a pre-charging module, a pull-up module, a reset module, a pull-down control module and a pull-down module;
the output end of the pre-charging module is electrically connected with the control node;
the control end of the pull-up module is electrically connected with the control node, the input end of the pull-up module is electrically connected with the first clock signal input end of the driving unit, and the first output end of the pull-up module is electrically connected with the first output end of the driving unit;
the output end of the reset module is electrically connected with the control node;
a first control end of the pull-down control module is electrically connected with the control node, a second control end of the pull-down control module is electrically connected with a first control signal input end of the driving unit, and an input end of the pull-down control module is electrically connected with a first level signal input end of the driving unit; the first control signal input ends of two adjacent stages of driving units input opposite signals;
the control end of the pull-down module is electrically connected with the output end of the pull-down control module, the input end of the pull-down module is electrically connected with the second level signal input end of the driving unit, the first output end of the pull-down module is electrically connected with the control node, and the second output end of the pull-down module is electrically connected with the first output end of the driving unit;
the third output end of the pull-down module is electrically connected with the control node of the previous-stage driving unit, and the fourth output end of the pull-down module is electrically connected with the first output end of the previous-stage driving unit;
the driving method includes:
a pre-charging stage, controlling the pre-charging module to pull up the potential of the control node;
in the pull-up stage, the pull-up module is controlled to output a scanning signal at a first output end of the drive unit of the current stage;
in the resetting stage, the pull-up module is controlled to stop outputting scanning signals, and the potential of the control node is pulled down;
a pull-down maintaining stage, controlling the pull-down module to pull down the control node of the current-stage driving unit and the potential of the first output end according to the first control signal input by the first control signal input end, and to maintain the pull-down module in a low level state, and controlling the pull-down module to pull down the control node of the previous-stage driving unit and the potential of the first output end, and to maintain the pull-down module in a low level state;
and stopping working according to a second control signal input by the first control signal input end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710295905.XA CN106910451B (en) | 2017-04-28 | 2017-04-28 | Gate drive circuit and drive method of gate drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710295905.XA CN106910451B (en) | 2017-04-28 | 2017-04-28 | Gate drive circuit and drive method of gate drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106910451A CN106910451A (en) | 2017-06-30 |
| CN106910451B true CN106910451B (en) | 2020-09-29 |
Family
ID=59211380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710295905.XA Active CN106910451B (en) | 2017-04-28 | 2017-04-28 | Gate drive circuit and drive method of gate drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106910451B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107331418B (en) * | 2017-07-31 | 2020-06-19 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN109841194B (en) * | 2017-11-27 | 2020-04-10 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN107800280B (en) * | 2017-12-12 | 2019-08-30 | 上海贝岭股份有限公司 | The driving circuit of power switch |
| CN110223655A (en) * | 2019-06-28 | 2019-09-10 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426414A (en) * | 2013-07-16 | 2013-12-04 | 北京京东方光电科技有限公司 | Shifting register unit and driving method thereof, gate driving circuit and display device |
| KR20140148235A (en) * | 2013-06-21 | 2014-12-31 | 엘지디스플레이 주식회사 | Shift register and display device using the same |
| CN104318909A (en) * | 2014-11-12 | 2015-01-28 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, drive method thereof, and display panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9501989B2 (en) * | 2014-04-29 | 2016-11-22 | Shenzhen China Star Optoelectronics Technology Co. | Gate driver for narrow bezel LCD |
| CN104050941B (en) * | 2014-05-27 | 2016-03-30 | 深圳市华星光电技术有限公司 | A kind of gate driver circuit |
| CN104835475B (en) * | 2015-06-08 | 2017-03-29 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN105261341B (en) * | 2015-11-11 | 2017-11-03 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and display device |
-
2017
- 2017-04-28 CN CN201710295905.XA patent/CN106910451B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140148235A (en) * | 2013-06-21 | 2014-12-31 | 엘지디스플레이 주식회사 | Shift register and display device using the same |
| CN103426414A (en) * | 2013-07-16 | 2013-12-04 | 北京京东方光电科技有限公司 | Shifting register unit and driving method thereof, gate driving circuit and display device |
| CN104318909A (en) * | 2014-11-12 | 2015-01-28 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, drive method thereof, and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106910451A (en) | 2017-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3214616B1 (en) | Goa unit and drive method, goa circuit, and display device | |
| CN103761937B (en) | Shifting register unit, gate driving circuit, driving method of gate driving circuit and display device | |
| KR102080730B1 (en) | Bidirectional scanning gate driving circuit | |
| US10121436B2 (en) | Shift register, a gate driving circuit, a display panel and a display apparatus | |
| CN107507556B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| JP6423957B2 (en) | Gate electrode drive circuit based on IGZO manufacturing process | |
| JP6329691B2 (en) | Gate electrode drive circuit with bootstrap function | |
| US9269455B2 (en) | Shift register unit, gate driving circuit, array substrate and display apparatus | |
| CN108806584B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN104778928B (en) | A kind of shift register, gate driver circuit, display floater and display device | |
| WO2017185590A1 (en) | Shift register unit, gate driving circuit and driving method therefor, and display device | |
| JP6423956B2 (en) | Gate electrode drive circuit based on IGZO manufacturing process | |
| EP3296997B1 (en) | Shift register and driving method therefor, gate drive circuit and display apparatus | |
| WO2016161726A1 (en) | Shift register unit, gate electrode driver device, and display device | |
| CN106910451B (en) | Gate drive circuit and drive method of gate drive circuit | |
| EP3041000A1 (en) | Shift register unit, shift register, and display device | |
| WO2019100822A1 (en) | Shift register, drive method therefor, gate drive circuit, and display device | |
| WO2016161725A1 (en) | Shift register unit, gate electrode driver device, and display device | |
| EP2966649A1 (en) | Shift register, gate electrode driver circuit, array substrate, and display device | |
| CN104361852A (en) | Shifting register, gate drive circuit and display device | |
| CN108492793B (en) | Shift register, grid drive circuit and display device | |
| CN109427409B (en) | Shift register, grid driving circuit, display panel and driving method | |
| CN109658888B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN108154836B (en) | Shifting register unit, driving method thereof and grid driving circuit | |
| CN106898322B (en) | Shift register and driving method thereof, grid driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 215301 No. 1, Longteng Road, Kunshan Development Zone, Jiangsu, Suzhou Applicant after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301 No. 1, Longteng Road, Kunshan Development Zone, Jiangsu, Suzhou Applicant before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |