CN104361852A - Shifting register, gate drive circuit and display device - Google Patents
Shifting register, gate drive circuit and display device Download PDFInfo
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- CN104361852A CN104361852A CN201410710826.7A CN201410710826A CN104361852A CN 104361852 A CN104361852 A CN 104361852A CN 201410710826 A CN201410710826 A CN 201410710826A CN 104361852 A CN104361852 A CN 104361852A
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Abstract
The invention discloses a shifting register, a gate drive circuit and a display device. The shifting register comprises a pre-charging module, an upward pulling module and N downward pulling modules. The output end of the pre-charging module and the input end of the upward pulling module are electrically connected to an upward pulling node. The output end of the upward pulling module is electrically connected to the output end of the shifting register. The output ends of the N downward pulling modules are electrically connected to the output end of the shifting register. The control ends of the N downward pulling modules are electrically connected with the output end of the pre-charging module. The input ends of the N downward pulling modules are electrically connected to N signal ends in a one-to-one corresponding mode. By means of control of N signals provided by the N signal ends, the output end of the shifting register is made to output a signal of the output end of at least one downward pulling module in the downward-pulling period, it is ensured that the shifting register is long in service life, and power consumption is lowered.
Description
Technical Field
The invention relates to the technical field of gate driving, in particular to a shift register, a gate driving circuit and a display device.
Background
The gate driving circuit generally includes a plurality of shift registers, and controls the shift registers to scan the gate lines step by step through a timing sequence, thereby controlling the display device to display a picture. A shift register with low power consumption and long service life is the focus of research nowadays.
Disclosure of Invention
In view of this, the invention provides a shift register, a gate driving circuit and a display device, which reduce the power consumption of the shift register and prolong the service life of the shift register.
The following is the technical scheme provided by the invention:
a shift register, comprising: the device comprises a pre-charging module, a pull-up module, a first pull-down module and an Nth pull-down module, wherein N is an integer of at least 2;
the output end of the pre-charge module and the input end of the pull-up module are electrically connected to a pull-up node, and the output end of the pull-up module is electrically connected to the output end of the shift register;
the output ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the shift register, the control ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the pre-charge module, and the input ends of the first pull-down module to the Nth pull-down module are electrically connected to the corresponding first signal end to the corresponding Nth signal end respectively, so that the output end of the shift register outputs at least one signal of the output end of the pull-down module in a pull-down stage through control of the first signal to the Nth signal provided by the first signal end to the Nth signal end respectively.
Preferably, the first signal terminal to the nth signal terminal respectively provide the first signal to the nth signal according to a first preset frequency to an nth preset frequency corresponding to each of the first signal terminal to the nth signal terminal, wherein,
the first preset frequency to the Nth preset frequency are the same; or,
at least one of the first preset frequency to the Nth preset frequency is different.
Preferably, at least any two of the first to nth signals are supplied to the corresponding signal terminals at the same time.
Preferably, the first to nth pull-down modules have the same circuit structure, and the ith pull-down module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; wherein,
a gate electrode of the first transistor, a first electrode of the first transistor, and a first electrode of the second transistor are electrically connected to the i-th signal terminal, and a second electrode of the first transistor, a gate electrode of the second transistor, and a first electrode of the third transistor are electrically connected to each other;
a second electrode of the second transistor, a first electrode of the fourth transistor, and a gate electrode of the fifth transistor are electrically connected to each other;
a gate electrode of the third transistor and a gate electrode of the fourth transistor are electrically connected to the pull-up node, a second electrode of the third transistor, a second electrode of the fourth transistor, and a second electrode of the fifth transistor are electrically connected to a third voltage terminal, and a first electrode of the fifth transistor is electrically connected to an output terminal of the shift register, wherein 1< ═ i < ═ N.
Preferably, the width-to-length ratio of the third transistor is larger than the width-to-length ratio of the first transistor.
Preferably, the shift register further includes: the pull-up node reset module is used for resetting the potential of the pull-up node; wherein, pull-up node reset module includes: a sixth transistor;
a gate of the sixth transistor is electrically connected to the gate of the fifth transistor, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node.
Preferably, the pre-charging module is a bidirectional pre-charging module, and the bidirectional pre-charging module includes: an eighth transistor and a ninth transistor; wherein,
a gate electrode of the eighth transistor is electrically connected to a first driving signal terminal, a first electrode of the eighth transistor is electrically connected to a first voltage terminal, and a second electrode of the eighth transistor is electrically connected to the pull-up node;
a gate of the ninth transistor is electrically connected to a second driving signal terminal, a first electrode of the ninth transistor is electrically connected to the pull-up node, and a second electrode of the ninth transistor is electrically connected to a second voltage terminal.
Preferably, the drawing-up module includes: a capacitor and a tenth transistor; wherein,
the first plate of the capacitor and the gate of the tenth transistor are both electrically connected to the pull-up node, the second plate of the capacitor and the second electrode of the tenth transistor are both electrically connected to the output end of the shift register, and the first electrode of the tenth transistor is electrically connected to a clock signal end.
Preferably, the shift register further includes: an initialization module comprising a seventh transistor; wherein,
a gate of the seventh transistor is electrically connected to a third driving signal terminal, a first electrode of the seventh transistor is electrically connected to a fourth voltage terminal, and a second electrode of the seventh transistor is electrically connected to an output terminal of the shift register.
A grid driving circuit comprises a first-stage shift register to an Mth-stage shift register which are arranged along a first direction, wherein the first-stage shift register to the Mth-stage shift register are all the shift registers, and M is an integer larger than 1.
A display device comprises an array substrate, wherein the array substrate comprises a pixel unit array and a gate driving circuit used for driving the pixel unit array, and the gate driving circuit is the gate driving circuit.
Compared with the prior art, the technical scheme provided by the invention has at least one of the following advantages:
the invention provides a shift register, a grid drive circuit and a display device, wherein the shift register comprises: the device comprises a pre-charging module, a pull-up module, a first pull-down module and an Nth pull-down module, wherein N is an integer of at least 2; the output end of the pre-charge module and the input end of the pull-up module are electrically connected to a pull-up node, and the output end of the pull-up module is electrically connected to the output end of the shift register; the output ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the shift register, the control ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the pre-charge module, and the input ends of the first pull-down module to the Nth pull-down module are electrically connected to the corresponding first signal end to the corresponding Nth signal end respectively, so that the output end of the shift register outputs at least one signal of the output end of the pull-down module in a pull-down stage through control of the first signal to the Nth signal provided by the first signal end to the Nth signal end respectively.
As can be seen from the above, in the technical solution provided by the present invention, the first to nth pull-down modules are respectively controlled to operate by the first to nth signals, that is, in the pull-down stage, the first to nth pull-down modules can be independently controlled to enable the output end of the shift register to output a low potential signal, so that when any one pull-down module is damaged, the shift register can be increased in service life by outputting signals to the remaining pull-down modules. In addition, the technical scheme provided by the invention can also set a special frequency for each signal to enable the first pull-down module to the Nth pull-down module to work alternately, and the purpose of reducing power consumption is achieved by outputting a low-frequency signal at each signal end, and the pull-down modules working alternately can reduce the loss rate of the pull-down modules and further prolong the service life of the shift register.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another shift register provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of a timing signal according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another shift register provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the gate driving circuit generally includes a plurality of shift registers, and controls the shift registers to scan the gate lines step by controlling the time sequence, so as to control the display device to display the image. A shift register with low power consumption and long service life is the focus of research nowadays.
Based on this, embodiments of the present application provide a shift register, which is described in detail with reference to fig. 1 to 3.
Referring to fig. 1, a schematic structural diagram of a shift register provided in an embodiment of the present application is shown, where the shift register includes:
the shift register comprises a pre-charging module 1, an up-pulling module 2, an output end Gn of a shift register and first to Nth down-pulling modules 31 to 3N, wherein N is an integer of at least 2;
the pre-charge module 1 is used for controlling the potential of a pull-up node PU, wherein the output end of the pre-charge module 1 and the input end of the pull-up module 2 are electrically connected to the pull-up node PU, and the output end of the pull-up module 2 is electrically connected to the output end Gn of the shift register; the pull-up module 2 controls the potential of the pull-up node PU to enable the output end Gn of the shift register to output a high potential signal in the pull-up stage;
the output ends of the first to nth pull-down modules 31 to 3N are electrically connected to the output end Gn of the shift register, the control ends of the first to nth pull-down modules 31 to 3N are electrically connected to the output end of the pre-charging module 1, and the input ends of the first to nth pull-down modules 31 to 3N are respectively connected to the corresponding first to nth signal ends LC1 to LCn, and are used for respectively enabling the output end of the shift register to output a signal of the output end of at least one pull-down module during a pull-down stage through control of the first to nth signals provided by the first to nth signal ends LC1 to LCn.
In the gate driving circuit, the shift register is mainly divided into a pre-charge phase, a pull-up phase and a pull-down phase, wherein the pull-up phase needs to enable the output end Gn of the shift register to output a high-potential signal to the gate line, and the pull-down phase needs to enable the output end Gn of the shift register to output a low-potential signal to the gate line, so that the on-off condition of the transistor connected with the gate line is controlled. The pre-charge module 1 is used for controlling the electric potential of a pull-up node, and during a pull-up stage, the pre-charge module 1 controls the electric potential of the pull-up node, the pull-up module 2 is controlled by the electric potential of the pull-up node PU, and the pull-up module 2 outputs a high-potential signal under the control of the electric potential of the pull-up node PU, so that the output terminal Gn of the shift register connected with the pull-up module outputs the high-potential signal;
in the pull-down stage, the pull-down module is required to output a low potential signal, so that the output end Gn of the shift register connected with the pull-down module outputs the low potential signal; moreover, in the shift register provided in the embodiment of the present application, the shift register includes N pull-down modules (i.e., the first pull-down module 31 to the nth pull-down module 3N), where N is an integer of at least 2, and any pull-down module can independently control the output terminal Gn of the shift register to output a low potential signal, so that in the pull-down stage, an arbitrary frequency can be set for the operating condition of each pull-down module, i.e., the first preset frequency to the nth preset frequency can be arbitrarily set, so that through a plurality of different or the same preset frequencies, all pull-down modules are controlled to simultaneously operate, all pull-down modules are controlled to operate cyclically one by one, or any combination of pull-down modules are controlled to operate alternately, and the output terminal of the shift register is controlled to output a low potential signal. For example, if the shift register includes two pull-down modules, namely a first pull-down module and a second pull-down module, each pull-down module can independently enable the output end of the shift register to output a low potential signal according to respective signal control, and the two pull-down modules can alternatively operate by setting the output frequency of the signal end connected with the pull-down modules, that is, in the pull-down stage, when the first pull-down module operates, the second pull-down module does not operate, after a preset time, the second pull-down module operates, the first pull-down module does not operate, and then the operating frequency is cycled; or when the first pull-down module works, the second pull-down module works at the same time; or, the first pull-down module and the second pull-down module operate according to any frequency, as long as it is ensured that the output end of the shift register outputs a low-potential signal in the pull-down stage. The embodiments of the present application are not limited to the above embodiments, and need to be specifically designed according to practical applications.
As can be seen from the above, the shift register provided in the embodiment of the present application includes a plurality of pull-down modules, and each pull-down module can independently control the output terminal of the shift register to output a low potential signal through the control of the signal output by the signal terminal, so that, through the design of the plurality of pull-down modules, when any pull-down module is damaged, the control timing sequence is changed to continue to operate the rest intact pull-down modules, so as to improve the service life of the shift register; in addition, the first pull-down module to the Nth pull-down module can work alternately by setting a special frequency for each signal, and the purpose of reducing power consumption is achieved by outputting a low-frequency signal at each signal end.
More preferably, the first signal terminal to the nth signal terminal respectively provide the first signal to the nth signal according to the first preset frequency to the nth preset frequency respectively corresponding to the first signal to the nth signal terminal, so that the output terminal of the shift register outputs a signal of the output terminal of at least one pull-down module in the pull-down stage, that is, the first pull-down module to the nth pull-down module can alternately operate through setting of the frequencies, the pull-down module which alternately operates can reduce the loss rate of the pull-down module, and the service life of the shift register is further prolonged. Wherein the first preset frequency to the Nth preset frequency are the same; or at least one of the first preset frequency to the nth preset frequency is different, that is, the embodiment of the present application is not limited to the operating frequency of the pull-down module, and it is only required to ensure that the output end of the shift register outputs a signal of the output end of at least one pull-down module in the pull-down stage. Furthermore, at the same time, at least any two signals of the first to nth signals are provided to the corresponding signal terminals, that is, the first to nth signals provided in the embodiment of the present application can control any two pull-down modules to operate at the initial time of the pull-down stage.
It should be noted that, in the embodiment of the present application, the first preset frequency to the nth preset frequency are not specifically limited, and need to be specifically designed according to practical applications. In addition, in the shift register provided by the application, the circuit structures of the first pull-down module to the Nth pull-down module can be all the same; or the circuit structures of the first pull-down module to the Nth pull-down module are all different; or, the circuit structures of the first pull-down module to the nth pull-down module are partially the same, which is not limited in this application.
The following describes a specific circuit structure and a driving timing sequence of each module provided in an embodiment of the present application, referring to fig. 2, a schematic structural diagram of another shift register provided in an embodiment of the present application, and referring to fig. 3, a schematic timing signal diagram corresponding to the shift register in fig. 2, it should be noted that, for convenience of detailed description of the shift register provided in this embodiment, the transistors in each module provided in the embodiment of the present application are all N-type transistors, that is, transistors turned on by high potential control, but other embodiments of the present application do not specifically limit the types of the transistors, as long as the corresponding functions can be completed in the driving process of the shift register.
In addition, the circuit structures of the first pull-down module to the Nth pull-down module provided by the embodiment of the application are the same, so that the high efficiency of manufacturing the shift register is ensured, the low cost of manufacturing the shift register is ensured, and the high stability of the shift register is also ensured. Specifically, the shift register includes: the precharge module 1, the pull-up module 2, the output terminal Gn of the shift register, and the first to nth pull-down modules (in fig. 2, the first pull-down module 31 and the second pull-down module 32 are taken as an example for explanation, and the circuit structures of the first pull-down module 31 and the second pull-down module 32 are the same), N is an integer of at least 2;
wherein, the ith pull-down module (refer to the first pull-down module 31 or the second pull-down module 32 in fig. 2) includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5; wherein,
the gate of the first transistor M1, the first electrode of the first transistor M1 and the first electrode of the second transistor M2 are all connected to the i-th signal terminal (refer to the first signal terminal LC1 or the second signal terminal LC2 in fig. 2), and the second electrode of the first transistor M1, the gate of the second transistor M2 and the first electrode of the third transistor M3 are electrically connected to each other;
the second electrode of the second transistor M2, the first electrode of the fourth transistor M4, and the gate of the fifth transistor M5 are electrically connected to each other;
a gate of the third transistor M3 and a gate of the fourth transistor M4 are electrically connected to the pull-up node PU, a second electrode of the third transistor M3, a second electrode of the fourth transistor M4 and a second electrode of the fifth transistor M5 are electrically connected to the third voltage terminal Vss, and a first electrode of the fifth transistor M5 is electrically connected to the output terminal Gn of the shift register, wherein 1< ═ i < ═ N.
The gate of the third transistor M3 and the gate of the fourth transistor M4 can be both directly electrically connected to the pull-up node PU; in addition, the gate of the third transistor M3 and the gate of the fourth transistor M4 may be electrically connected to another circuit, and the circuit can provide a pull-up signal having the same potential as the pull-up node PU, that is, the pull-up signal varies with the change of the potential of the pull-up node PU, and the pull-up signal and the potential of the pull-up node PU vary the same.
In addition, the precharge module 1 provided in the embodiment of the present application may be selected as a bidirectional precharge module 1, where the bidirectional precharge module 1 includes: an eighth transistor M8 and a ninth transistor M9; wherein,
a gate electrode of the eighth transistor M8 is electrically connected to the first driving signal terminal Gn-1, a first electrode of the eighth transistor M8 is electrically connected to the first voltage terminal DR1, and a second electrode of the eighth transistor is electrically connected to the pull-up node PU;
a gate of the ninth transistor M9 is electrically connected to the second driving signal terminal Gn +1, a first electrode of the ninth transistor M9 is electrically connected to the pull-up node PU, and a second electrode of the ninth transistor M9 is electrically connected to the second voltage terminal DR 2.
Finally, the upward-pulling module 2 provided by the embodiment of the present application includes: a capacitor C and a tenth transistor M10; wherein,
the first plate of the capacitor C and the gate of the tenth transistor M10 are electrically connected to the pull-up node PU, the second plate of the capacitor C and the second electrode of the tenth transistor M10 are electrically connected to the output terminal Gn of the shift register, and the first electrode of the tenth transistor M10 is electrically connected to the clock signal terminal CLK.
The specific driving method of the shift register according to the above-mentioned embodiment of the present application is described in detail with reference to the timing sequence of the previous frame shown in fig. 3, wherein the driving method includes a pre-charge phase T1, a pull-up phase T2, and a pull-down phase T3, and specifically,
first, the shift register enters a precharge phase:
in the pre-charging stage T1, the first driving signal terminal Gn-1 outputs a high-potential signal to control the eighth transistor M8 to be turned on, and then the high-potential signal output from the first voltage terminal DR1 is transmitted to the pull-up node PU through the eighth transistor M8, so that the potential of the pull-up node PU is high, and further the tenth transistor M10 is turned on and charges the capacitor C at the same time; in the precharge stage T1, the clock signal terminal CLK outputs a low-potential signal, and controls the output terminal Gn of the shift register to output a low-potential signal through the tenth transistor M10; the signal terminal Gn +1 outputs a low-level signal to turn off the ninth transistor M9.
For the shift register of this stage, the first driving signal Gn-1 is the output signal of the shift register of the previous stage, and the second driving signal Gn +1 is the output signal of the shift register of the next stage.
Then, the shift register enters a pull-up stage:
in the pull-up stage T2, the first driving signal terminal Gn-1 and the second driving signal terminal Gn +1 both output low-level signals to respectively drive the eighth transistor M8 and the ninth transistor M9 to be turned off, at this time, the clock signal terminal CLK outputs a high-level signal, and then the high-level signal is bootstrapped to the pull-up node PU by the capacitor C, so that the potential of the pull-up node PU is higher than the potential in the pre-charge stage T1 to drive the tenth transistor M10 to be turned on, and at the same time, the clock signal terminal CLK outputs a high-level signal which is transmitted to the output terminal Gn of the shift register by the tenth transistor M10, so that the output signal of the output terminal Gn of the shift register is the high-level signal output by the clock signal terminal CLK;
in addition, during the pull-up period T2, the fifth transistor M5 needs to be controlled to be turned off, so as to avoid the influence on the output signal of the output terminal Gn of the shift register caused by the low-potential signal provided by the third voltage terminal Vss being transmitted to the output terminal Gn of the shift register through the fifth transistor M5, and therefore, the gate potential of the fifth transistor M5 needs to be controlled to be low. And the gate potential of the fifth transistor M5 is controlled by the second transistor M2 or the fourth transistor M4, wherein, since the potential of the pull-up node PU is higher than the potential in the pre-charge phase T1 during the pull-up phase T2, and the third transistor M3 and the fourth transistor M4 whose gates are connected to the pull-up node PU are driven to be turned on, the fourth transistor M4 transmits the low potential signal outputted from the third voltage terminal Vss to the gate of the fifth transistor M5, as can be seen from fig. 2, when the aspect ratio of the third transistor M3 is less than or equal to the aspect ratio of the first transistor M1, it is necessary to control the first signal terminal LC1 and the second signal terminal LC2 to output low potential signals during the pull-up phase T2, at this time, only the third transistor M3 and the fourth transistor M4 are turned on, and the third transistor M3 transmits the low potential signal from the third voltage terminal Vss to the gate of the second transistor M2 to be turned off 2, and the low potential signal of the third voltage terminal Vss is transmitted to the gate of the fifth transistor M5 by the fourth transistor M4, and the fifth transistor M5 is controlled to be turned off; alternatively, when the width-to-length ratio of the third transistor M3 is greater than the width-to-length ratio of the first transistor M1, there is no limitation on controlling the potentials of the output signals of the first signal terminal LC1 and the second signal terminal LC2 in the pull-up phase T2, that is, there is no influence on the gate potential of the second transistor M2 regardless of whether the first transistor M1 is turned on, the gate potential of the second transistor M2 is controlled by the third transistor M3, that is, in the pull-up phase T2, the third transistor M3 transmits the low potential signal of the third voltage terminal Vss to the gate of the second transistor M2, the second transistor M2 is controlled to be turned off, and the fourth transistor M4 transmits the low potential signal of the third voltage terminal Vss to the gate of the fifth transistor M5, and the fifth transistor M5 is controlled to be turned off.
In this embodiment, preferably, the width-to-length ratio of the third transistor is greater than that of the first transistor, so that on the basis of ensuring that the output end of the shift register in the pull-down stage outputs the low-potential signal, the frequency of the ith signal end can be set arbitrarily, and the frequency of the ith signal end can be reduced to the lowest level, so as to reduce the power consumption of the shift register.
Finally, the shift register enters a pull-down stage:
in the pull-down period T3, the first driving signal terminal Gn-1 outputs a low-level signal to control the eighth transistor M8 to turn off; the second driving signal terminal Gn +1 outputs a high signal to control the ninth transistor M9 to be turned on, the second voltage terminal DR2 outputs a low signal to control the pull-up node PU to be at a low voltage, and the clock signal CLK outputs a low signal.
During the pull-down period T3, the output terminal Gn of the shift register needs to output a low-potential signal, i.e., the fifth transistor M5 needs to be controlled to be turned on, and the fifth transistor M5 transmits the low-potential signal output from the third voltage terminal Vss to the output terminal Gn of the shift register. Since the pull-up node PU is at a low potential, the third transistor M3 and the fourth transistor M4 are driven to be turned off, and therefore the gate potential of the fifth transistor M5 is controlled by the second transistor M2. At this time, high-potential signals are output to the first signal terminal LC1 and the second signal terminal LC2 according to the corresponding first preset frequency and second preset frequency, so as to respectively control the conduction of the respective first transistor M1, then the high-potential signal is transmitted to the gate of the second transistor M2 through the first transistor M1 to drive the conduction of the second transistor M2, and the high-potential signal is transmitted to the gate of the fifth transistor M5 through the second transistor M2 to drive the conduction of the fifth transistor M5, finally, the fifth transistor M5 transmits the low-potential signal of the third voltage terminal Vss to the output terminal Gn of the shift register, so that the output terminal Gn of the shift register outputs a low-potential signal.
As can be seen from the working process of the pull-down stage T3, the ith pull-down module provided in this embodiment is controlled by the high-potential signal output by the ith signal terminal connected to the ith signal terminal according to the ith preset frequency, so as to control the fifth transistor to transmit the low-potential signal to the output terminal of the shift register, so that the output terminal of the shift register outputs the low-potential signal, thereby completing the pull-down function of the shift register, and therefore, on the basis of ensuring that the output terminal of the shift register in the pull-down stage outputs the low-potential signal, the frequency of the high-potential signal output by any one signal terminal can be reduced to the minimum, so as to ensure that the shift register has a long service life, and at the same; in addition, compared with some existing shift registers using capacitor pull-down, the pull-down module provided by the embodiment of the application controls the output end of the shift register to output a low-potential signal through the cooperation of a plurality of transistors, so that the pull-down module is ensured to work more stably.
In addition, referring to fig. 3, based on the shift register circuit provided in fig. 2, since the pre-charge module is a bidirectional pre-charge module, after the previous frame is scanned, the next frame can be scanned from another direction, that is,
first, the shift register enters a precharge phase:
in the pre-charging stage T1, the second driving signal terminal Gn +1 outputs a high-potential signal to control the ninth transistor M9 to be turned on, and then the high-potential signal output from the second voltage terminal DR2 is transmitted to the pull-up node PU through the ninth transistor M9, so that the potential of the pull-up node PU is high, the tenth transistor M10 is turned on, and the capacitor C is charged at the same time; in the precharge stage T1, the clock signal terminal CLK outputs a low-potential signal, and controls the output terminal Gn of the shift register to output a low-potential signal through the tenth transistor M10; the signal terminal Gn +1 outputs a low-level signal to turn off the ninth transistor M9.
For the shift register of this stage, the first driving signal Gn-1 is the output signal of the shift register of the previous stage, and the second driving signal Gn +1 is the output signal of the shift register of the next stage.
Then, the shift register enters a pull-up stage:
in the pull-up stage T2, the first driving signal terminal Gn-1 and the second driving signal terminal Gn +1 both output low-level signals to respectively drive the eighth transistor M8 and the ninth transistor M9 to be turned off, at this time, the clock signal terminal CLK outputs a high-level signal, and then the high-level signal is bootstrapped to the pull-up node PU by the capacitor C, so that the potential of the pull-up node PU is higher than the potential in the pre-charge stage T1 to drive the tenth transistor M10 to be turned on, and at the same time, the clock signal terminal CLK outputs a high-level signal which is transmitted to the output terminal Gn of the shift register by the tenth transistor M10, so that the output signal of the output terminal Gn of the shift register is the high-level signal output by the clock signal terminal CLK;
in addition, during the pull-up period T2, the fifth transistor M5 needs to be controlled to be turned off, so as to avoid the influence on the output signal of the output terminal Gn of the shift register caused by the low-potential signal provided by the third voltage terminal Vss being transmitted to the output terminal Gn of the shift register through the fifth transistor M5, and therefore, the gate potential of the fifth transistor M5 needs to be controlled to be low. And the gate potential of the fifth transistor M5 is controlled by the second transistor M2 or the fourth transistor M4, wherein, since the potential of the pull-up node PU is higher than the potential in the pre-charge phase T1 during the pull-up phase T2, and the third transistor M3 and the fourth transistor M4 whose gates are connected to the pull-up node PU are driven to be turned on, the fourth transistor M4 transmits the low potential signal outputted from the third voltage terminal Vss to the gate of the fifth transistor M5, as can be seen from fig. 2, when the aspect ratio of the third transistor M3 is less than or equal to the aspect ratio of the first transistor M1, it is necessary to control the first signal terminal LC1 and the second signal terminal LC2 to output low potential signals during the pull-up phase T2, at this time, only the third transistor M3 and the fourth transistor M4 are turned on, and the third transistor M3 transmits the low potential signal from the third voltage terminal Vss to the gate of the second transistor M2 to be turned off 2, and the low potential signal of the third voltage terminal Vss is transmitted to the gate of the fifth transistor M5 by the fourth transistor M4, and the fifth transistor M5 is controlled to be turned off; alternatively, when the width-to-length ratio of the third transistor M3 is greater than the width-to-length ratio of the first transistor M1, there is no limitation on controlling the potentials of the output signals of the first signal terminal LC1 and the second signal terminal LC2 in the pull-up phase T2, that is, there is no influence on the gate potential of the second transistor M2 regardless of whether the first transistor M1 is turned on, the gate potential of the second transistor M2 is controlled by the third transistor M3, that is, in the pull-up phase T2, the third transistor M3 transmits the low potential signal of the third voltage terminal Vss to the gate of the second transistor M2, the second transistor M2 is controlled to be turned off, and the fourth transistor M4 transmits the low potential signal of the third voltage terminal Vss to the gate of the fifth transistor M5, and the fifth transistor M5 is controlled to be turned off.
In this embodiment, preferably, the width-to-length ratio of the third transistor is greater than that of the first transistor, so that on the basis of ensuring that the output end of the shift register in the pull-down stage outputs the low-potential signal, the frequency of the ith signal end can be set arbitrarily, and the frequency of the ith signal end can be reduced to the lowest level, so as to reduce the power consumption of the shift register.
Finally, the shift register enters a pull-down stage:
in the pull-down period T3, the second driving signal terminal Gn +1 outputs a low-level signal to control the ninth transistor M9 to turn off; the first driving signal terminal Gn-1 outputs a high signal to control the eighth transistor M8 to be turned on, the first voltage terminal DR1 outputs a low signal to control the pull-up node PU to be at a low voltage, and the clock signal CLK outputs a low signal.
During the pull-down period T3, the output terminal Gn of the shift register needs to output a low-potential signal, i.e., the fifth transistor M5 needs to be controlled to be turned on, and the fifth transistor M5 transmits the low-potential signal output from the third voltage terminal Vss to the output terminal Gn of the shift register. Since the pull-up node PU is at a low potential, the third transistor M3 and the fourth transistor M4 are driven to be turned off, and therefore the gate potential of the fifth transistor M5 is controlled by the second transistor M2. At this time, high-potential signals are output to the first signal terminal LC1 and the second signal terminal LC2 according to the corresponding first preset frequency and second preset frequency, so as to respectively control the conduction of the respective first transistor M1, then the high-potential signal is transmitted to the gate of the second transistor M2 through the first transistor M1 to drive the conduction of the second transistor M2, and the high-potential signal is transmitted to the gate of the fifth transistor M5 through the second transistor M2 to drive the conduction of the fifth transistor M5, finally, the fifth transistor M5 transmits the low-potential signal of the third voltage terminal Vss to the output terminal Gn of the shift register, so that the output terminal Gn of the shift register outputs a low-potential signal.
As can be seen from the working process of the pull-down stage T3, the ith pull-down module provided in this embodiment is controlled by the high-potential signal output by the ith signal terminal connected to the ith signal terminal according to the ith preset frequency, so as to control the fifth transistor to transmit the low-potential signal to the output terminal of the shift register, so that the output terminal of the shift register outputs the low-potential signal, thereby completing the pull-down function of the shift register, and therefore, on the basis of ensuring that the output terminal of the shift register in the pull-down stage outputs the low-potential signal, the frequency of the high-potential signal output by any one signal terminal can be reduced to the minimum, so as to ensure that the shift register has a long service life, and at the same; in addition, compared with some existing shift registers using capacitor pull-down, the pull-down module provided by the embodiment of the application controls the output end of the shift register to output a low-potential signal through the cooperation of a plurality of transistors, so that the pull-down module is ensured to work more stably.
In addition, as can be seen from fig. 3, the frequency of the signal provided by the signal terminal of the pull-down module provided in the embodiment of the present application is not particularly limited, and in the process of scanning the previous frame, a signal can be provided by one signal terminal LC1 in the pull-down stage of any one stage of shift register; during the scanning of the next frame, the shift register stage can be provided with a signal from another signal terminal LC2,
Further, based on the shift register shown in fig. 2, an embodiment of the present application further provides a shift register, which is shown in fig. 4, and is a schematic structural diagram of another shift register provided in the embodiment of the present application, where in addition to the structure shown in fig. 2, the shift register further includes: the pull-up node reset module 4 is used for resetting the potential of the pull-up node PU, namely controlling the pull-up node PU to be at a low potential; wherein, pull-up node reset module 4 includes: a sixth transistor M6;
a gate of the sixth transistor M6 is electrically connected to the gate of the fifth transistor M5, a first electrode of the sixth transistor M6 is electrically connected to the third voltage terminal Vss, and a second electrode of the sixth transistor M6 is electrically connected to the pull-up node PU.
In order to ensure that the potential of the pull-up node is changed into a low potential rapidly in the pull-down stage, the potential of the pull-up node can be pulled down through the pull-up node reset module, namely, in the pull-down stage, the fifth transistor is controlled to be switched on by the second transistor, the sixth transistor is also controlled to be switched on, a low potential signal output by the third voltage end is transmitted to the pull-up node through the sixth transistor, the potential of the pull-up node is pulled down rapidly, and the condition that the pull-up node interferes with the work of the pull-down module is avoided.
Further, referring to fig. 4, the shift register further includes: the initialization module 5 is used for enabling the output end Gn of the shift register to be at a low potential before the shift register works; the initialization module 5 includes a seventh transistor M7; wherein,
a gate electrode of the seventh transistor M7 is electrically connected to the third driving signal terminal Reset, a first electrode of the seventh transistor M7 is electrically connected to the fourth voltage terminal Vgl, and a second electrode of the seventh transistor M7 is electrically connected to the output terminal Gn of the shift register.
The fourth voltage end outputs a low potential signal, namely, the display device is ensured to be started to generate an instant screen splash phenomenon, before the gate lines are scanned step by step, namely, before the pre-charging voltage stage of the shift register, the potential of the output end of the shift register is initialized to be a low potential, and the low potential signal output by the fourth voltage end is transmitted to the output end of the shift register through the control of the signal output by the third driving signal end.
Correspondingly, the invention further provides a gate driving circuit, which includes first to mth shift registers arranged along a first direction, where the first to mth shift registers are all the shift registers provided in any of the above embodiments, and M is an integer greater than 1.
Referring to fig. 5, a schematic diagram of a structure of a gate driving circuit provided in an embodiment of the present disclosure is shown, where a shift register of the gate driving circuit provided in the embodiment of the present disclosure is the same as the shift register provided in fig. 2, and includes a first-stage shift register to an M-th-stage shift register arranged along a first direction Y, where an output end of a previous-stage shift register along the first direction is electrically connected to a first driving signal end of a next-stage shift register, and a second driving signal end of the previous-stage shift register along the first direction is electrically connected to an output end of the next-stage shift register;
in addition, the even-numbered stage shift registers arranged along the first direction are connected to the first clock signal CLK1, the odd-numbered stage shift registers arranged along the first direction are connected to the second clock signal CLK2, and the first clock signal CLK1 and the second clock signal CLK2 are opposite signals to each other.
In the process of scanning a frame of picture by using the gate driving circuit, in the pull-down stage of each stage of the shift register, the stage of the shift register can be controlled to output a signal of the output end of at least one pull-down module by connecting signals provided by the first signal end to the Nth signal end of the shift register.
Specifically, referring to fig. 5, each stage of the shift register includes two pull-down modules respectively connected to the first signal LC1 and the second signal LC 2. In the process of scanning a frame of picture, in the pull-down stage of each stage of shift register, the frequencies of signals provided by the first signal LC1 and the second signal LC2 for the respective pull-down modules are the same, that is, after each stage of shift register enters the pull-down stage, the first signal LC1 and the second signal LC2 both provide signals for the respective pull-down modules, so that the stage of shift register outputs the output end signals of the two pull-down modules; or, in the process of scanning a frame of picture, in the pull-down stage of each stage of shift register, the frequencies of the signals provided by the first signal LC1 and the second signal LC2 for the respective pull-down modules are different, so that the stage of shift register outputs the signal of the output end of the same pull-down module, or the stage of shift register alternately outputs the signals of the output ends of two pull-down modules according to the preset frequency; alternatively, in the process of scanning a frame, the frequencies of the first signal LC1 and the second signal LC2 in the pull-down phase of the shift registers of different stages are different, and the embodiment of the present application is not limited in particular.
Correspondingly, the invention further provides a display device, which comprises an array substrate, wherein the array substrate comprises a pixel unit array and a gate driving circuit for driving the pixel unit array, and the gate driving circuit is the gate driving circuit provided by the embodiment.
The embodiment of the application provides a shift register, a gate drive circuit and a display device, wherein the shift register comprises:
the device comprises a pre-charging module, a pull-up module, a first pull-down module and an Nth pull-down module, wherein N is an integer of at least 2; the output end of the pre-charge module and the input end of the pull-up module are electrically connected to a pull-up node, and the output end of the pull-up module is electrically connected to the output end of the shift register; the output ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the shift register, the control ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the pre-charge module, and the input ends of the first pull-down module to the Nth pull-down module are electrically connected to the corresponding first signal end to the corresponding Nth signal end respectively, so that the output end of the shift register outputs at least one signal of the output end of the pull-down module in a pull-down stage through control of the first signal to the Nth signal provided by the first signal end to the Nth signal end respectively.
As can be seen from the above, in the technical solution provided by the present invention, the first to nth pull-down modules are respectively controlled to operate by the first to nth signals, that is, in the pull-down stage, the first to nth pull-down modules can be independently controlled to enable the output end of the shift register to output a low potential signal, so that when any one pull-down module is damaged, the shift register can be increased in service life by outputting signals to the remaining pull-down modules. In addition, the technical scheme provided by the invention can also set a special frequency for each signal to enable the first pull-down module to the Nth pull-down module to work alternately, and the purpose of reducing power consumption is achieved by outputting a low-frequency signal at each signal end, and the pull-down modules working alternately can reduce the loss rate of the pull-down modules and further prolong the service life of the shift register.
Claims (11)
1. A shift register, comprising: the device comprises a pre-charging module, a pull-up module, a first pull-down module and an Nth pull-down module, wherein N is an integer of at least 2;
the output end of the pre-charge module and the input end of the pull-up module are electrically connected to a pull-up node, and the output end of the pull-up module is electrically connected to the output end of the shift register;
the output ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the shift register, the control ends of the first pull-down module to the Nth pull-down module are electrically connected to the output end of the pre-charge module, and the input ends of the first pull-down module to the Nth pull-down module are electrically connected to the corresponding first signal end to the corresponding Nth signal end respectively, so that the output end of the shift register outputs at least one signal of the output end of the pull-down module in a pull-down stage through control of the first signal to the Nth signal provided by the first signal end to the Nth signal end respectively.
2. The shift register according to claim 1, wherein the first to nth signal terminals provide the first to nth signals at respective corresponding first to nth predetermined frequencies, wherein the first to nth predetermined frequencies are the same; or,
at least one of the first preset frequency to the Nth preset frequency is different.
3. The shift register according to claim 2, wherein at least any two of the first to nth signals are supplied to the corresponding signal terminals at the same time.
4. The shift register of claim 1, wherein the first to nth pull-down modules have the same circuit structure, and the ith pull-down module comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; wherein,
a gate electrode of the first transistor, a first electrode of the first transistor, and a first electrode of the second transistor are electrically connected to the i-th signal terminal, and a second electrode of the first transistor, a gate electrode of the second transistor, and a first electrode of the third transistor are electrically connected to each other;
a second electrode of the second transistor, a first electrode of the fourth transistor, and a gate electrode of the fifth transistor are electrically connected to each other;
a gate electrode of the third transistor and a gate electrode of the fourth transistor are electrically connected to the pull-up node, a second electrode of the third transistor, a second electrode of the fourth transistor, and a second electrode of the fifth transistor are electrically connected to a third voltage terminal, and a first electrode of the fifth transistor is electrically connected to an output terminal of the shift register, wherein 1< ═ i < ═ N.
5. The shift register according to claim 4, wherein a width-to-length ratio of the third transistor is larger than a width-to-length ratio of the first transistor.
6. The shift register of claim 4, further comprising: the pull-up node reset module is used for resetting the potential of the pull-up node; wherein, pull-up node reset module includes: a sixth transistor;
a gate of the sixth transistor is electrically connected to the gate of the fifth transistor, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node.
7. The shift register of claim 1, wherein the precharge module is a bi-directional precharge module, the bi-directional precharge module comprising: an eighth transistor and a ninth transistor; wherein,
a gate electrode of the eighth transistor is electrically connected to a first driving signal terminal, a first electrode of the eighth transistor is electrically connected to a first voltage terminal, and a second electrode of the eighth transistor is electrically connected to the pull-up node;
a gate of the ninth transistor is electrically connected to a second driving signal terminal, a first electrode of the ninth transistor is electrically connected to the pull-up node, and a second electrode of the ninth transistor is electrically connected to a second voltage terminal.
8. The shift register of claim 1, wherein the pull-up module comprises: a capacitor and a tenth transistor; wherein,
the first plate of the capacitor and the gate of the tenth transistor are both electrically connected to the pull-up node, the second plate of the capacitor and the second electrode of the tenth transistor are both electrically connected to the output end of the shift register, and the first electrode of the tenth transistor is electrically connected to a clock signal end.
9. The shift register of claim 1, further comprising: an initialization module comprising a seventh transistor; wherein,
a gate of the seventh transistor is electrically connected to a third driving signal terminal, a first electrode of the seventh transistor is electrically connected to a fourth voltage terminal, and a second electrode of the seventh transistor is electrically connected to an output terminal of the shift register.
10. A gate driving circuit, comprising first to M-th shift registers arranged along a first direction, the first to M-th shift registers being the shift register according to any one of claims 1 to 9, M being an integer greater than 1.
11. A display device, comprising an array substrate, wherein the array substrate comprises a pixel unit array, and a gate driving circuit for driving the pixel unit array, wherein the gate driving circuit is the gate driving circuit according to claim 10.
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| CN201410710826.7A CN104361852A (en) | 2014-11-28 | 2014-11-28 | Shifting register, gate drive circuit and display device |
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