CN105938849A - Manufacturing method for Schottky chip used for chip scale packaging - Google Patents
Manufacturing method for Schottky chip used for chip scale packaging Download PDFInfo
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- CN105938849A CN105938849A CN201610075437.0A CN201610075437A CN105938849A CN 105938849 A CN105938849 A CN 105938849A CN 201610075437 A CN201610075437 A CN 201610075437A CN 105938849 A CN105938849 A CN 105938849A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 111
- 229910052751 metal Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 108
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 97
- 239000010703 silicon Substances 0.000 claims abstract description 97
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 88
- 230000004888 barrier function Effects 0.000 claims abstract description 78
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 54
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000003647 oxidation Effects 0.000 claims abstract description 22
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 238000011049 filling Methods 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 6
- 238000000407 epitaxy Methods 0.000 claims description 49
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 238000007789 sealing Methods 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 14
- 239000007792 gaseous phase Substances 0.000 claims description 13
- 238000005260 corrosion Methods 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 9
- 230000000737 periodic effect Effects 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 4
- 230000012010 growth Effects 0.000 claims description 4
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 7
- 239000007924 injection Substances 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000000945 filler Substances 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000002277 temperature effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 143
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
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- 239000011574 phosphorus Substances 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 230000002441 reversible effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 206010037660 Pyrexia Diseases 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical class O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229910021484 silicon-nickel alloy Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- XRZCZVQJHOCRCR-UHFFFAOYSA-N [Si].[Pt] Chemical compound [Si].[Pt] XRZCZVQJHOCRCR-UHFFFAOYSA-N 0.000 description 1
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- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
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- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method for a Schottky chip used for chip scale packaging. The manufacturing method for the Schottky chip comprises the following steps: preparing a silicon substrate and forming a silicon epitaxial layer; depositing a silicon dioxide layer on the surface of the silicon epitaxial layer through thermal oxidation or/and chemical vapor deposition; forming grooves running through the silicon epitaxial layer; filling conductive polycrystalline silicon as a groove filler in the grooves; forming a protection ring of a Schottky electrode through an ion injection method; depositing a silicon dioxide layer through a chemical vapor deposition method, and carrying out thermal diffusion for injected ions by using a high temperature effect during oxidizing at the same time; and forming a barrier metal and a top metal. According to the Schottky chip manufactured by the manufacturing method, the two electrodes are arranged on the same main surface of the silicon epitaxial layer, so that the requirement of the chip scale packaging that a packaging device is of dimensions approximate to those of a semiconductor element is reached.
Description
Technical field
The present invention relates to semiconductor device, particularly for schottky device chip and the manufacturer of wafer-level package
Method.
Background technology
Due to energy-conservation, the needs of lightness small-sized with equipment, the application of high frequency switch power is the most universal.With junction type two
Pole pipe is compared, and Schottky diode has that forward voltage is lower and the higher advantage of operating frequency, and therefore, Schottky diode exists
Being widely used in high frequency switch power, it is mainly used in PC power, solar energy, LED streetlamp power source, industrial power, fits
Orchestrations etc., the application of current Schottky diode accounts for position leading in the application of all commutation diodes, and its utility ratio has continuation
The trend raised.
Along with customer demand integrated more multi-functional and requirement to electronic component smallerization in small portable device
Increase, exploitation new device use joint space-efficient wafer-level package (Chip Scale Package: CSP), be applied to sky
Between limited hand-held and portable equipment, such as panel computer, smart phone, PDA and miniature hard disk drive, range of application includes electricity
Stream regulation, boosting and freewheeling circuit etc..Wide variety of Schottky diode in electronic circuit, wishes have and can answer naturally
For the Schottky chip of wafer-level package to realize the miniaturization of electronic circuit.
Wafer-level package require chip area and package area close to the ideal situation of 1:1, thus than traditional quasiconductor
Encapsulation takies the area on less circuit board.Use the Schottky chip of conventional package technique, the electrode of tube core is arranged on
On positive and negative two surfaces, wafer-level package device approximates the size of semiconductor element in order to ensure having, by the electrode of tube core only
Arrange on a surface, as patent of invention that notification number is CN 100380679C proposes the Xiao Te of a kind of wafer-level package
Base device structure, it is simply that negative electrode and anode are simultaneously located at the example on same surface.But, in this patent of invention, negative electrode is to pass through
Injecting and follow-up diffusion-driven forms a sinker area and electrically connects to be formed in epitaxial region, the negative electrode of this structure has high
Conducting resistance, simultaneously its sinker area also can take bigger chip area, and the negative electrode conducting resistance how reducing device is current
It is applied to the main bugbear of the chip development of wafer-level package.
Summary of the invention
For the technical problem of the Schottky chip being currently used for wafer-level package, it is desirable to provide a kind of negative electrode tool
There is less conducting resistance and take the manufacture method of Schottky chip of less chip area.
The invention provides the manufacture method of a kind of Schottky chip for wafer-level package, a kind of for chip-scale envelope
The manufacture method of the Schottky chip of dress, comprises the following steps:
(1) silicon substrate preparation process；Described silicon substrate has the first conduction type；
(2) silicon epitaxy layer forming step；Described silicon epitaxy layer has the first conduction type；
(3) insulating barrier part forming step: by thermal oxide or/and chemical gaseous phase is deposited on silicon epitaxy layer surface deposition dioxy
SiClx layer；
(4) groove forming step: by being dry-etched between the front surface of silicon substrate and the front surface of silicon epitaxy layer formation Europe
Some grooves of nurse electrode, groove through-silicon epitaxial layer；
(5) polysilicon step is filled: in described groove, fill conductive polycrystalline silicon as trench filling；Described conductive polycrystalline
Silicon has the first conduction type；
(6) around Schottky electrode, ion implantation forms the protection ring of Schottky electrode；Inject the Schottky electricity formed
Pole protection ring has the second conduction type, contrary with the first conduction type；
(7) insulating barrier another part is formed and ion diffusing step: made by chemical vapor deposition layer of silicon dioxide
For insulating barrier another part that is three time oxide layer, while three oxide layer growths, high temperature action when utilizing oxidation, carry out
The thermal diffusion injecting ion that step (six) completes；
(8) barrier metal and top-level metallic forming step: in this step, completes the formation of barrier metal, thus is formed at anode
Barrier metal and the Schottky contacts of silicon epitaxy layer；In this step, also complete top-level metallic anode metal and negative electrode couples metal
Formation, form Schottky electrode and Ohmic electrode respectively.
Further, in described (four) groove forming step, the number of the groove of formation and Schottky electrode number are one
Arrange one；Negative electrode described in step (eight) couple metal be formed as on trench filling formed cathodic metal.
Further, in described (four) groove forming step, the groove of multiple periodic arrangement is formed；Described in step (eight)
Negative electrode couples metal and forms the formation barrier metal on the gap epitaxial layer between the groove being included in periodic arrangement and whole
The formation cathodic metal of individual Ohmic electrode top layer, this barrier metal and cover cathodic metal thereon and trench gap extension
Layer is formed and electrically connects.Further, in described (four) groove forming step, the A/F of each groove of periodic arrangement is 0.6
～1.2 μm, the gap epitaxial layer width between two grooves is 0.5～2 μm.
The manufacture method of the Schottky chip that the present invention provides, further comprises sealing coat forming step: in this step
In, between conductive polycrystalline silicon and groove lateral margin, make sealing coat；Its step is deposited on total for first passing through chemical gaseous phase
Surface deposition layer of silicon dioxide layer；Then optionally removed the silicon dioxide layer of channel bottom by photoetching corrosion, expose
Go out the front surface of the silicon epitaxy layer of channel bottom, and be retained in the silicon dioxide layer that groove lateral margin is formed, the two of this groove lateral margin
Silicon oxide layer constitutes described sealing coat.
Further, described by chemical gaseous phase be deposited on total surface deposition layer of silicon dioxide layer be: pass through
Thermal oxidation method forms the silicon dioxide layer of 400～600A thickness.Preferred as another, described be deposited on by chemical gaseous phase whole
Body structure surface deposition layer of silicon dioxide layer is: formed the silicon dioxide layer of 1000～3000A thickness by wet oxidation method.
Further, described (eight) barrier metal and top-level metallic forming step be: first carries out the photoetching corrosion of insulating barrier,
Selective removal, as the silicon dioxide layer of insulating barrier, opens negative electrode and anode openings, before anode exposes silicon epitaxy layer
Surface, negative electrode exposes the front surface of the gap epitaxial layer between upper surface and the groove of conductive polycrystalline silicon；Then potential barrier is carried out
Metal deposit；Carry out negative electrode and anode metal forming step again；Finally carry out metal lithographic corrosion, expose insulating barrier to open
Opening, cut off electrically connecting between anode metal and cathodic metal.
Further, in described (eight) barrier metal and top-level metallic forming step, after carrying out barrier metal deposition,
Once make annealing treatment, make barrier metal form metal alloy with the front surface silicon of silicon epitaxy layer.
Further, the square resistance of the conductive polycrystalline silicon filled in described groove is 14～20 Ω/sq.
Further, described (three) insulating barrier part forming step is: first passes through thermal oxide and forms one in epi-layer surface
Layer silicon dioxide layer i.e. once oxidation layer, then continue to deposit the second layer on first time silicon dioxide layer by chemical gaseous phase deposition
Silicon dioxide layer i.e. secondary oxidation layer.
Beneficial effects of the present invention:
1) Schottky chip manufactured by the present invention, two electrode Schottky electrode (anode) and Ohmic electrode are (cloudy
Pole) it is arranged on the same first type surface of silicon epitaxy layer, reach wafer-level package and required that packaging has approximation transistor
The size requirements of core.
2) if groove-shaped sinker area and negative electrode by the highly doped conductive polycrystalline silicon of dry-packing couple metal and constitute ohm electricity
Pole.Heavy doping conductive polycrystalline silicon has good conduction property, it is possible to effectively reduces the conducting resistance of chip and can enter
One step reduces the thickness of cathodic metal, thus improves its reverse-conducting characteristic, and further reduces what Ohmic electrode took
Chip area, the more efficient miniaturization realizing electronic circuit.
3) this manufacture method, uses insulant to isolate, effectively conductive polycrystalline silicon and groove lateral margin the most further
Isolate Schottky electrode and the Ohmic electrode of chip, decreased highly doped conductive polycrystalline silicon simultaneously and mix in subsequent high temperature processes
The diffusion of heteroion, reduce further the reverse leakage current of this Schottky chip so that it is reverse blocking capability is strong, reliability
Good.
Accompanying drawing explanation
Fig. 1 is the structural representation of the Schottky chip using traditional packaged type.
Fig. 2 be notification number be the Schottky chip structure chart in the patent of invention of CN 100380679C.
The cross sectional representation of the Schottky chip 11 in Fig. 3 first embodiment of the invention.
The cross sectional representation of the Schottky chip 12 in Fig. 4 first embodiment of the invention.
Fig. 5 is the flow chart of the manufacture method of Schottky chip 11 in first embodiment of the invention.
Fig. 6 is the cross sectional representation of Schottky chip 20 in second embodiment of the invention.
The flow chart of the manufacture method of Schottky chip 20 in Fig. 7 second embodiment of the invention.
In each figure: silicon substrate 2, the front surface 2a of silicon substrate, the back surface 2b of silicon substrate, silicon epitaxy layer 3, silicon epitaxy layer
Front surface 3a, Schottky electrode 4, protection ring 41, Schottky barrier metal 42, anode metal 43, Ohmic electrode 6, trench fill
Thing 61, sealing coat 62, cathodic metal 63, injection sinker area 64, insulating barrier 7, once oxidation layer 71, secondary oxidation layer 72, three times
Oxide layer 73.
Detailed description of the invention
Hereinafter based on accompanying drawing, embodiment of the present invention will be described.In following figure, identical or corresponding parts are used
Identical reference represents, and the description that they will not be repeated.
Existing market mainly uses the Schottky chip using traditional packaged type, its structure such as Fig. 1, the two of this chip
Individual electrode i.e. Schottky electrode 4(anode) and Ohmic electrode 6(negative electrode) the front surface 3a of the silicon epitaxy layer 3 that is placed in and silicon substrate
The back surface 2b of 2 so that it is the volume of packaging and package thickness are all difficult to meet further the space of small portable device and are subject to
Limit demand.
Notification number be the Schottky chip structure of the wafer-level package provided in the patent of invention of CN 100380679C such as
Fig. 2, its negative electrode (Ohmic electrode 6) is because being to form a sinker area with shape by injection and follow-up diffusion-driven in epitaxial region
One-tenth electrically connects with silicon epitaxy layer, and owing to being limited by injection technology and follow-up diffusion, the negative electrode of this structure is in diffusion
During formed as Fig. 2 injects the structure wide at the top and narrow at the bottom shown in sinker area 64, and doping content is from the upper surface of injection region
Form gradient from high to low along diffusion path to its lower surface, the Ohmic electrode being consequently formed have high conducting resistance,
It is difficult to reach with the conduction property of Fig. 1 traditional structure simultaneously as its injection sinker area needs bigger at silicon epitaxy layer front surface
Area so the Ohmic electrode of device can take bigger chip area.
(first embodiment)
Comparing both above Schottky chip, Fig. 3 is to schematically show the Schottky chip 11 in first embodiment of the invention
Cross-sectional view.As it is shown on figure 3, Schottky chip 11 includes having the highly doped silicon substrate 2 of the first conduction type, be formed at
Low-doped silicon epitaxy layer 3, this silicon epitaxy layer 3 on the front surface 2a of highly doped silicon substrate 2 also have the first conductive-type
Type, the Schottky electrode 4 being formed on this silicon epitaxy layer 3, Ohmic electrode 6, be formed on silicon epitaxy layer 3 for isolating Xiao
The protection ring 41 that special base electrode 4 and the insulating barrier 7 of Ohmic electrode 6, periphery around Schottky electrode 4 are arranged, this protection ring 41
Have and the second conduction type of the first conduction type opposite conductivities；Wherein said Schottky electrode 4 includes being formed at outside silicon
Prolong the Schottky barrier metal 42 on layer 3 and cover the anode metal 43 on barrier metal 42；The composition bag of Ohmic electrode 6
Include: for some through-silicon epitaxial layers 3 groove and be formed at Ohmic electrode top layer negative electrode couple metal, and groove in fill
There is the trench filling 61 with the first conduction type, this trench filling 61 and described silicon substrate 2 front surface 2a and negative electrode
Couple metal formation to electrically connect.The most described preferred heavy doping conductive polycrystalline silicon of trench filling 61, preferably first leads
Electricity type is the N-type of the adulterant such as Doping Phosphorus or arsenic, and therefore the second conduction type of protection ring 41 is preferably the doping such as doped with boron
The p-type of agent；As preferably, the Schottky barrier metal 42 of the present invention selects the relatively low schottky barrier metal layer of potential barrier such as
Ni, Ti, Cr etc., to reduce device forward cut-in voltage, can also reduce the thickness of anode metal layer simultaneously, so can be substantially improved
Device forward conduction characteristic, and noble metal such as Pt equal proportion contained by the metal that generally potential barrier is relatively low is low or does not contains noble metal,
Therefore schottky barrier metal layer low cost, it is possible to decrease the cost of whole device；As preferably, the present invention uses silicon dioxide to make
For isolation Schottky electrode 4 and the insulating barrier 7 of Ohmic electrode 6.Preferred as one, the groove of Ohmic electrode and Schottky electrode
Number is arranged one to one, and it is to be formed at the cathodic metal 63 on trench filling that negative electrode couples metal, and trench filling is heavily doped
The square resistance of miscellaneous conductive polycrystalline silicon is 14～20 Ω/sq.
Preferred as another, another arrangement of the Ohmic electrode as shown in Schottky chip 12 in Fig. 4, Ohmic electrode is
The trench cycle arrangement of some through-silicon epitaxial layers 3 forms, and the width h1 of the groove of periodic arrangement is 0.6～1.2 μm, two grooves
Between gap epitaxial layer width h2 be 0.5～2 μm, certainly, Fig. 4 simply illustrates groove and the cycle of gap epitaxial layer thereof
Pattern of rows and columns, is not offered as the groove number being limited to shown in figure, and concrete groove number is according to the width h1 of groove, gap width
H2 and groove overall width determine；Thus, the negative electrode of the Ohmic contact forming Ohmic electrode 6 couples metal for being formed at outside gap
Prolong the barrier metal 42 on layer and be formed at the cathodic metal 63 of whole Ohmic electrode top layer, this barrier metal and cover it
On cathodic metal 63 and trench gap epitaxial layer formed electrically connect.
The Schottky chip of the present invention, both by by the two of Schottky chip electrode Schottky electrodes (anode) and ohm
Electrode (negative electrode) is arranged on the same first type surface of silicon epitaxy layer, has reached wafer-level package and has required that packaging has approximation half
The size requirements of conductor tube core, also improves the design of Ohmic electrode, if by the groove of the highly doped conductive polycrystalline silicon of dry-packing
Type sinker area and anode metal constitute Ohmic electrode.Heavy doping conductive polycrystalline silicon has good conduction property, it is possible to effective
Reduce the conducting resistance of chip and the thickness of cathodic metal can be reduced further, thus improving its reverse-conducting characteristic, and
And further reduce the chip area that Ohmic electrode takies, the more efficient miniaturization realizing electronic circuit.
Describe the method for Schottky chip in the present embodiment that manufactures below with reference to Fig. 5, Fig. 5 is to illustrate by order of steps
Manufacture the method flow diagram of Schottky chip in the present embodiment.
With reference to Fig. 5, silicon substrate preparation process (S10) is first carried out.In this substrate preparation process, prepared silicon substrate 2, appoint
Monocrystalline silicon piece prepared by what preparation method all can be as this silicon substrate 2, such as: prepare have the heavy doping phosphorus that crystal orientation is<111>
N-type silicon substrate.
It follows that perform silicon epitaxy layer forming step (S20).In this step, silicon substrate 2 forms silicon epitaxy layer 3,
The relative silicon substrate of epitaxial layer 3 has crystal orientation for<111>for being lightly doped and having conduction type as silicon substrate, such as silicon substrate
The N-type silicon substrate of heavy doping phosphorus, then silicon epitaxy layer is the single-crystal Si epitaxial layers in<111>crystal orientation of N-type conduction of light p-doped.
It follows that perform insulating barrier part forming step (S30).In this step, on the front surface 3a of silicon epitaxy layer 3
Form a silicon dioxide layer part as insulating barrier 7.Concrete, such as: be deposited on silicon epitaxy layer by performing chemical gaseous phase
Surface deposition layer of silicon dioxide layer or by the silicon layer of thermal oxide epi-layer surface, form this titanium dioxide in epi-layer surface
Silicon layer.The silicon dioxide of thermal oxide growth has more excellent film quality, and stability and reliability to device performance are more favourable,
But its speed of growth is slow, therefore, the present invention performs this insulating barrier part forming step and preferably employs and first pass through thermal oxide in extension
Layer surface forms one layer of i.e. once oxidation layer 71 of thin silicon dioxide layer, then is continued at first time dioxy by chemical gaseous phase deposition
Depositing second layer silicon dioxide layer i.e. secondary oxidation layer 72 on SiClx layer, the gross thickness of twice silicon dioxide layer reaches this step institute
The thickness of silicon dioxide layer required, the most both ensure that the insulation characterisitic that insulating barrier is good, it is ensured that resulting devices performance steady
Qualitative and reliability, also ensure that the efficiency of production technology simultaneously, but this step is not limited to described carry out twice oxidation
Method.
It follows that perform groove forming step (S40).Concrete, this step is with the silicon dioxide formed in previous step
Layer is hard mask, runs through the groove of whole silicon epitaxy layer by etching of photoetching and Etch selectivity.As preferably, according to figure
3, groove and the Schottky electrode number of Ohmic electrode are arranged one to one；Preferred, according to Fig. 4, the ditch of Ohmic electrode as another
Groove arrangement is that the trench cycle arrangement of some through-silicon epitaxial layers 3 forms, therefore in this groove forming step, and the opening of each groove
Width h1 is preferably 0.6～1.2 μm, and the gap epitaxial layer width h2 between two grooves is preferably 0.5～2 μm.Latter groove
Arrangement optimal way, the more easy to control and saving process time in production technology.
It follows that fill polysilicon step (S50).In this step, the groove formed above is filled heavily doped many
Crystal silicon 61, this polysilicon 61 has the first conduction type as silicon epitaxy layer 3, such as, fills the polysilicon of heavy doping phosphorus,
Its conduction type is N-type, and the preferably square resistance of this heavily doped polysilicon is 14～20 Ω/sq.Concrete execution step
For: first clean total layer surface；Afterwards at the polysilicon of total layer surface deposition of heavily doped, it is ensured that whole groove quilt
Fill；Selective removal partial polysilicon afterwards, before making last to be filled with polysilicon and polysilicon and epitaxial layer 3 in groove
Surface 3a is concordant.
It follows that the protection ring 41 forming step (S60) of Schottky electrode.Protection ring 41 uses ion implantation to be formed,
The conduction type of protection ring 41 is the second conduction type, contrary with the first conduction type, such as: the first conduction type is N-type, then
Protection ring uses ion implantation to inject boron ion, has conduction type p-type.Concrete, such as: etch oxidation by photoresist
Layer opening so that it is expose silicon epitaxy layer；Then by ion implantation doping agent；Remove photoresist and clean total layer table
Face.
Formed and ion diffusing step (S70) it follows that perform insulating barrier another part.In this step, by chemistry
Vapour deposition process deposition layer of silicon dioxide, as three oxide layers 73 of insulating barrier another part, grows three oxide layers 73
While, by high temperature action during oxidation, carry out injecting the thermal diffusion of ion, thus ultimately form protection ring 41.Concrete, first
Clean the surface of total layer；Afterwards on total layer surface by chemical vapor deposition layer of silicon dioxide layer
I.e. three times oxide layers 73, in deposition process, by controlling temperature and time during oxidation, have met required silicon oxide layer simultaneously
The formation of thickness and the control of injection ion diffusion length, thus form final anodic protection while forming silicon oxide layer
Ring.
It follows that perform barrier metal and top-level metallic forming step (S80).In this step, complete at anode openings
Become the formation of barrier metal 42, thus form barrier metal 42 and the Schottky contacts of silicon epitaxy layer 3 at anode；In this step,
Also complete top layer anode metal 43 and the formation of cathodic metal 63, anode metal and cathodic metal can select same metal example
As all selected TiNiAg, or all select CrNiAu etc.；Different metals can also be selected to make anode and negative electrode respectively, but two is electric
Pole selects different metals, can increase a photoetching and the technique of metal formation, and device cost can increase therewith, therefore, and this
The most same bright metal is as two electrode matel material, but the invention is not restricted to this selection.Concrete, first carry out insulating barrier
Photoetching corrosion step (S81), selective removal, as the silicon dioxide layer of insulating barrier, opens negative electrode and anode openings, anode
Exposing the front surface 3a of silicon epitaxy layer 3, negative electrode exposes the upper surface of conductive polycrystalline silicon 61 and (forms the Schottky chip of Fig. 4
When 12, at this, also can expose the front surface of each trench gap epitaxial layer)；Then barrier metal deposition step (S82), gesture are carried out
The method building metal deposit can be magnetron sputtering or metal fever evaporation etc.；Then carry out negative electrode and anode metal forms (S83)
Step；Finally carry out metal lithographic corrosion step (S84), to open opening, cut-out anode metal and the moon exposing insulating barrier 7
Electrically connecting between the metal of pole.Preferably, such as barrier metal is Ni, and corresponding anode and cathodic metal select TiNiAg, because of
For Ti and Ni, there is good adhesive force, it is ensured that contact good between metal, lower conducting resistance, also reduce surface metal and come off
Risk；For another example: barrier metal is Ni, corresponding anode and cathodic metal select TiWNiVAl；For another example: barrier metal is Cr,
Corresponding anode and cathodic metal select CrNiAu or CrTiWNiVAl.But barrier metal of the present invention and negative electrode and anode metal
Selection is not limited to listed herein.Preferably, after carrying out barrier metal deposition step (S82), once make annealing treatment,
Make it form metal alloy with silicon epitaxy layer 3 surface silicon, to increase barrier height, reduce reverse leakage current, simultaneously metal alloy
Barrier height the most stable, such as: barrier metal is NiPt alloy, is formed after barrier metal NiPt, carries out annealing treatment
Reason, in this annealing process, at anode openings, barrier metal NiPt forms nickel silicon alloy on silicon epitaxy layer 3 surface with monocrystal silicon
And platinum silicon alloy.
(the second embodiment)
Fig. 6 is to schematically show the cross-sectional view of Schottky chip 20 in the present embodiment.As shown in Figure 6, Xiao in the present embodiment
Special base chip 20 is with the difference of Schottky chip in first embodiment 11: Schottky chip farther includes: if
The lateral margin of the groove of dry through-silicon epitaxial layer 3, is provided with sealing coat 62 between conductive polycrystalline silicon 61 and groove lateral margin；Preferably, every
The insulant that absciss layer 62 is identical with insulating barrier selection, such as the same with insulating barrier 71 silicon dioxide that all uses, the most permissible
While insulating barrier 71 is formed, complete the formation of this sealing coat 62, decrease processing step, the manufacturing cost of saving components；
The preferably thickness of this silicon dioxide sealing coat is 400～3000A.But it is necessary with insulating barrier 7 that the present invention is not limited to sealing coat 62
Select the same material, it is possible to use different insulant respectively, but both use different materials, can increase the most exhausted
Edge material is formed and chemical wet etching step, and device cost increases.The Schottky chip 20 of the present embodiment is relative to first embodiment
Schottky chip 11 because conductive polycrystalline silicon and groove lateral margin have been carried out further insulant isolation, therefore enter one
The Schottky electrode being effectively isolated chip of step and Ohmic electrode, decrease highly doped conductive polycrystalline silicon at subsequent high temperature simultaneously
The diffusion of dopant ion in technique, reduce further the reverse leakage current of this Schottky chip so that it is reverse blocking capability increases
By force, good reliability.
Fig. 7 is by the flow chart of the method for Schottky chip 20 in the manufacture the present embodiment shown in order of steps.
With reference to Fig. 7, silicon substrate preparation process (S10) being first carried out, this step is identical with first embodiment.
It follows that perform silicon epitaxy layer forming step (S20), this step is identical with first embodiment.
It follows that perform insulating barrier part forming step (S30).This step is identical with first embodiment.
It follows that perform groove forming step (S40).This step is identical with first embodiment.
It follows that perform sealing coat forming step (S90).In this step, conductive polycrystalline silicon 61 and groove lateral margin are completed
Between the making of sealing coat 62.Concrete, such as: first carry out oxidation step (S91), be deposited on whole knot by chemical gaseous phase
Structure surface deposition layer of silicon dioxide layer, can use thermal oxide in this step, its thickness is preferably 400～600A, or adopts
With wet-oxygen oxidation, its thickness is 1000～3000A；Then perform sealing coat photoetching corrosion step (S92), selected by photoetching corrosion
The silicon dioxide layer removing channel bottom of selecting property, exposes the front surface 3a of the silicon epitaxy layer 3 of channel bottom, and is retained in ditch
The silicon dioxide layer that groove lateral margin is formed, the silicon dioxide layer of this groove lateral margin i.e. constitutes described sealing coat 62.
It follows that perform to fill polysilicon step (S50), the protection ring 41 forming step (S60) of Schottky electrode, insulation
Layer another part is formed and ion diffusing step (S70), barrier metal and top-level metallic forming step (S80).These steps
Identical with first embodiment.
Certainly, in the present embodiment, the groove arrangement of Schottky chip 20 equally uses such as Schottky in first embodiment
The periodic arrangement mode of chip 12, its alternative approach equivalent and Schottky chip 11 to Schottky chip 12 in first embodiment
Change.
Hereinafter, the example of the present invention will be described.
Example 1
The manufacture method of Schottky chip 11, the basis produced in the first embodiment of the invention that this example illustrates according to Fig. 5
The Schottky chip of example.
Concrete, silicon substrate preparation process, employ the N-type silicon substrate of the heavy doping phosphorus that crystal orientation is<111>, resistivity is
0.0010Ω·cm。
It follows that silicon epitaxy layer is formed, define the silicon epitaxy layer in<111>crystal orientation of the N-type conduction of light p-doped, silicon epitaxy
Layer thickness 3.6 μm, resistivity 0.56 Ω cm.
It follows that first pass through thermal oxide first grow the silicon dioxide of one layer of once oxidation layer 500A, then pass through wet-oxygen oxidation
Form the silicon dioxide of secondary oxidation layer 5000A.
It follows that to form silicon dioxide layer above as hard mask, optionally etched by photoetching and dry etching
One rectangular groove, and the front surface 3a of silicon epitaxy layer is exposed at channel bottom.
It follows that by LPCVD deposition process in the groove formed above, the conduction filling Doping Phosphorus in the trench is many
Crystal silicon, the square resistance of conductive polycrystalline silicon is 18 Ω/sq.
It follows that etch oxide layer opening by photoresist so that it is expose silicon epitaxy layer；Then ion implanting is passed through
Adulterant boron, forms the protection ring 41 of Schottky electrode；Remove photoresist and clean total layer surface.
It follows that formed the silicon dioxide of three i.e. thickness 3300A of oxide layer by chemical vapor deposition, simultaneously
By high temperature action during oxidation, carry out injecting the thermal diffusion of ion, thus ultimately formed protection ring 41.
It follows that form barrier metal and two electrode metals.Concrete, the photoetching first carrying out insulating barrier silicon dioxide is rotten
Erosion, optionally removes silicon dioxide layer, opens negative electrode and anode openings；Then carry out having carried out potential barrier by metal fever evaporation
W metal deposits, and the thickness of Ni is 500A；Then carry out at a temperature of 450 degree, N2 protects the annealing under atmosphere, at this
In annealing process, at anode openings, barrier metal Ni defines nickel silicon alloy, nisiloy on silicon epitaxy layer 3 surface with monocrystal silicon
Alloy and silicon epitaxy layer constitute Schottky contacts, form potential barrier；Use metal fever evaporation afterwards, on total layer surface
Form metal level TiNiAg；Finally carry out metal lithographic corrosion, to open opening, the cut-out anode gold exposing silicon dioxide layer
Belong to the connection between cathodic metal.
Example 2
The manufacture method of Schottky chip 20, this reality produced in the embodiment of the present invention two that this example illustrates according to Fig. 7
The Schottky chip of example.The Schottky chip of this example and example 1 difference are add at groove lateral margin and conduct electricity many
Silicon dioxide sealing coat between crystal silicon, this silicon dioxide sealing coat is formed by wet-oxygen oxidation, and its thickness is 1500A, remaining
As all identical with example 1 in silicon substrate, silicon epitaxy layer, conductive polycrystalline silicon, barrier metal, two electrode metals etc..
Claims (11)
1. the manufacture method for the Schottky chip of wafer-level package, it is characterised in that comprise the following steps:
One) silicon substrate (2) preparation process；Described silicon substrate has the first conduction type；
Two) silicon epitaxy layer (3) forming step；Described silicon epitaxy layer has the first conduction type；
Three) insulating barrier part forming step: by thermal oxide or/and chemical gaseous phase is deposited on silicon epitaxy layer surface deposition titanium dioxide
Silicon layer；
Four) groove forming step: by being dry-etched between the front surface of silicon substrate and the front surface of silicon epitaxy layer formation Europe
Some grooves of nurse electrode, groove through-silicon epitaxial layer；
Five) polysilicon step is filled: in described groove, fill conductive polycrystalline silicon as trench filling (61)；Described conduction is many
Crystal silicon has the first conduction type；
Six) around Schottky electrode, ion implantation forms the protection ring (41) of Schottky electrode；Inject the Schottky formed
Electrode protection ring has the second conduction type, contrary with the first conduction type；
Seven) insulating barrier another part is formed and ion diffusing step: made by chemical vapor deposition layer of silicon dioxide
For insulating barrier another part that is three time oxide layer (73), while three oxide layer growths, utilize high temperature action when aoxidizing,
Carry out the thermal diffusion injecting ion that step (six) completes；
Eight) barrier metal and top-level metallic forming step: in this step, completes the formation of barrier metal, thus is formed at anode
Barrier metal and the Schottky contacts of silicon epitaxy layer；In this step, also complete top-level metallic anode metal and negative electrode couples metal
Formation, form Schottky electrode (4) and Ohmic electrode (6) respectively.
The manufacture method of a kind of Schottky chip for wafer-level package the most according to claim 1, it is characterised in that:
Described four), in groove forming step, the number of the groove of formation and Schottky electrode number are for arrange one to one；Step 8) in
Described negative electrode couple metal be formed as on trench filling (61) formed cathodic metal (63).
The manufacture method of a kind of Schottky chip for wafer-level package the most according to claim 1, it is characterised in that:
Described four), in groove forming step, the groove of multiple periodic arrangement is formed；Step 8) described in negative electrode couple metal formed bag
Include the formation barrier metal (42) on the gap epitaxial layer between the groove of periodic arrangement and at whole Ohmic electrode top layer
Formation cathodic metal (63), this barrier metal and cover cathodic metal thereon (63) and trench gap epitaxial layer and formed
Electrically connect.
The manufacture method of a kind of Schottky chip for wafer-level package the most according to claim 3, it is characterised in that:
Described four), in groove forming step, the A/F of each groove of periodic arrangement is 0.6～1.2 μm, the gap between two grooves
Epitaxial layer width is 0.5～2 μm.
5. according to the manufacture method of a kind of Schottky chip for wafer-level package described in Claims 1 to 4 any one,
Characterized by further comprising following steps:
Sealing coat forming step: in this step, makes sealing coat (62) between conductive polycrystalline silicon (61) and groove lateral margin；Its
Step is deposited on total surface deposition layer of silicon dioxide layer for first passing through chemical gaseous phase；Then selected by photoetching corrosion
Property remove channel bottom silicon dioxide layer, expose the front surface of the silicon epitaxy layer of channel bottom, and be retained in channel side
The silicon dioxide layer that edge is formed, the silicon dioxide layer of this groove lateral margin constitutes described sealing coat (62).
The manufacture method of a kind of Schottky chip for wafer-level package the most according to claim 5, it is characterised in that
Described by chemical gaseous phase be deposited on total surface deposition layer of silicon dioxide layer be: by thermal oxidation method formed 400～
The silicon dioxide layer of 600A thickness.
The manufacture method of a kind of Schottky chip for wafer-level package the most according to claim 5, it is characterised in that
Described by chemical gaseous phase be deposited on total surface deposition layer of silicon dioxide layer be: by wet oxidation method formed 1000
～the silicon dioxide layer of 3000A thickness.
8. according to the manufacture method of a kind of Schottky chip for wafer-level package described in any one of Claims 1 to 4, its
It being characterised by: described eight) barrier metal and top-level metallic forming step be: first carry out the photoetching corrosion of insulating barrier, optionally
Removing the silicon dioxide layer as insulating barrier, open negative electrode and anode openings, anode exposes the front surface of silicon epitaxy layer, negative electrode
Expose the front surface of gap epitaxial layer between upper surface and the groove of conductive polycrystalline silicon；
Then barrier metal deposition is carried out；
Carry out negative electrode and anode metal forming step again；
Finally carry out metal lithographic corrosion, with open expose insulating barrier opening, cut off between anode metal and cathodic metal
Electrically connect.
The manufacture method of a kind of Schottky chip for wafer-level package the most according to claim 8, it is characterised in that:
Described eight), in barrier metal and top-level metallic forming step, after carrying out barrier metal deposition, once make annealing treatment,
Barrier metal is made to form metal alloy with the front surface silicon of silicon epitaxy layer.
10. according to the manufacture method of a kind of Schottky chip for wafer-level package described in any one of Claims 1 to 4,
It is characterized in that: the square resistance of the conductive polycrystalline silicon filled in described groove is 14～20 Ω/sq.
The manufacture method of 11. a kind of Schottky chip for wafer-level package according to claim 1, its feature exists
In: described three) insulating barrier part forming step is: first passes through thermal oxide and forms layer of silicon dioxide layer that is one in epi-layer surface
Secondary oxide layer (71), then continue on first time silicon dioxide layer, to deposit second layer silicon dioxide layer i.e. by chemical gaseous phase deposition
Secondary oxidation layer (72).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106409828A (en) * | 2016-11-30 | 2017-02-15 | 上海芯石微电子有限公司 | Half-bridge rectification Schottky device suitable for miniaturization packaging and manufacturing method thereof |
| CN109390231A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | A kind of manufacturing method of channel schottky front silver surface metal structure |
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| US20060030142A1 (en) * | 2004-08-03 | 2006-02-09 | Grebs Thomas E | Semiconductor power device having a top-side drain using a sinker trench |
| CN102769043A (en) * | 2011-05-04 | 2012-11-07 | 刘福香 | Schottky diode and manufacturing method thereof |
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| CN1708850A (en) * | 2002-11-06 | 2005-12-14 | 国际整流器公司 | Chip-scale schottky device |
| US20060030142A1 (en) * | 2004-08-03 | 2006-02-09 | Grebs Thomas E | Semiconductor power device having a top-side drain using a sinker trench |
| CN102769043A (en) * | 2011-05-04 | 2012-11-07 | 刘福香 | Schottky diode and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106409828A (en) * | 2016-11-30 | 2017-02-15 | 上海芯石微电子有限公司 | Half-bridge rectification Schottky device suitable for miniaturization packaging and manufacturing method thereof |
| CN106409828B (en) * | 2016-11-30 | 2023-06-02 | 上海芯石微电子有限公司 | Half-bridge rectifying schottky device suitable for miniaturized packaging and manufacturing method |
| CN109390231A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | A kind of manufacturing method of channel schottky front silver surface metal structure |
| CN109390231B (en) * | 2017-08-08 | 2021-10-08 | 天津环鑫科技发展有限公司 | Manufacturing method of groove type Schottky front silver surface metal structure |
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