CN109037206B - Power device protection chip and manufacturing method thereof - Google Patents
Power device protection chip and manufacturing method thereof Download PDFInfo
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- CN109037206B CN109037206B CN201810817024.4A CN201810817024A CN109037206B CN 109037206 B CN109037206 B CN 109037206B CN 201810817024 A CN201810817024 A CN 201810817024A CN 109037206 B CN109037206 B CN 109037206B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 74
- 229920005591 polysilicon Polymers 0.000 claims abstract description 66
- 238000002347 injection Methods 0.000 claims abstract description 56
- 239000007924 injection Substances 0.000 claims abstract description 56
- 230000000149 penetrating effect Effects 0.000 claims abstract description 15
- 238000002513 implantation Methods 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 33
- 239000010410 layer Substances 0.000 description 435
- 239000004065 semiconductor Substances 0.000 description 19
- 238000009792 diffusion process Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000000407 epitaxy Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- 238000005137 deposition process Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 238000000927 vapour-phase epitaxy Methods 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000003749 cleanliness Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a power device protection chip and a manufacturing method thereof, wherein the power device protection chip comprises the following steps: a substrate of a first conductivity type; a first epitaxial layer of a second conductivity type; a first buried layer of a first conductivity type and a second buried layer of a second conductivity type formed in the first epitaxial layer; a second epitaxial layer of the first conductivity type; a first implanted region of a first conductivity type and a second implanted region of a second conductivity type formed on the upper surface of the second epitaxial layer, the first implanted region being connected to the second implanted region; a polysilicon layer penetrating the second epitaxial layer and connected to the first implanted region and the first buried layer, respectively; the dielectric layer is formed on the upper surface of the second epitaxial layer; the first electrode comprises a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer; and the second electrode is formed on the lower surface of the substrate. The invention can improve the performance of the device and reduce the cost of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power device protection chip and a manufacturing method thereof.
Background
The power device protection chip is a solid semiconductor device specially designed for protecting sensitive semiconductor devices from transient voltage surge damage, and has the advantages of small clamping coefficient, small volume, fast response, small leakage current, high reliability and the like, so that the power device protection chip is widely applied to voltage transient and surge protection. The low-capacitance power device protection chip is suitable for a protection device of a high-frequency circuit, because the interference of parasitic capacitance to the circuit can be reduced, and the attenuation of signals of the high-frequency circuit can be reduced.
Electrostatic discharge, and other transient voltages that occur randomly in the form of some voltage surge, are commonly present in a variety of electronic devices. As semiconductor devices increasingly tend to be miniaturized, high density, and multifunctional, electronic devices are increasingly susceptible to voltage surges, even fatal damage. The protection chip of the power device can induce transient current peak from various voltage surges from static discharge to lightning and the like, and is usually used for protecting sensitive circuits from surge. Based on different applications, the power device protection chip can play a circuit protection role by changing a surge discharge path and the clamping voltage of the power device protection chip.
At present, if bidirectional protection is required, a plurality of power device protection chips need to be connected in series or in parallel, so that the area and the manufacturing cost of the device are increased.
Disclosure of Invention
The invention provides a power device protection chip and a manufacturing method thereof based on the problems, which can improve the performance of the power device protection chip and reduce the manufacturing cost of the power device protection chip.
In view of this, an aspect of the embodiments of the present invention provides a power device protection chip, where the power device protection chip includes:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type grown on the upper surface of the substrate;
the first buried layer of the first conductivity type and the second buried layer of the second conductivity type are formed in the first epitaxial layer, at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
a second epitaxial layer of the first conductivity type formed on the upper surface of the first epitaxial layer, and the first buried layer has a higher doping concentration than the second epitaxial layer;
a first implantation region of a first conductivity type and a second implantation region of a second conductivity type formed on the upper surface of the second epitaxial layer, the first implantation region being connected to the second implantation region, the first implantation region having a higher doping concentration than the second epitaxial layer;
a polysilicon layer penetrating the second epitaxial layer and connected to the first implanted region and the first buried layer, respectively;
the dielectric layer is formed on the upper surface of the second epitaxial layer;
the first electrode comprises a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer;
and the second electrode is formed on the lower surface of the substrate and is connected with the substrate.
Further, the doping concentration of the first implanted region is higher than that of the first buried layer.
Further, the doping concentration of the second buried layer is higher than that of the second implanted region.
Further, the second buried layer is disposed opposite to the second implanted region.
Further, the first buried layer includes a first sub buried layer and a second sub buried layer respectively disposed at both sides of the second buried layer, the first implanted region includes a first sub implanted region and a second sub implanted region respectively disposed at both sides of the second implanted region, and the polysilicon layer includes a first polysilicon layer connected to the first sub buried layer and the first sub implanted region, and a second polysilicon layer connected to the second sub buried layer and the second sub implanted region.
Another aspect of the embodiments of the present invention provides a method for manufacturing a power device protection chip, where the method includes:
growing a first epitaxial layer of a second conductivity type on the upper surface of a substrate of the first conductivity type;
forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type in the first epitaxial layer, wherein at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer, wherein the doping concentration of the first buried layer is higher than that of the second epitaxial layer;
forming a first trench penetrating through the second epitaxial layer and extending to the first buried layer, and forming a second trench located on an upper side of the first trench and communicating with the first trench;
forming a first injection region of a first conductivity type and a second injection region of a second conductivity type on the upper surface of the second epitaxial layer, and connecting the first injection region with the first injection region, wherein the doping concentration of the first injection region is higher than that of the second epitaxial layer;
forming a polysilicon layer connected with the first buried layer in the first trench and the second trench, and connecting the polysilicon layer with the first injection region;
forming a dielectric layer on the upper surface of the second epitaxial layer;
forming a first electrode, wherein the first electrode comprises a first part which penetrates through the dielectric layer and extends to the second injection region and a second part which is formed on the surface of the dielectric layer;
and forming a second electrode connected with the substrate on the lower surface of the substrate.
Further, the doping concentration of the first implanted region is higher than that of the first buried layer.
Further, the doping concentration of the second buried layer is higher than that of the second implanted region.
Further, the second buried layer is disposed opposite to the second implanted region.
Further, the first buried layer includes a first sub buried layer and a second sub buried layer respectively disposed at both sides of the second buried layer, the first implanted region includes a first sub implanted region and a second sub implanted region respectively disposed at both sides of the second implanted region, and the polysilicon layer includes a first polysilicon layer connected to the first sub buried layer and the first sub implanted region, and a second polysilicon layer connected to the second sub buried layer and the second sub implanted region.
The technical scheme of the embodiment of the invention is that a first epitaxial layer of a second conduction type is grown on the upper surface of a substrate of a first conduction type; forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type in the first epitaxial layer, wherein at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer; forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer, wherein the doping concentration of the first buried layer is higher than that of the second epitaxial layer; forming a first trench penetrating through the second epitaxial layer and extending to the first buried layer, and forming a second trench located on an upper side of the first trench and communicating with the first trench; forming a first injection region of a first conductivity type and a second injection region of a second conductivity type on the upper surface of the second epitaxial layer, and connecting the first injection region with the first injection region, wherein the doping concentration of the first injection region is higher than that of the second epitaxial layer; forming a polysilicon layer connected with the first buried layer in the first trench and the second trench, and connecting the polysilicon layer with the first injection region; forming a dielectric layer on the upper surface of the second epitaxial layer; forming a first electrode, wherein the first electrode comprises a first part which penetrates through the dielectric layer and extends to the second injection region and a second part which is formed on the surface of the dielectric layer; and forming a second electrode connected with the substrate on the lower surface of the substrate. The technical scheme of the invention reduces the difficulty of the device manufacturing process, greatly reduces the parasitic capacitance and improves the protection characteristic and the reliability of the device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a power device protection chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power device protection chip according to an embodiment of the present invention;
fig. 3 to fig. 10 are schematic structural diagrams illustrating steps of a method for manufacturing a power device protection chip according to an embodiment of the present invention;
fig. 11 is an equivalent circuit diagram of a power device protection chip structure according to an embodiment of the present invention;
in the figure: 1. a substrate; 2. a first epitaxial layer; 3. a first buried layer; 4. a second buried layer; 5. a second epitaxial layer; 6. a first trench; 7. a first implanted region; 8. a second implanted region; 9. a second trench; 10. a polysilicon layer; 11. a dielectric layer; 12. a first electrode; 121. a first portion; 122. a second portion; 13. a second electrode; a1, a first diode; b1, a second diode; c1, a third diode; a2, fourth diode; b2, a fifth diode; c2, a sixth diode.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing methods and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The following describes a method for manufacturing a power device protection chip in detail with reference to the accompanying drawings.
A power device protection chip and a method for manufacturing the same according to an embodiment of the present invention are described in detail below with reference to fig. 1 to 10.
An embodiment of the present invention provides a method for manufacturing a power device protection chip, as shown in fig. 1 and fig. 2, the method for manufacturing the power device protection chip includes:
step S1: growing a first epitaxial layer 2 of a second conduction type on the upper surface of a substrate 1 of a first conduction type;
step S2: forming a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type in the first epitaxial layer 2, wherein at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2;
step S3: forming a second epitaxial layer 5 of the first conductivity type on the upper surface of the first epitaxial layer 2, and the doping concentration of the first buried layer 3 is higher than that of the second epitaxial layer 5;
step S4: forming a first trench 6 penetrating through the second epitaxial layer 5 and extending to the first buried layer 3, and forming a second trench 9 located on an upper side of the first trench 6 and communicating with the first trench 6;
step S5: forming a first implantation region 7 of a first conductivity type and a second implantation region 8 of a second conductivity type on the upper surface of the second epitaxial layer 5, and connecting the first implantation region 7 with the first implantation region 7, wherein the doping concentration of the first implantation region 7 is higher than that of the second epitaxial layer 5;
step S6: forming a polysilicon layer 10 connected with the first buried layer 3 in the first trench 6 and the second trench 9, and connecting the polysilicon layer 10 with the first implantation region 7;
step S7: forming a dielectric layer 11 on the upper surface of the second epitaxial layer 5;
step S8: forming a first electrode 12, wherein the first electrode 12 comprises a first portion 121 penetrating through the dielectric layer 11 and extending to the second injection region 8 and a second portion 122 formed on the surface of the dielectric layer 11; a second electrode 13 connected to the substrate 1 is formed on the lower surface of the substrate 1.
Specifically, the first conductive type is one of P-type doping and N-type doping, and the second conductive type is the other of P-type doping and N-type doping.
For convenience of description, it is specifically stated herein that: the first conductivity type may be N-type doped, such that the second conductivity type is P-type doped; the first conductivity type may also be P-type doped, whereby the second conductivity type is N-type doped. It is to be understood that, when the first conductivity type is P-type doping and the second conductivity type is N-type doping, the substrate 1, the first buried layer 3, the second epitaxial layer 5 and the first implanted region 7 are all P-type doping, and the first epitaxial layer 2, the second buried layer 4 and the second implanted region 8 are all N-type epitaxial layers. When the first conductivity type is N-type doping and the second conductivity type is P-type doping, the substrate 1, the first buried layer 3, the second buried layer 5 and the first implanted region 7 are all N-type doping, and the first epitaxial layer 2, the second buried layer 4 and the second implanted region 8 are all P-type epitaxial layers. In the following embodiments, the first conductive type is P-type doped, and the second conductive type is N-type doped, but the invention is not limited thereto.
Specifically, the P-type substrate and the P-type epitaxy belong to a P-type semiconductor, and the N-type substrate and the N-type epitaxy belong to an N-type semiconductor. The P-type semiconductor is a silicon wafer doped with trivalent elements, such as boron elements, indium elements, aluminum elements or any combination of the three. The N-type semiconductor is a silicon wafer doped with pentavalent elements, such as phosphorus or arsenic or any combination of the phosphorus and the arsenic.
Referring to fig. 3, step S1 is executed, specifically: a first epitaxial layer 2 of a second conductivity type is grown on the upper surface of a substrate 1 of a first conductivity type. The method for growing the first epitaxial layer 2 of the second conductivity type on the upper surface of the substrate 1 of the first conductivity type is not limited to a fixed method, and the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by using epitaxial growth, or the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by ion implantation and/or diffusion. Further, the epitaxial growth may be used to form the first epitaxial layer 2 on the upper surface of the substrate 1, and the first epitaxial layer 2 may also be formed on the upper surface of the substrate 1 by ion implantation and/or diffusion of phosphorus or arsenic or any combination of the two. In particular, the method of epitaxy or diffusion comprises a deposition process. In some embodiments of the present invention, the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by using a deposition process, for example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, and sputtering. Preferably, the first epitaxial layer 2 is formed on said substrate 1 using chemical vapor deposition, which comprises a vapor phase epitaxy process. In production, chemical vapor deposition mostly uses a vapor phase epitaxy process, the first epitaxial layer 2 is formed on the upper surface of the substrate 1 by using the vapor phase epitaxy process, and the vapor phase epitaxy process can improve the perfection of a silicon material, improve the integration level of a device, prolong the minority carrier lifetime and reduce the leakage current of a storage unit. Preferably, the first epitaxial layer 2 and the substrate 1 are made of silicon material, so that the substrate 1 and the first epitaxial layer 2 have silicon surfaces with the same crystal structure, thereby maintaining control over impurity type and concentration. In addition, the first epitaxial layer 2 reduces series resistance while optimizing the breakdown voltage of the PN junction, and improves the device speed under moderate current intensity.
Referring to fig. 4, step S2 is executed, specifically: forming a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type in the first epitaxial layer 2, wherein at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2. The first buried layer 3 and the second buried layer 4 may be formed by epitaxial growth, and may also be formed by ion implantation and/or diffusion. Further, the first buried layer 3 may be formed by epitaxial growth, and may be formed by ion implantation and/or diffusion of phosphorus or arsenic or any combination of the two. Similarly, the second buried layer 4 may be formed by epitaxial growth, or may be formed by ion implantation and/or diffusion of a boron element, an indium element, an aluminum element, or any combination thereof. Preferably, the first buried layer 3 and the second buried layer 4 may be formed using an ion implantation method, and the formation of the first buried layer 3 and the second buried layer 4 by ion implantation enables precise control of the total dose, depth distribution, and surface uniformity of impurities, prevents re-diffusion of original impurities, and the like, and may implement a self-aligned technique to reduce a capacitive effect. In some embodiments of the present invention, at least a portion of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed to the upper surface of the first epitaxial layer 2, that is, the upper surfaces of the first buried layer 3 and the second buried layer 4 are exposed to the first epitaxial layer 2.
Referring to fig. 5, step S3 is executed to specifically: a second epitaxial layer 5 of the first conductivity type is formed on the upper surface of the first epitaxial layer 2, and the doping concentration of the first buried layer 3 is higher than that of the second epitaxial layer 5. The manner of forming the second epitaxial layer 5 of the first conductivity type on the upper surface of the first epitaxial layer 2 is not limited to a fixed manner, and the second epitaxial layer 5 may be formed by using an epitaxy, diffusion and/or implantation method, and specifically, the epitaxy or diffusion method includes a deposition process. Further, the second epitaxial layer 5 may be formed using methods of epitaxy, diffusion and/or implantation of elemental phosphorus or elemental arsenic or any combination of the two. In some embodiments of the present invention, the second epitaxial layer 5 is formed on the upper surface of the first epitaxial layer 2 using a deposition process, for example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering. The chemical vapor deposition comprises a vapor phase epitaxy process, preferably, the second epitaxial layer 5 is formed on the upper surface of the first epitaxial layer 2 by using the vapor phase epitaxy process, the perfectness of the silicon material can be improved by the vapor phase epitaxy process, the integration level of a device is improved, the minority carrier lifetime is prolonged, and the leakage current of the storage unit is reduced. The second epitaxial layer 5 covers the upper surface of the first epitaxial layer 2 and has a certain thickness.
Further, the doping concentration of the first buried layer 3 is different from the doping concentration of the second epitaxial layer 5. Preferably, the doping concentration of the first buried layer 3 is higher than that of the second epitaxial layer 5, and the first buried layer 3 is heavily doped, so that the resistivity of the first buried layer 3 is lower than that of the second epitaxial layer 5, and current flows along the buried layer with low resistivity to the lower side of the first epitaxial layer 2 without overflowing into the second epitaxial layer 5, thereby forming parallel branches.
Referring to fig. 6 and 8, step S4 is executed, specifically: a first trench 6 is formed through the second epitaxial layer 5 and extending to the first buried layer 3, and a second trench 9 is formed on an upper side of the first trench 6 and communicating with the first trench 6. In some embodiments of the present invention, a mask material, specifically, a first photoresist, is prepared on the upper surface of the second epitaxial layer 5, a first trench 6 extending through the second epitaxial layer 5 to the first buried layer 3 is formed on the first photoresist layer by etching, and then the first photoresist is removed. The etching method comprises dry etching and wet etching, preferably, the used etching method is dry etching, the dry etching comprises light volatilization, gas phase corrosion, plasma corrosion and the like, and the dry etching is easy to realize automation, pollution is not introduced in the treatment process, and the cleanliness is high. In some embodiments of the present invention, the bottom surface of the first trench 6 is connected to the first buried layer 3, for example, the bottom surface of the first trench 6 may extend into the first buried layer 3, and the bottom surface of the first trench 6 may also be connected to the upper surface of the first buried layer 3, so as to ensure that the bottom surface of the first trench 6 is in contact with the first buried layer 3. Further, a second groove 9 coaxial with the first groove 6 is formed on the upper side of the first groove 6, and the inner diameter of the second groove 9 is larger than the inner diameter of the first groove 6. The second trench 9 is located within the second epitaxial layer 5 and one side of the second trench 9 is connected to the first implanted region 7. It should be noted that the first trench 6 and the second trench 9 communicate with each other for filling the material in the first trench 6 and the second trench 9 more quickly and efficiently. Regarding the shape of the first trench 6 and the second trench 9, those skilled in the art may select trenches with different shapes according to the electrical performance of the device, and the shape of the first trench 6 and the second trench 9 may be a rectangular trench, a square trench, a U-shaped trench, or even a ball bottom trench, etc.
Referring to fig. 7, step S5 is performed, specifically, a first implantation region 7 of the first conductivity type and a second implantation region 8 of the second conductivity type are formed on the upper surface of the second epitaxial layer 5, and the first implantation region 7 is connected to the first implantation region 7, where a doping concentration of the first implantation region 7 is higher than a doping concentration of the second epitaxial layer 5. In some embodiments of the present invention, a mask material, specifically a second photoresist, is prepared on the upper surface of the second epitaxial layer 5, and a first implanted region 7 of the first conductivity type and a second implanted region 8 of the second conductivity type are respectively formed in the second epitaxial layer 5 by a photolithography method on the second photoresist layer, where the first implanted region 7 is adjacent to and partially connected to the second implanted region 8. And forming a first implanted region 7 of the first conductivity type and a second implanted region 8 of the second conductivity type on the upper surface of the second photoresist layer by using an ion implantation and/or diffusion method, and removing the second photoresist layer. Further, a first implantation region 7 of the first conductivity type is formed on the upper surface of the second photoresist layer by ion implantation and/or diffusion of boron element, indium element, aluminum element, or any combination of the three; and simultaneously, forming a second implanted region 8 of the second conductivity type on the upper surface of the second photoresist layer by using ion implantation and/or diffusion of phosphorus element or arsenic element or any combination of the phosphorus element and the arsenic element, and finally removing the second photoresist layer.
Further, the second buried layer 4 is disposed opposite to the second implanted region 8. Preferably, the second buried layer 4 is disposed directly below the first implanted region 7, and the second implanted region 8 is disposed in the middle of the first implanted region 7, so as to form a conductive path for current to flow in order from the second implanted region 8, the first implanted region 7, the second epitaxial layer 5, and the second buried layer 4. The doping concentration of the first implanted region 7 is different from the doping concentration of the second epitaxial layer 5. Preferably, the doping concentration of the first implantation region 7 is higher than that of the second epitaxial layer 5, and when a current passes through the first implantation region 7 with the high doping concentration, the current is conducted before the second epitaxial layer 5, so that the current passes through the second implantation region 8 and the first implantation region 7, and a PN junction is formed.
Further, the doping concentration of the first implanted region 7 is different from the doping concentration of the first buried layer 3. Preferably, the doping concentration of the first implantation region 7 is higher than that of the first buried layer 3, so as to adjust the breakdown voltage of the power device protection chip.
Further, the doping concentration of the second implanted region 8 is different from the doping concentration of the second buried layer 4. Preferably, the doping concentration of the second buried layer 4 is higher than that of the second implantation region 8, so as to adjust the breakdown voltage of the power device protection chip.
Referring to fig. 9, step S6 is executed, specifically: a polysilicon layer 10 connected to the first buried layer 3 is formed in the first trench 6 and the second trench 9, and the polysilicon layer 10 is connected to the first implanted region 7. Because the first trench 6 is communicated with the second trench 9, the polysilicon layer 10 is formed in the first trench 6 and the second trench 9 by epitaxy, diffusion and/or injection, preferably, the polysilicon in the polysilicon layer 10 is doped polysilicon, the doped polysilicon reduces the open-circuit voltage under high current, and the effect of improving the breakdown voltage can be achieved by adjusting the doping concentration of the polysilicon. The first trench 6 and the second trench 9 are filled with polysilicon so that the polysilicon layer 10 forms conductive channels electrically connected to the first buried layer 3 and the first implanted region 7, respectively. Further, the polysilicon layer 10 is formed by doping phosphorus ions or boron ions into intrinsic polysilicon, and those skilled in the art can select different doped polysilicon types according to the structure of the device, and the polysilicon in the polysilicon layer 10 may be P-type polysilicon or N-type polysilicon. In particular, the method of epitaxy, diffusion and/or implantation comprises a deposition process. In some embodiments of the present invention, the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by using a deposition process, for example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, and sputtering. Preferably, the polysilicon layer 10 is formed on the substrate 1 by Low Pressure Chemical Vapor Deposition (LPCVD), and the formed polysilicon layer 10 has high purity and good uniformity.
Referring to fig. 9, step S7 is executed, specifically: a dielectric layer 11 is formed on the upper surface of the second epitaxial layer 5. A dielectric layer 11 is formed on the upper surface of the second epitaxial layer 5. The dielectric layer 11 is made of silicon oxide, silicon nitride or silicon oxynitride, and the dielectric layer 11 may be formed by sputtering, thermal oxidation or chemical vapor deposition. Preferably, the dielectric layer 11 is a silicon oxide layer formed by thermal oxidation, and in the subsequent doping step, the silicon oxide layer serves as a protective layer and will serve as an interlayer insulating layer of the final device. In addition, the dielectric layer 11 is provided with a certain thickness, so that the dielectric layer 11 plays a role in isolating current and insulating.
Further, one end of the polysilicon layer 10 penetrates through the second epitaxial layer 5 and extends to the first buried layer 3, and the other end is connected to the first implantation region 7 and the dielectric layer 11, respectively. It should be noted that the polysilicon layer 10 is formed in the first trench 6 and then in the second trench 9, and the upper surface of the polysilicon layer 10 is higher than the upper surface of the second epitaxial layer 5, so that the polysilicon layer 10 is connected not only to the first implantation region 7, but also to the dielectric layer 11.
Referring to fig. 10, step S8 is executed to specifically: forming a first electrode 12, wherein the first electrode 12 comprises a first portion 121 penetrating through the dielectric layer 11 and extending to the second injection region 8 and a second portion 122 formed on the surface of the dielectric layer 11; a second electrode 13 connected to the substrate 1 is formed on the lower surface of the substrate 1. First, a first contact hole (not shown) is formed through the dielectric layer 11 and extends to the second implantation region 8 by etching. Preferably, the first contact hole is formed by dry etching, the dry etching comprises light volatilization, gas phase corrosion, plasma corrosion and the like, and the dry etching is easy to realize automation, has no pollution introduced in the treatment process and has high cleanliness. And filling a metal material into the first contact hole to form a first part 121, and covering the upper surface of the dielectric layer 11 with the metal material to form the second part 122. The first portion 121 and the second portion 122 form a first metal layer, i.e., a first electrode 12, which is in communication with each other. The first electrode 12 is electrically connected to the second implant region 8 through the first portion 121 so that a current flows to a path formed by the second implant region 8 and the first implant region 7 to form a PN junction. In addition, a second metal layer is formed by metallizing the lower surface of the substrate 1, thereby forming a second electrode 13 electrically connected to the substrate 1. The current flows through the substrate 1 along the second electrode 13 to an external circuit.
Further, the first buried layer 3 includes a first sub buried layer and a second sub buried layer respectively disposed at two sides of the second buried layer 4, the first implanted region 7 includes a first sub implanted region and a second sub implanted region respectively disposed at two sides of the second implanted region 8, the polysilicon layer 10 includes a first polysilicon layer 10 connected to the first sub buried layer and the first sub implanted region, and a second polysilicon layer 10 connected to the second sub buried layer and the second sub implanted region, so that the whole power device protection chip forms a symmetrical device structure, and branches symmetrical at left and right sides are respectively formed outside a conductive path formed by current sequentially passing through the first electrode 12, the second implanted region 8, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, the substrate 1, and the second electrode 13.
It is understood that the first trench 6 is a deep trench, and a parallel conductive path is formed by forming the polysilicon layer 10 in the first trench 6 and the second trench 9, which are electrically connected to the first buried layer 3 and the first implanted region 7, respectively, forming the polysilicon layer 10 into a conductive channel for conducting electricity, and electrically connecting the first implanted region 7 to the first buried layer 3. In addition, the first buried layer 3 and the polysilicon layer 10 are symmetrically distributed to form a 3-way bidirectional parallel equivalent circuit, and due to the unidirectional conductivity of the diode and the small section capacitance, the access capacitance is effectively reduced, so that the parasitic capacitance of the device can be reduced in a high-frequency circuit.
A power device protection chip is described in detail below with reference to the accompanying drawings.
As shown in fig. 2, the embodiment of the present invention provides a power device protection chip, which includes:
a substrate 1 of a first conductivity type;
a first epitaxial layer 2 of a second conductivity type grown on the upper surface of the substrate 1;
a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type formed in the first epitaxial layer 2, wherein at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2;
a second epitaxial layer 5 of the first conductivity type formed on the upper surface of the first epitaxial layer 2, and the first buried layer 3 having a higher doping concentration than the second epitaxial layer 5;
a first implantation region 7 of a first conductivity type and a second implantation region 8 of a second conductivity type formed on the upper surface of the second epitaxial layer 5, wherein the first implantation region 7 is connected with the second implantation region 8, and the doping concentration of the first implantation region 7 is higher than that of the second epitaxial layer 5;
a polysilicon layer 10 penetrating through the second epitaxial layer 5 and connected to the first implanted region 7 and the first buried layer 3, respectively;
a dielectric layer 11 formed on the upper surface of the second epitaxial layer 5;
a first electrode 12 including a first portion 121 penetrating the dielectric layer 11 and extending to the second implantation region 8 and a second portion 122 formed on the surface of the dielectric layer 11;
and a second electrode 13 formed on a lower surface of the substrate 1 and connected to the substrate 1.
Specifically, the first conductive type is one of P-type doping and N-type doping, and the second conductive type is the other of P-type doping and N-type doping.
For convenience of description, it is specifically stated herein that: the first conductivity type may be N-type doped, such that the second conductivity type is P-type doped; the first conductivity type may also be P-type doped, whereby the second conductivity type is N-type doped. It is to be understood that, when the first conductivity type is P-type doping and the second conductivity type is N-type doping, the substrate 1, the first buried layer 3, the second epitaxial layer 5 and the first implanted region 7 are all P-type doping, and the first epitaxial layer 2, the second buried layer 4 and the second implanted region 8 are all N-type epitaxial layers. When the first conductivity type is N-type doping and the second conductivity type is P-type doping, the substrate 1, the first buried layer 3, the second buried layer 5 and the first implanted region 7 are all N-type doping, and the first epitaxial layer 2, the second buried layer 4 and the second implanted region 8 are all P-type epitaxial layers. In the following embodiments, the first conductive type is P-type doped, and the second conductive type is N-type doped, but the invention is not limited thereto.
Specifically, the P-type substrate and the P-type epitaxy belong to a P-type semiconductor, and the N-type substrate and the N-type epitaxy belong to an N-type semiconductor. The P-type semiconductor is a silicon wafer doped with trivalent elements, such as boron elements, indium elements, aluminum elements or any combination of the three. The N-type semiconductor is a silicon wafer doped with pentavalent elements, such as phosphorus or arsenic or any combination of the phosphorus and the arsenic.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip includes a substrate 1 of a first conductivity type and a first epitaxial layer 2 of a second conductivity type, and the first epitaxial layer 2 is grown on an upper surface of the substrate 1. In particular, the substrate 1 is a carrier in an integrated circuit, the substrate 1 plays a role of support, and the substrate 1 also participates in the operation of the integrated circuit. The substrate 1 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate, or even a silicon substrate, and preferably, the substrate 1 is a silicon substrate because the silicon substrate has the characteristics of low cost, large size, and electrical conductivity, so that the edge effect is avoided, and the yield can be greatly improved. The first epitaxial layer 2 of the second conductivity type grows on the upper surface of the substrate 1 of the first conductivity type, and reacts at the same time, and when current sequentially passes through the first epitaxial layer 2 and the substrate 1, a PN junction is formed.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip further includes a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type, the first buried layer 3 and the second buried layer 4 are both formed in the first epitaxial layer 2, at least a portion of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than the doping concentration of the first epitaxial layer 2. Further, the first buried layer 3 and the second buried layer 4 are adjacent, and the first buried layer 3 and the second buried layer 4 may be spaced apart from each other or may be connected to each other. In addition, the first buried layer 3 and the second buried layer 4 are both heavily doped, thereby reducing the resistivity of the first buried layer 3 and the second buried layer 4. Preferably, the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2, and current flows along the second buried layer 4 with low resistivity to the lower side of the first epitaxial layer 2, so that a current path is changed, which is equivalent to reduction of series resistance.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip further includes a second epitaxial layer 5 of the first conductivity type, and the second epitaxial layer 5 is formed on the upper surface of the first epitaxial layer 2. The thickness of the first epitaxial layer 2 and the second epitaxial layer 5 depends on the physical size of the semiconductor device to be realized and on the silicon loss during the device manufacturing process. The second epitaxial layer 5 grows on the upper surface of the first epitaxial layer 2, and plays a role in reducing the leakage current of PN junctions in the semiconductor device.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip further includes a first implantation region 7 of a first conductivity type and a second implantation region 8 of a second conductivity type, the first implantation region 7 and the second implantation region 8 are formed on the upper surface of the second epitaxial layer 5, the first implantation region 7 is connected to the second implantation region 8, and a doping concentration of the first implantation region 7 is higher than a doping concentration of the second epitaxial layer 5. In some embodiments of the present invention, the first injection region 7 and the second injection region 8 are both heavily doped, and since the conductivity types of the first injection region 7 and the second injection region 8 are different, the first injection region 7 and the second injection region 8 react to form a PN junction with a high doping concentration. It should be noted that the first implantation region 7 and the second implantation region 8 are adjacent and partially connected, so that current forms parallel branches along the PN junction formed by the first implantation region 7 and the second implantation region 8. Further, the doping concentration of the first implanted region 7 is higher than the doping concentration of the first buried layer 3. Further, the doping concentration of the second buried layer 4 is higher than the doping concentration of the second implanted region 8. Further, the second buried layer 4 is disposed opposite to the second implanted region 8.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip further includes a polysilicon layer 10, and the polysilicon layer 10 penetrates through the second epitaxial layer 5 and is connected to the first implanted region 7 and the first buried layer 3, respectively. The power device protection chip and even the semiconductor device are mostly made of monocrystalline silicon, the polycrystalline silicon layer 10 is respectively electrically connected with the first injection region 7 and the first buried layer 3, and current directly flows into the first buried layer 3 after passing through the first injection region 7, so that the discharge efficiency is higher. Specifically, the polycrystalline silicon layer 10 has high compatibility in single crystal silicon.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip further includes a dielectric layer 11, and the dielectric layer 11 is formed on the upper surface of the second epitaxial layer 5. The dielectric layer 11 is used to isolate the second epitaxial layer 5.
Further, one end of the polysilicon layer 10 penetrates through the second epitaxial layer 5 and extends to the first buried layer 3, and the other end is connected to the first implantation region 7 and the dielectric layer 11, respectively. One end of the polysilicon layer 10 penetrates through the second epitaxial layer 5 and extends to the first buried layer 3, and one end of the polysilicon layer 10 penetrates through the second epitaxial layer 5 and extends into the first buried layer 3, or one end of the polysilicon layer 10 penetrates through the second epitaxial layer 5 and extends to the upper surface of the first buried layer 3, so that one end of the polysilicon layer is in contact with the first buried layer 3. More specifically, the other end of the polysilicon layer 10 extends from the upper surface of the second epitaxial layer 5 into the dielectric layer 11, and a protrusion is formed higher than the surface of the second epitaxial layer 5, and in one embodiment of the present invention, the protrusion has a square or rectangular shape. The protrusion is in contact with the dielectric layer 11, and one side of the protrusion of the polysilicon layer 10 is connected to the first injection region 7, and since the dielectric layer 11 is insulated, the other end of the polysilicon layer 10 is electrically connected to the first injection region 7.
In some embodiments of the present invention, as shown in fig. 2, the power device protection chip further includes a first electrode 12, where the first electrode 12 includes a first portion 121 penetrating through the dielectric layer 11 and extending to the second implantation region 8, and a second portion 122 formed on a surface of the dielectric layer 11; the power device protection chip further comprises a second electrode 13, and the second electrode 13 is formed on the lower surface of the substrate 1 and connected with the substrate 1. In some embodiments of the present invention, the first portion 121 penetrates through the dielectric layer 11 and extends to the second implantation region 8, and may be the first portion 121 penetrates through the dielectric layer 11 and extends into the second implantation region 8, or the first portion 121 penetrates through the dielectric layer 11 and extends to an upper surface of the second implantation region 8, so as to ensure that the first portion 121 contacts the second implantation region 8. The first electrode 12 is specifically a first metal layer, the second electrode 13 is specifically a second metal layer, the first portion 121 and the second portion 122 are filled with a metal material, and the first portion 121 and the second portion 122 are connected to form the first metal layer. The first metal layer and the second metal layer are provided with a certain thickness. The second metal layer is in electrically connected relationship with the substrate 1.
Further, the first buried layer 3 includes a first sub buried layer and a second sub buried layer respectively disposed at two sides of the second buried layer 4, the first implanted region 7 includes a first sub implanted region and a second sub implanted region respectively disposed at two sides of the second implanted region 8, the polysilicon layer 10 includes a first polysilicon layer 10 connected to the first sub buried layer and the first sub implanted region, and a second polysilicon layer 10 connected to the second sub buried layer and the second sub implanted region, and the power device protection chip has a symmetrical overall structure and is a first primitive cell.
Please refer to the equivalent circuit diagram of the protection chip structure of the power device shown in fig. 11. When electricity is applied to the first electrode 12 and the second electrode 13, the current flows from the first electrode 12 to the second electrode 13. Note that, the forward direction and the reverse direction of the PN junction formed below are determined by setting the first conductivity type to be P-type and setting the second conductivity type to be N-type, which is an embodiment of the present invention, but the present invention is not limited thereto. The current sequentially passes through the first electrode 12, the second injection region 8, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, the substrate 1 and the second electrode 13 to form a main circuit. The second implanted region 8 and the second epitaxial layer 5 form an inverted PN junction and thus an inverted first diode a 1. The second epitaxial layer 5 and the second buried layer 4 form a PN junction in the forward direction, thus forming a second diode b1 in the forward direction. Said first epitaxial layer 2 and said substrate 1 form a reverse PN junction, thus forming a reverse third diode c 1. The main circuit forms an equivalent circuit consisting of three diodes. When current passes through the first electrode 12 and the second injection region 8 in sequence, the current is shunted to the polysilicon layer 10 after passing through the second injection region 8 in sequence due to the action of the first injection region 7 and the polysilicon layer 10, and then passes through the first injection region 7, the polysilicon layer 10, the first buried layer 3, the first epitaxial layer 2, the substrate 1 and the second electrode 13 in sequence to form a parallel first shunt circuit. The second implant region 8 and the first implant region 7 form an inverted PN junction, thus forming an inverted fourth diode a 2. The first buried layer 3 forms a PN junction in the forward direction with the first epitaxial layer 2, thereby forming a fifth diode b2 in the forward direction. The first epitaxial layer 2 forms an inverted PN junction with the substrate 1, thus forming an inverted sixth diode c 2. The first sub-circuit forms an equivalent circuit consisting of three diodes. In addition, since the first buried layer 3 includes the first and second sub-buried layers, the first implanted region 7 includes the first and second sub-implanted regions, and the polysilicon layer 10 includes the first and second polysilicon layers 10 and 10, the power device protection chip has a structure having a symmetrically distributed first and second sub-circuits in addition to a main circuit. In summary, the power device protection chip to be protected in the invention forms an equivalent circuit with 3 groups of diodes connected in parallel, and because the diodes have unidirectional conductivity and have smaller capacitance, the access capacitance is effectively reduced, so that the parasitic capacitance of the device can be reduced in a high-frequency circuit.
The technical scheme of the invention is described in detail in the above with reference to the attached drawings, 3 groups of power device protection chips are integrated together through the improvement of the technical scheme of the invention, the area of the device is reduced by introducing a buried layer process, the process difficulty is reduced, and the manufacturing cost of the device is reduced. Three groups of diodes are connected in parallel, parasitic capacitance is reduced, and the protection characteristic and reliability of the improved power device protection chip are improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A power device protection chip, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type grown on the upper surface of the substrate;
the first buried layer of the first conductivity type and the second buried layer of the second conductivity type are formed in the first epitaxial layer, at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
a second epitaxial layer of the first conductivity type formed on the upper surface of the first epitaxial layer, and the first buried layer has a higher doping concentration than the second epitaxial layer;
a first implantation region of a first conductivity type and a second implantation region of a second conductivity type formed on the upper surface of the second epitaxial layer, the first implantation region being connected to the second implantation region, the first implantation region having a higher doping concentration than the second epitaxial layer;
a polysilicon layer penetrating the second epitaxial layer and connected to the first implanted region and the first buried layer, respectively;
the dielectric layer is formed on the upper surface of the second epitaxial layer;
the first electrode comprises a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer;
the second electrode is formed on the lower surface of the substrate and is connected with the substrate;
the first buried layer comprises a first sub buried layer and a second sub buried layer which are arranged on two sides of the second buried layer respectively, the first injection region comprises a first sub injection region and a second sub injection region which are arranged on two sides of the second injection region respectively, the polycrystalline silicon layer comprises a first polycrystalline silicon layer connected with the first sub buried layer and the first sub injection region and a second polycrystalline silicon layer connected with the second sub buried layer and the second sub injection region, and the second buried layer and the second injection region are arranged oppositely.
2. The power device protection chip of claim 1, wherein a doping concentration of the first implanted region is higher than a doping concentration of the first buried layer.
3. The power device protection chip of claim 1, wherein a doping concentration of the second buried layer is higher than a doping concentration of the second implanted region.
4. A manufacturing method of a power device protection chip comprises the following steps:
growing a first epitaxial layer of a second conductivity type on the upper surface of a substrate of the first conductivity type;
forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type in the first epitaxial layer, wherein at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer, wherein the doping concentration of the first buried layer is higher than that of the second epitaxial layer;
forming a first trench penetrating through the second epitaxial layer and extending to the first buried layer, and forming a second trench located on an upper side of the first trench and communicating with the first trench;
forming a first injection region of a first conductivity type and a second injection region of a second conductivity type on the upper surface of the second epitaxial layer, and connecting the first injection region with the first injection region, wherein the doping concentration of the first injection region is higher than that of the second epitaxial layer;
forming a polysilicon layer connected with the first buried layer in the first trench and the second trench, and connecting the polysilicon layer with the first injection region;
forming a dielectric layer on the upper surface of the second epitaxial layer;
forming a first electrode, wherein the first electrode comprises a first part which penetrates through the dielectric layer and extends to the second injection region and a second part which is formed on the surface of the dielectric layer;
forming a second electrode connected with the substrate on the lower surface of the substrate;
the first buried layer comprises a first sub buried layer and a second sub buried layer which are arranged on two sides of the second buried layer respectively, the first injection region comprises a first sub injection region and a second sub injection region which are arranged on two sides of the second injection region respectively, the polycrystalline silicon layer comprises a first polycrystalline silicon layer connected with the first sub buried layer and the first sub injection region and a second polycrystalline silicon layer connected with the second sub buried layer and the second sub injection region, and the second buried layer and the second injection region are arranged oppositely.
5. The method as claimed in claim 4, wherein the doping concentration of the first implanted region is higher than the doping concentration of the first buried layer.
6. The method as claimed in claim 4, wherein the doping concentration of the second buried layer is higher than the doping concentration of the second implanted region.
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| CN108054164A (en) * | 2017-12-12 | 2018-05-18 | 深圳迈辽技术转移中心有限公司 | Transient Voltage Suppressor and preparation method thereof |
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