CN105870136A - Array substrate, making method thereof and display device - Google Patents
Array substrate, making method thereof and display device Download PDFInfo
- Publication number
- CN105870136A CN105870136A CN201610481624.9A CN201610481624A CN105870136A CN 105870136 A CN105870136 A CN 105870136A CN 201610481624 A CN201610481624 A CN 201610481624A CN 105870136 A CN105870136 A CN 105870136A
- Authority
- CN
- China
- Prior art keywords
- electrode
- pattern
- array base
- base palte
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 238000002161 passivation Methods 0.000 claims description 43
- 238000009413 insulation Methods 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 description 23
- 239000010408 film Substances 0.000 description 22
- 238000005530 etching Methods 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- 230000005611 electricity Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical class [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
An embodiment of the invention provides an array substrate, a making method thereof and a display device and relates to the technical field of display. Number of times of using composition process when making the array substrate. The array substrate comprises a first electrode layer, a grid metal layer and a second electrode layer, the first electrode layer comprises a reserved pattern and a first electrode, the grid metal layer is positioned on the first electrode layer and comprises a grid metal pattern positioned on the reserved pattern and directly contacting with the same, the second electrode layer comprises a second electrode arranged opposite to the first electrode, the first electrode is a common electrode, and the second electrode is a pixel electrode; or the first electrode is a pixel electrode, and the second electrode is a common electrode. The array substrate can be applied in the making process of the display device.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof,
Display device.
Background technology
As it is shown in figure 1, be the structural representation of array base palte in current display floater, making
During this array base palte, at least need to use 5-6 patterning processes, such as, a structure can be first passed through
Figure technique forms grid 13, and then forms gate insulation layer 05 on grid 13, then by once
Patterning processes is formed with active layer 02, then forms source electrode 11 and drain electrode respectively by a patterning processes
12, then form pixel electrode 01 by a patterning processes, and then in source electrode 11, drain electrode 12
And form passivation layer 04 on pixel electrode 01, finally, by a patterning processes at passivation layer
Form public electrode 03 on 04, so, can get above-mentioned array base palte through 5 patterning processes.
It can be seen that the number of times of use patterning processes is more when making above-mentioned array base palte, from
And add complexity when making array base palte and cost of manufacture.
Summary of the invention
The present invention provides the manufacture method of a kind of array base palte, it is possible to decrease make when making array base palte
With the number of times of patterning processes, and, the present invention also provides for a kind of support and reduces patterning processes
The array base palte of number of times and display device.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
On the one hand, the present invention provides a kind of array base palte, including:
First electrode layer, described first electrode layer includes: retain pattern and the first electrode；
Being positioned at the grid metal level on described first electrode layer, described grid metal level includes: be positioned at institute
State and retain the grid metal pattern directly contacted on pattern and with described reservation pattern；
The second electrode lay, described the second electrode lay includes: be oppositely arranged with described first electrode
Second electrode, wherein, described first electrode is public electrode, and described second electrode is pixel electricity
Pole；Or, described first electrode is pixel electrode, and described second electrode is public electrode.
Further, described the second electrode lay is positioned at described grid metal layer, described array base
Plate also includes:
It is positioned at the gate insulation layer on described grid metal level；
The source and drain metal level being positioned on described gate insulation layer, described source and drain metal level includes: source electrode
And drain electrode, data wire；
It is positioned at the passivation layer on described source and drain metal level；
Wherein, described the second electrode lay is positioned on described passivation layer.
Further, being provided with the first via in described passivation layer, described drain electrode is by described
One via electrically connects with described second electrode so that described second electrode is pixel electrode.
Further, being provided with the second via in described gate insulation layer, described drain electrode is by described
Second via electrically connects with described first electrode so that described first electrode is pixel electrode.
Further, described the second electrode lay also includes: connecting pattern；
Being provided with the 3rd via in described passivation layer, described connecting pattern passes through described 3rd via
It is connected with described drain electrode；
Described array base palte also has the 4th mistake running through described passivation layer and described gate insulation layer
Hole, described connecting pattern is connected with described first electrode by described 4th via so that described
First electrode is pixel electrode.
Further, described the second electrode lay also includes: the screen being oppositely arranged with described data wire
Cover electrode.
Further, described the second electrode lay also includes: signal accesses pattern, described source and drain gold
Belong to layer also to include: conductive pattern, described grid metal pattern includes public electrode wire；
Wherein, described signal accesses pattern by running through the via of described passivation layer and described conduction
Pattern electrically connects, and described conductive pattern is public with described by the via running through described gate insulation layer
Electrode wires electrically connects.
Further, described signal access pattern includes: first accesses sub pattern and second accesses
Sub pattern；
Described first accesses sub pattern by running through the 5th via of described passivation layer and described conduction
Pattern electrically connects, described second access sub pattern by run through the 6th via of described passivation layer with
Described conductive pattern electrically connects.
On the other hand, the present invention provides the manufacture method of above-mentioned array base palte, including:
Underlay substrate makes transparent conductive film and metallic film successively, and use is once covered
Lamina membranacea forms the first electrode layer and grid metal to described transparent conductive film and metallic film composition
Layer；Wherein, described first electrode layer includes: retain pattern and the first electrode, described grid metal
Layer includes: the grid metal being positioned on described reservation pattern and directly contacting with described reservation pattern
Pattern；
Described method also includes: forming the second electrode lay, described the second electrode lay includes: with institute
State the second electrode that the first electrode is oppositely arranged；
Wherein, described first electrode is public electrode, and described second electrode is pixel electrode；Or
Person, described first electrode is pixel electrode, and described second electrode is public electrode.
On the other hand, the present invention provides a kind of display device, including the battle array described in any of the above-described item
Row substrate.
So far, the present invention provides a kind of array base palte and preparation method thereof, display device, wherein,
This array base palte includes: the first electrode layer, and this first electrode layer includes: retain pattern and first
Electrode；Being positioned at the grid metal level on this first electrode layer, this grid metal level includes: be positioned at reservation
The grid metal pattern directly contacted on pattern and with reservation pattern；And, the second electrode lay,
This second electrode lay includes: the second electrode being oppositely arranged with the first electrode, wherein, and the first electricity
Extremely public electrode, the second electrode is pixel electrode；Or, the first electrode is pixel electrode,
Second electrode is public electrode.So, when making above-mentioned array base palte, can be at substrate base
Make transparent conductive film and metallic film on plate successively, and use a mask plate to lead transparent
Conductive film and metallic film are patterned, and form the first electrode layer and the grid metal level of said structure,
I.e. can make the first electrode and grid, compared to prior art by a patterning processes simultaneously
In need to make grid, pixel electrode and public electrode respectively by three patterning processes, this
Array base palte that invention provides and preparation method thereof uses composition work when can reduce making array base palte
The number of times of skill.
Accompanying drawing explanation
Fig. 1 is the structural representation one of array base palte in prior art；
The structural representation one of a kind of array base palte that Fig. 2 provides for the embodiment of the present invention；
The structural representation two of a kind of array base palte that Fig. 3 provides for the embodiment of the present invention；
The structural representation three of a kind of array base palte that Fig. 4 provides for the embodiment of the present invention；
The structural representation four of a kind of array base palte that Fig. 5 provides for the embodiment of the present invention；
The structural representation five of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention；
The structural representation six of a kind of array base palte that Fig. 7 provides for the embodiment of the present invention；
Fig. 8 is the structural representation two of array base palte in prior art；
The manufacturing process schematic diagram one of a kind of array base palte that Fig. 9 provides for the embodiment of the present invention；
The manufacturing process schematic diagram two of a kind of array base palte that Figure 10 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, to the technical side in the embodiment of the present invention
Case is clearly and completely described, it is clear that described embodiment is only the present invention one
Divide embodiment rather than whole embodiments.
It addition, term " first ", " second " are only used for describing purpose, and it is not intended that
Indicate or imply relative importance or the implicit quantity indicating indicated technical characteristic.Thus,
Define " first ", the feature of " second " can express or implicitly include one or
More this feature.In describing the invention, except as otherwise noted, the implication of " multiple "
It is two or more.
Embodiments of the invention provide a kind of array base palte 100, as in figure 2 it is shown, include:
First electrode layer, this first electrode layer includes: retain pattern 101 and the first electrode 102；
Being positioned at the grid metal level on this first electrode layer, this grid metal level includes: be positioned at this reservation
The grid metal pattern 103 directly contacted on pattern 101 and with this reservation pattern 101；
The second electrode lay, this second electrode lay includes: be oppositely arranged with this first electrode 102
Second electrode 104, wherein, this first electrode 102 is public electrode, and this second electrode is 104
Pixel electrode；Or, this first electrode 102 is pixel electrode, and this second electrode 104 is public
Common electrode.
Exemplary, for the array base palte 100 of bottom grating structure, still as in figure 2 it is shown, this array
Substrate 100 also includes: be positioned at the gate insulation layer 14 on this grid metal level；It is positioned at this gate insulation layer
Source and drain metal level on 14, this source and drain metal level includes: source electrode 105 and drain electrode 106, data
Line 107；And, it is positioned at the passivation layer 16 on this source and drain metal level；Wherein, above-mentioned second electricity
Pole layer is positioned on this passivation layer 16.
It can be seen that when making above-mentioned array base palte 100, can on underlay substrate successively
Make transparent conductive film and metallic film, and use mask plate to transparent conductive film and
Metallic film is patterned, thus forms the first electrode layer and the grid metal level of said structure, i.e.
The first electrode 102 and grid can be made, compared to existing skill by a patterning processes simultaneously
Art needs make grid, pixel electrode and public electrode respectively by three patterning processes,
Array base palte that the present invention provides and preparation method thereof uses composition when can reduce making array base palte
The number of times of technique.
Meanwhile, in the array base palte 100 that the embodiment of the present invention provides, due to the first electrode 102
And it is provided with passivation layer 16 and gate insulation layer 14 two-layer altogether between the second electrode 104, therefore,
Without needing in the prior art to reduce the first electrode and the by increasing the thickness of passivation layer
Store electric capacity between two electrodes, thus reduce the thickness of array base palte.
Exemplary, in a kind of possible design, as it is shown on figure 3, arrange in passivation layer 16
The first via 201, drain electrode 106 is had to be electrically connected with the second electrode 104 by the first via 201,
Making the second electrode 104 is pixel electrode.
Exemplary, in alternatively possible design, as shown in Figure 4, the second electrode lay is also
Including: connecting pattern 108；Wherein, in passivation layer 16, it is provided with the 3rd via 202, connects
Pattern 108 is connected with drain electrode 106 by the 3rd via 202；Now, array base palte 100 is also
Having the 4th via 203 running through passivation layer 16 and gate insulation layer 14, connecting pattern 108 is passed through
4th via 203 is connected with the first electrode 102 so that the first electrode 102 is pixel electrode.
But, in array base palte 100 as shown in Figure 4, owing to comprising connection the 3rd via
202 and the 4th connecting pattern 108 of via 203, cause the area that via area is set to increase,
So that the aperture opening ratio of array base palte 100 reduces.
To this, the embodiment of the present invention proposes a kind of prioritization scheme on the basis of Fig. 4, such as Fig. 5
Shown in, it being provided with the second via 204 in gate insulation layer 14, drain electrode 106 is by the second via 204
Electrically connect with the first electrode 102 so that the first electrode 102 is pixel electrode.
So, compared with the array base palte 100 shown in Fig. 4, at the array base palte shown in Fig. 5
In 100, owing to individually gate insulation layer 14 1 layers being performed etching, formed in gate insulation layer 14
Second via 204, can reduce the area of via area, thus reduce array substrate 100 opening
The impact of rate.
It addition, in the array base palte 100 shown in arbitrary in Fig. 2-Fig. 5, as shown in Figure 6,
The second electrode lay also includes: the bucking electrode 109 being oppositely arranged with data wire 107, now, and screen
Cover electrode 109 for shield data wire 107 surrounding formed electric field, prevent from causing because of this electric field
Light leakage phenomena.
Further, based on any one array base palte 100 shown in Fig. 2-Fig. 5, as it is shown in fig. 7,
The second electrode lay also includes: signal accesses pattern 110；Source and drain metal level also includes: conductive pattern
111；Grid metal pattern 103 includes grid 112 and public electrode wire 113；Wherein, signal connects
Enter pattern 110 and electrically connect with conductive pattern 111 by running through the via of passivation layer 16, conduction figure
Case 111 electrically connects with public electrode wire 113 by running through the via of gate insulation layer 14.
Exemplary, still as it is shown in fig. 7, signal access pattern 110 specifically includes: first connects
Enter sub pattern 211 and second and access sub pattern 212；Wherein, the first access sub pattern 211 is passed through
The 5th via 205 running through passivation layer electrically connects with conductive pattern 111, and second accesses sub pattern
212 electrically connect with conductive pattern 111 by running through the 6th via 206 of passivation layer.
And in prior art, based on the array base palte shown in Fig. 1, its signal access pattern 110,
The set-up mode of conductive pattern 111 and public electrode wire 113 as shown in Figure 8, wherein, if
It is equipped with the via C running through gate insulation layer 14 and passivation layer 16, and runs through the mistake of passivation layer 16
Hole D and via E, conductive pattern 111 accesses pattern 110 by via D and via E with signal
Connection, public electrode wire 113 accesses pattern 110 by via C with signal and connects, now,
Owing to being provided with three vias, i.e. via C, via D and via E, thus cause via area
In territory, signal accesses the area increase of pattern 110, reduces the aperture opening ratio of array base palte 100.
And in the array base palte 100 provided in embodiment of the present invention Fig. 7, forming gate insulation
During layer 14, via can be made by etching technics so that conductive pattern 111 is by this via
Electrically connect with public electrode wire 113, the 5th via 205 and the only need to be set in passivation layer 16
Six vias 206, just can make signal access pattern 110 by conductive pattern 111 and public electrode
Line 113 electrically connects, thus decreased signal access pattern 110 area, thus reduce right
The impact of array base palte 100 aperture opening ratio.
Further, embodiments of the invention also provide for the manufacture method of above-mentioned array base palte 100,
Including:
First, as it is shown in figure 9, make transparent conductive film 31 on underlay substrate 200 successively
With metallic film 32.This transparent conductive film 31 can be ITO (Indium Tin Oxides,
Tin indium oxide) etc. transparent conductive material.
And then, as shown in Figure 10, use a mask plate to transparent conductive film 31 and metal
After thin film 32 is exposed, develops and etches, the pattern that transparent conductive film 31 remains
Being the first electrode layer, the pattern that metallic film 32 remains is grid metal level.
Wherein, the first electrode layer includes: retain pattern 101 and the first electrode 102；Grid metal level
Including: it is positioned at the grid metal figure retaining on pattern 101 and directly contacting with reservation pattern 101
Case 103.
Such as, this grid metal pattern 103 can be made up of grid 112 and public electrode wire 113.
It should be noted that the first electrode 102 can be public electrode, now, with the first electricity
The second electrode that pole 102 is oppositely arranged is pixel electrode；Or, the first electrode 102 can be
Pixel electrode, now, the second electrode being oppositely arranged with the first electrode 102 is public electrode.
It can be seen that above-mentioned manufacture method only can make the by patterning processes simultaneously
One electrode 102 and grid 112, compared to needing in prior art by secondary patterning processes respectively
Making grid and the first electrode, array base palte that the present invention provides and preparation method thereof can reduce system
Make to use during array base palte the number of times of patterning processes, thus reduce complexity when making array base palte
Degree and cost of manufacture.
Follow-up, it is also possible to make above-mentioned gate insulation layer 14, source and drain metal level, passivation layer 16 respectively
And the second electrode lay.
Hereinafter, the concrete of array base palte 100 being respectively directed in above-mentioned Fig. 3-Fig. 5 provide is tied
Structure, elaborates the manufacture method of array base palte 100.
For array base palte 100 as shown in Figure 3, forming above-mentioned first electrode layer and grid metal
After Ceng, gate insulation layer 14 can be made on grid metal level, and then, on gate insulation layer 14
Making source and drain metal level by a patterning processes, this source and drain metal level includes: source electrode 105 He
Drain electrode 106, data wire 107；And then, source and drain metal level makes passivation layer 16, and,
In passivation layer 16, the first via 201, one end of the first via 201 is made by etching technics
It is connected with drain electrode 106, finally, passivation layer 16 makes the second electricity by a patterning processes
Pole layer, this second electrode lay includes: the second electrode 104 being oppositely arranged with this first electrode 102,
Now, the second electrode 104 is connected with the first via 201 so that the second electrode 104 and drain electrode
106 electrical connections, this second electrode 104 is pixel electrode, and this first electrode 102 is public electrode.
For array base palte 100 as shown in Figure 4, forming above-mentioned first electrode layer and grid metal
After Ceng, gate insulation layer 14 can be made on grid metal level, and then, on gate insulation layer 14
Making source and drain metal level by a patterning processes, this source and drain metal level includes: source electrode 105 He
Drain electrode 106, data wire 107；And then, source and drain metal level makes passivation layer 16, is being formed
After passivation layer 16, can be made respectively by twice etching technique and run through the 3rd of passivation layer 16
Via 202, and run through the 4th via 203 of passivation layer 16 and gate insulation layer 14, wherein,
One end of 3rd via 202 is connected with drain electrode 106, one end of the 4th via 203 and the first electricity
Pole 102 is connected, and owing to the degree of depth of the 4th via 203 is relatively big, therefore, is making the 4th via
The concentration of the etching liquid used when 203 is relatively big, and/or etch period is longer.Finally, blunt
Changing and make the second electrode lay by a patterning processes on layer 16, this second electrode lay includes: with
The second electrode 104 that this first electrode 102 is oppositely arranged, and connecting pattern 108, this connection
Pattern 108 is connected with the 3rd via 202 and the 4th via 203 simultaneously, so that drain electrode 106
It is electrically connected with the first electrode 102 by the 3rd via the 202, the 4th via 203 and connecting pattern 108
Connecing, now, this second electrode 104 is public electrode, and this first electrode 102 is pixel electrode.
For array base palte 100 as shown in Figure 5, forming above-mentioned first electrode layer and grid metal
After Ceng, gate insulation layer 14 can be made on grid metal level, after forming gate insulation layer 14,
The second via 204, the second via 204 can be made in gate insulation layer 14 by etching technics
One end be connected with the first electrode 102, and then, by a composition work on gate insulation layer 14
Skill makes source and drain metal level, and this source and drain metal level includes: source electrode 105 and drain electrode 106, data wire
107；Wherein, drain electrode 106 is connected with the other end of the second via 204, so that drain electrode 106
Electrically connect with the first electrode 102, follow-up, passivation layer can be made further on source and drain metal level
16, and then, passivation layer 16 makes the second electrode lay by a patterning processes, this is second years old
Electrode layer includes: the second electrode 104 being oppositely arranged with this first electrode 102, now, and second
Electrode 104 is public electrode, and the first electrode 102 is pixel electrode.
Further, based on any one manufacture method above-mentioned, above-mentioned the second electrode lay is being made
Time, the second electrode 104 and bucking electrode 109, bucking electrode 109 and data can be concurrently formed
Line 107 is oppositely arranged, and obtains array base palte 100 as shown in Figure 6, now, bucking electrode
109 for shielding the electric field that data wire 107 surrounding is formed, and prevents the light leak caused because of this electric field existing
As.
It addition, based on any one manufacture method above-mentioned, making array base as shown in Figure 7
During plate 100, when making source electrode 105 and drain electrode 106, conductive pattern 111 can be made simultaneously,
Now, source electrode 105 and drain electrode 106, data wire 107 and conductive pattern 111 constitute source and drain metal
Layer；Make the second electrode 104 time, can make simultaneously signal access pattern 110, such as,
First accesses sub pattern 211 and second accesses sub pattern 212, and, forming gate insulation layer
After 14, in gate insulation layer 14, make connection public electrode wire 113 by etching technics and pass
Lead the via of pattern 111, and after forming passivation layer 16, by etching technics at passivation layer
Make in 16 and connect conductive pattern 111 and the via of signal access pattern 110, so, outside
Voltage signal can access pattern 110 by signal and be transferred to public electrode wire 113, to drive public affairs
Common electrode and pixel electrode form electric field under the effect of external voltage signal, make array base palte with
Liquid crystal molecule between color membrane substrates deflects.
Further, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned array
Substrate 100.Wherein, described display device can be any display floater, it is also possible to for being integrated with
Any product with display function of display floater or parts, such as: liquid crystal panel, electronics
Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, number
Code-phase frame, navigator etc..
So far, the present invention provides a kind of array base palte and preparation method thereof, display device, wherein,
This array base palte includes: the first electrode layer, and this first electrode layer includes: retain pattern and first
Electrode；Being positioned at the grid metal level on this first electrode layer, this grid metal level includes: be positioned at reservation
The grid metal pattern directly contacted on pattern and with reservation pattern；And, the second electrode lay,
This second electrode lay includes: the second electrode being oppositely arranged with the first electrode, wherein, and the first electricity
Extremely public electrode, the second electrode is pixel electrode；Or, the first electrode is pixel electrode,
Second electrode is public electrode.So, when making above-mentioned array base palte, can be at substrate base
Make transparent conductive film and metallic film on plate successively, and use a mask plate to lead transparent
Conductive film and metallic film are patterned, and form the first electrode layer and the grid metal level of said structure,
I.e. can make the first electrode and grid, compared to prior art by a patterning processes simultaneously
In need to make grid, pixel electrode and public electrode respectively by three patterning processes, this
Array base palte that invention provides and preparation method thereof uses composition work when can reduce making array base palte
The number of times of skill.
In the description of this specification, specific features, structure, material or feature can be in office
What one or more embodiments or example combine in an appropriate manner.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is also
Being not limited to this, any those familiar with the art is at the technology model that the invention discloses
In enclosing, change can be readily occurred in or replace, all should contain within protection scope of the present invention.
Therefore, protection scope of the present invention should be as the criterion with scope of the claims.
Claims (10)
1. an array base palte, it is characterised in that including:
First electrode layer, described first electrode layer includes: retain pattern and the first electrode；
Being positioned at the grid metal level on described first electrode layer, described grid metal level includes: be positioned at institute
State and retain the grid metal pattern directly contacted on pattern and with described reservation pattern；
The second electrode lay, described the second electrode lay includes: be oppositely arranged with described first electrode
Second electrode, wherein, described first electrode is public electrode, and described second electrode is pixel electrode；
Or, described first electrode is pixel electrode, and described second electrode is public electrode.
Array base palte the most according to claim 1, it is characterised in that described second electrode
Layer is positioned at described grid metal layer, and described array base palte also includes:
It is positioned at the gate insulation layer on described grid metal level；
The source and drain metal level being positioned on described gate insulation layer, described source and drain metal level includes: source electrode
And drain electrode, data wire；
It is positioned at the passivation layer on described source and drain metal level；
Wherein, described the second electrode lay is positioned on described passivation layer.
Array base palte the most according to claim 2, it is characterised in that in described passivation layer
Being provided with the first via, described drain electrode is electrically connected with described second electrode by described first via,
Making described second electrode is pixel electrode.
Array base palte the most according to claim 2, it is characterised in that described gate insulation layer
Inside being provided with the second via, described drain electrode is electrically connected with described first electrode by described second via
Connect so that described first electrode is pixel electrode.
Array base palte the most according to claim 2, it is characterised in that
Described the second electrode lay also includes: connecting pattern；
Being provided with the 3rd via in described passivation layer, described connecting pattern passes through described 3rd via
It is connected with described drain electrode；
Described array base palte also has the 4th mistake running through described passivation layer and described gate insulation layer
Hole, described connecting pattern is connected with described first electrode by described 4th via so that described the
One electrode is pixel electrode.
6. according to the array base palte according to any one of claim 2-5, it is characterised in that institute
State the second electrode lay also to include: the bucking electrode being oppositely arranged with described data wire.
7. according to the array base palte according to any one of claim 1-5, it is characterised in that institute
State the second electrode lay also to include: signal accesses pattern, and described source and drain metal level also includes: conduction figure
Case, described grid metal pattern includes public electrode wire；
Wherein, described signal accesses pattern by running through the via of described passivation layer and described conduction
Pattern electrically connects, and described conductive pattern is by running through the via of described gate insulation layer and described common electrical
Polar curve electrically connects.
Array base palte the most according to claim 7, it is characterised in that described signal accesses
Pattern includes: first accesses sub pattern and second accesses sub pattern；
Described first accesses sub pattern by running through the 5th via of described passivation layer and described conduction
Pattern electrically connects, and described second accesses sub pattern by running through the 6th via and the institute of described passivation layer
State conductive pattern electrical connection.
9. a manufacture method for the array base palte as according to any one of claim 1-8, its
It is characterised by, including:
Underlay substrate makes transparent conductive film and metallic film successively, and use is once covered
Lamina membranacea forms the first electrode layer and grid metal level to described transparent conductive film and metallic film composition；
Wherein, described first electrode layer includes: retaining pattern and the first electrode, described grid metal level includes:
The grid metal pattern being positioned on described reservation pattern and directly contact with described reservation pattern；
Described method also includes: forming the second electrode lay, described the second electrode lay includes: with institute
State the second electrode that the first electrode is oppositely arranged；
Wherein, described first electrode is public electrode, and described second electrode is pixel electrode；Or
Person, described first electrode is pixel electrode, and described second electrode is public electrode.
10. a display device, it is characterised in that include as any one of claim 1-8
Described array base palte.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610481624.9A CN105870136A (en) | 2016-06-27 | 2016-06-27 | Array substrate, making method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610481624.9A CN105870136A (en) | 2016-06-27 | 2016-06-27 | Array substrate, making method thereof and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105870136A true CN105870136A (en) | 2016-08-17 |
Family
ID=56655348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610481624.9A Pending CN105870136A (en) | 2016-06-27 | 2016-06-27 | Array substrate, making method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105870136A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783737A (en) * | 2017-04-07 | 2017-05-31 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display panel, display device |
| CN106896602A (en) * | 2017-03-14 | 2017-06-27 | 上海中航光电子有限公司 | Array base palte, display panel, display device and preparation method |
| CN107919321A (en) * | 2017-11-22 | 2018-04-17 | 深圳市华星光电半导体显示技术有限公司 | FFS type thin-film transistor array base-plates and preparation method thereof |
| US10304866B1 (en) | 2017-11-22 | 2019-05-28 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | FFS type TFT array substrate and the manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208491A (en) * | 2013-02-25 | 2013-07-17 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
| CN203260582U (en) * | 2013-04-03 | 2013-10-30 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN103545252A (en) * | 2013-09-27 | 2014-01-29 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and liquid crystal display device |
| CN103698955A (en) * | 2013-12-13 | 2014-04-02 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, manufacturing method of array substrate and display device |
| CN103779357A (en) * | 2014-01-24 | 2014-05-07 | 京东方科技集团股份有限公司 | Array substrate, display device and array substrate manufacturing method |
-
2016
- 2016-06-27 CN CN201610481624.9A patent/CN105870136A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208491A (en) * | 2013-02-25 | 2013-07-17 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
| CN203260582U (en) * | 2013-04-03 | 2013-10-30 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN103545252A (en) * | 2013-09-27 | 2014-01-29 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and liquid crystal display device |
| CN103698955A (en) * | 2013-12-13 | 2014-04-02 | 京东方科技集团股份有限公司 | Pixel unit, array substrate, manufacturing method of array substrate and display device |
| CN103779357A (en) * | 2014-01-24 | 2014-05-07 | 京东方科技集团股份有限公司 | Array substrate, display device and array substrate manufacturing method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106896602A (en) * | 2017-03-14 | 2017-06-27 | 上海中航光电子有限公司 | Array base palte, display panel, display device and preparation method |
| CN106783737A (en) * | 2017-04-07 | 2017-05-31 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display panel, display device |
| CN106783737B (en) * | 2017-04-07 | 2020-02-21 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| CN107919321A (en) * | 2017-11-22 | 2018-04-17 | 深圳市华星光电半导体显示技术有限公司 | FFS type thin-film transistor array base-plates and preparation method thereof |
| US10304866B1 (en) | 2017-11-22 | 2019-05-28 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | FFS type TFT array substrate and the manufacturing method thereof |
| WO2019100495A1 (en) * | 2017-11-22 | 2019-05-31 | 深圳市华星光电半导体显示技术有限公司 | Ffs-type thin-film transistor array substrate and manufacturing method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3088951B1 (en) | Array substrate, preparation method thereof, motherboard comprising array substrate and display apparatus | |
| CN103676354B (en) | Electrode structure and preparation method, array base palte and preparation method and display device | |
| CN103268878B (en) | The manufacture method of tft array substrate, tft array substrate and display unit | |
| CN1573453B (en) | Display device and manufacturing method of the same | |
| CN105974690B (en) | A kind of mask plate, array substrate, display panel and display device | |
| CN105977261A (en) | Array substrate, liquid crystal display panel, and liquid crystal display device | |
| CN104049430B (en) | Array substrate, display device and manufacturing method of array substrate | |
| CN103915444B (en) | Array substrate, preparation method thereof and liquid crystal display panel | |
| CN104698706B (en) | A kind of array substrate and its manufacturing method, display device | |
| CN105870136A (en) | Array substrate, making method thereof and display device | |
| CN102945846B (en) | Array base palte and manufacture method, display unit | |
| CN104345511B (en) | Dot structure and its manufacture method, display panel | |
| CN106055160A (en) | Array substrate and manufacturing method thereof, display panel and display device | |
| CN106019679A (en) | Array substrate, manufacturing method, display panel and display device | |
| CN103698955A (en) | Pixel unit, array substrate, manufacturing method of array substrate and display device | |
| CN204028524U (en) | Display base plate and display device | |
| CN104795405B (en) | A kind of array base palte and preparation method thereof, display device | |
| CN106229310A (en) | Array base palte and preparation method thereof | |
| KR101431655B1 (en) | Electronic paper active substrate and method of forming the same and electronic paper display panel | |
| CN108417579A (en) | A kind of display base plate and its manufacturing method | |
| CN104766869A (en) | Array substrate and manufacturing method and display device thereof | |
| CN100504561C (en) | Pixel structure and its manufacturing method and multi-field vertical alignment LCD | |
| CN110112160B (en) | Array substrate, preparation method thereof and display device | |
| CN106876415B (en) | Thin film transistor array substrate and manufacturing method thereof | |
| CN105974699A (en) | Array substrate, manufacturing method thereof and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160817 |
|
| RJ01 | Rejection of invention patent application after publication |