CN104183219A - Scanning drive circuit and organic light-emitting displayer - Google Patents
Scanning drive circuit and organic light-emitting displayer Download PDFInfo
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- CN104183219A CN104183219A CN201410464972.6A CN201410464972A CN104183219A CN 104183219 A CN104183219 A CN 104183219A CN 201410464972 A CN201410464972 A CN 201410464972A CN 104183219 A CN104183219 A CN 104183219A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention provides a scanning drive circuit. In comparison with a traditional scanning drive circuit, fewer clock signals and fewer transistors are adopted, the reliability of the drive circuit can be greatly improved, and meanwhile the design cost and the production cost of the drive circuit are reduced. The invention further discloses an organic light-emitting displayer based on the scanning drive circuit.
Description
Technical field
The present invention relates to scan drive circuit field, particularly relate to a kind of scan drive circuit and organic light emitting display that is applied to turntable driving organic light emitting device pixel circuit.
Background technology
Organic light emitting display is that a kind of application Organic Light Emitting Diode (OLED) is as the display of luminescent device, compare present main flow flat panel display Thin Film Transistor-LCD (TFT-LCD), organic light emitting display has the advantages such as high-contrast, wide viewing angle, low-power consumption, volume be thinner, being expected to become the flat panel display of future generation after LCD, is one of the maximum technology that receives publicity in current flat panel display.
Traditional organic light emitting display comprise to data line provide the data driver of data-signal, successively wherein a road sweep trace provide the first scanner driver of sweep signal, successively to another road sweep trace provide sweep signal the second scanner driver, to the first scanner driver and the second scanner driver, provide clock signal and the time schedule controller of low and high level signal and the display unit of a plurality of pixels.The effect of the first scanner driver and the second scanner driver is that to produce successively the driving signal that offers display panel bright dark with the pixel of controlling in display panel.
Yet, because each cascade structure of the first traditional scanner driver and the second scanner driver comprises more input clock signal (at least 3) and has comprised a large amount of transistor (more than 10), the risk going wrong is thus corresponding increase also, the cost and risk of producing and designing is all higher, is difficult to guarantee the reliability of product.
Summary of the invention
Based on this, be necessary to provide a kind of scan drive circuit that can reduce clock signal and number of transistors.In addition, also provide a kind of organic light emitting display.
A kind of scan drive circuit, comprise exporting successively and select the first scanner driver of signal and export successively the second scanner driver transmitting, described the first scanner driver comprises a plurality of the first cascade structures, described the second scanner driver comprises a plurality of the second cascade structures, described the first cascade structure or/and each cascade structure in described the second cascade structure comprise: the first transistor, comprises and the sweep signal output terminal of last cascade structure or the connected input end of sweep signal input end, gate terminal and the output terminal being connected with the first clock end; Transistor seconds, comprises the gate terminal being connected with the output terminal of the first transistor, the input end being connected with second clock end and the output terminal being connected with sweep signal output terminal; The 3rd transistor, comprises the input end being connected with the first level end, the gate terminal and the output terminal that are connected with sweep signal output terminal; The 4th transistor, comprises the input end being connected with the 3rd transistorized output terminal, the gate terminal being connected with the first clock end and the output terminal being connected with second electrical level end; The 5th transistor, comprises the input end being connected with the first level end, the gate terminal being connected with the 3rd transistorized output terminal and the output terminal being connected with sweep signal output terminal; The 6th transistor, comprises the input end being connected with the first level end, the gate terminal and the output terminal that are connected with sweep signal output terminal; The 7th transistor, comprises the input end being connected with the 6th transistorized output terminal end, the gate terminal being connected with the first clock end and the output terminal being connected with second electrical level end; The 8th transistor, comprises the input end being connected with the first level end, the gate terminal being connected with sweep signal output terminal and the output terminal being connected with driving signal output part; The 9th transistor, comprises and the input end, the gate terminal being connected with the 6th transistorized output terminal that drive signal output part to be connected and the output terminal being connected with the 3rd level end; And be connected in the gate terminal of transistor seconds and the first electric capacity between output terminal.
Therein in an embodiment, the frequency of the signal that the signal that the first clock termination of described the first cascade structure and each cascade structure in described the second cascade structure is received is received with second clock termination is consistent, the signal that when signal of receiving when the first clock termination is high level, second clock termination is received is low level, and the signal that when signal of receiving when the first clock termination is low level, second clock termination is received is high level.
In an embodiment, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor are Thin Film Transistor (TFT) therein.
In an embodiment, between described the first level end and described the 6th transistorized gate terminal, be connected with the second electric capacity therein.
In an embodiment, between described second electrical level end and described the 9th transistorized gate terminal, be connected with the 3rd electric capacity therein.
In an embodiment, between described driving signal output part and described the 9th transistorized gate terminal, be connected with the 3rd electric capacity therein.
In an embodiment, described the 3rd level end and described second electrical level end are same level end therein.
In an embodiment, less than the magnitude of voltage of inputting from described second electrical level end from the magnitude of voltage of described the 3rd level end input therein.
In an embodiment, from the voltage of described the first level end input, being high level therein, is low level from the voltage of described second electrical level end and the input of the 3rd level end.
Above-mentioned scan drive circuit has only been used two clock signals and 9 transistors, all fewer than traditional scan drive circuit, can increase substantially the reliability of circuit, has also reduced design cost and production cost simultaneously.
A kind of organic light emitting display, comprise image element circuit, data driver and time schedule controller, also comprise above-mentioned scan drive circuit, the first clock end that described time schedule controller is described scan drive circuit, second clock end, sweep signal input end, the first level end, second electrical level end and the 3rd level end provide clock signal and low and high level signal, the driving signal output part of described scan drive circuit and the driving signal input of image element circuit are connected, and with output drive signal, drive image element circuit work.
Apply the organic light emitting display of above-mentioned scan drive circuit and used less transistor, therefore can increase substantially the reliability of product, also reduced product design costs and production cost simultaneously.
Accompanying drawing explanation
Fig. 1 is the module map of the first scanner driver of the scan drive circuit of the first embodiment;
Fig. 2 is the circuit diagram of one of them cascade structure of the first scanner driver described in Fig. 1;
Fig. 3 is the sequential chart of the part signal of the first scanner driver shown in Fig. 1;
Fig. 4 is the circuit diagram of one of them cascade structure of the first scanner driver of the scan drive circuit of the second embodiment;
Fig. 5 is the circuit diagram of one of them cascade structure of the first scanner driver of the scan drive circuit of the 3rd embodiment;
Fig. 6 is organic light emitting display circuit module figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.In instructions, for ease of understanding, quote signal port symbol and represent this signal below.
Embodiment 1
Please refer to Fig. 1 and Fig. 2, the present embodiment provides a kind of scan drive circuit.This scan drive circuit comprises exporting successively to be selected the first scanner driver of signal and exports successively the second scanner driver transmitting.The first scanner driver comprises a plurality of the first cascade structures, and the second scanner driver comprises a plurality of the second cascade structures.The first cascade structure is or/and each cascade structure in the second cascade structure can comprise following structure.In this embodiment, each cascade structure in the first cascade structure and the second cascade structure includes the first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, sweep signal input end IN, sweep signal output terminal OUT, the first clock end CKL1, second clock end CLK2, the first level end VGH, second electrical level end VGL1, the 3rd level end VGL2 and driving signal output part EM.
The first transistor M1 comprises and the sweep signal output terminal OUT of last cascade structure or the connected input end of sweep signal input end IN, gate terminal and the output terminal being connected with the first clock end CKL1.Transistor seconds M2 comprises the gate terminal being connected with the output terminal of the first transistor M1, the input end being connected with second clock end CKL2 and the output terminal being connected with sweep signal output terminal OUT.The 3rd transistor M3 comprises the input end being connected with the first level end VGH, the gate terminal and the output terminal that are connected with sweep signal output terminal OUT.The 4th transistor M4 comprises the input end being connected with the output terminal of the 3rd transistor M3, the gate terminal being connected with the first clock end CKL1 and the output terminal being connected with second electrical level end VGL1.The 5th transistor M5 comprises the input end being connected with the first level end VGH, the gate terminal being connected with the output terminal of the 3rd transistor M3 and the output terminal being connected with sweep signal output terminal OUT.The 6th transistor M6 comprises the input end being connected with the first level end VGH, the gate terminal and the output terminal that are connected with sweep signal output terminal OUT.The 7th transistor M7 comprises the input end being connected with the output terminal end of the 6th transistor M6, the gate terminal being connected with the first clock end CKL1 and the output terminal being connected with second electrical level end VGL1.The 8th transistor M8 comprises the input end being connected with the first level end VGH, the gate terminal being connected with sweep signal output terminal OUT and the output terminal being connected with driving signal output part EM.The 9th transistor M9 comprises and the input end, the gate terminal being connected with the output terminal of the 6th transistor M6 that drive signal output part EM to be connected and the output terminal being connected with the 3rd level end VGL2.
The grid of the first transistor M1, the grid short circuit of the grid of the 4th transistor M4 and the 7th transistor M7, second utmost point of the first transistor M1, the first end short circuit of the grid of transistor seconds M2 and the first capacitor C 1, second utmost point of transistor seconds M2, the grid of the 3rd transistor M3, second utmost point of the 5th transistor M5, the grid of the 6th transistor M6, the grid of the 8th transistor M8, the second end short circuit of the first end of the first capacitor C 1 and the second capacitor C 2, first utmost point of the 3rd transistor M3, first utmost point of the 5th transistor M5, first utmost point of the 6th transistor M6, the first end short circuit of first utmost point of the 8th transistor M8 and the second capacitor C 2, first utmost point of second utmost point of the 3rd transistor M3 and the 4th transistor M4 and the grid short circuit of the 5th transistor M5, second utmost point of the 4th transistor M4, the second end short circuit of second utmost point of the 7th transistor M7 and the 3rd capacitor C 3, second utmost point of the 6th transistor M4, first utmost point of the 7th transistor M7, the grid short circuit of the first end of the 3rd capacitor C 3 and the 9th transistor M9, the first utmost point short circuit of second utmost point of the 8th transistor M8 and the 9th transistor M9.
First utmost point of the first transistor M1 connects sweep signal input end IN, second utmost point of transistor seconds M2 connects sweep signal output terminal OUT, the grid of the first transistor M1 connects the first clock end CLK1, first utmost point of transistor seconds M2 connects second clock end CLK2, first utmost point of the 3rd transistor M3 connects the first level end VGH, second utmost point of the 4th transistor M4 connects second electrical level end VGL1, second utmost point of the 9th transistor M9 connects the second low level signal input end VGL2, and second utmost point of the 8th transistor M8 connects driving signal output part EM.
High level signal is inputted (voltage that can be understood as the first level end VGH input is malleation) from the first level end VGH, the first clock signal is inputted from the first clock end CLK1, second clock signal is inputted from second clock end CLK2, sweep signal is inputted from sweep signal input end IN, the first low level signal is from second electrical level end VGL1 input (voltage that can be understood as second electrical level end VGL1 input is negative pressure), the second low level signal is inputted (voltage that can be understood as the second low level signal input end VGL2 input is negative pressure) from the second low level signal input end VGL2, drive signal from driving signal output part EM output, output scanning signal is exported from sweep signal output terminal OUT.
The first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9 are field effect transistor, are preferably P channel type field effect transistors.Be more specifically Thin Film Transistor (TFT) (TFT), be preferably P channel-type Thin Film Transistor (TFT).
Because the first scanner driver of this scan drive circuit and the cascade structure of the second scanner driver include nine transistors, and only need use two clock signals, the number of transistors that this scan drive circuit is used can be less, therefore the reliability of product be can increase substantially, product design costs and production cost also reduced simultaneously.The existence of the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9 can make this scan drive circuit driving signal output part EM output more accurately and reliably.
It should be noted that, if sweep signal output terminal OUT termination has load capacitance, the second capacitor C 2 and the 3rd capacitor C 3 also can be omitted herein.The current value that the second capacitor C 2 and the 3rd capacitor C 3 can reduce the first level end VGH, second electrical level end VGL1, the 3rd level end VGL2 is set in this embodiment.
First scanner driver of take below is specifically introduced the annexation of a plurality of cascade structures as example.
The first scanner driver comprises N cascade structure, and the sweep signal output terminal of first order cascade structure connects the sweep signal input end of second level cascade structure, the sweep signal output terminal of second level cascade structure connects the sweep signal input end of third level cascade structure ... the sweep signal output terminal of N-1 level cascade structure connects the sweep signal input end of N level cascade structure.
The second clock end short circuit of the first clock end of the cascade structure of odd level and the cascade structure of even level, the first clock end short circuit of the second clock end of the cascade structure of odd level and the cascade structure of even level.
The first clock signal clk 1 is from the first clock end input of first order cascade structure, and second clock signal CLK2 is from the second clock end input of first order cascade structure.
The driving signal output part of cascade structures at different levels respectively output drive signal EM.1, EM.2, EM.3 ... EM.N is luminous with the image element circuit of driving organic light emitting display to the image element circuit of a plurality of organic light emitting display.
Below in conjunction with accompanying drawing, the course of work of circuit in a scan period T described, incorporated by reference to Fig. 1, Fig. 2 and Fig. 3.Wherein, from the voltage of the first level end VGH input, be high level, from the voltage of second electrical level end VGL1 and the 3rd level end VGL2 input, be low level.The frequency of the signal that the signal that the first clock end CLK1 of the first cascade structure and each cascade structure in the second cascade structure receives receives with second clock end CLK2 is consistent, the signal that when signal receiving as the first clock end CLK1 is high level, second clock end CLK2 receives is low level, the signal that when signal receiving as the first clock end CLK1 is low level, second clock end CLK2 receives is high level, this is equivalent to the first clock end CLK1 of each cascade structure in the first cascade structure and the second cascade structure and the single spin-echo of the signal that second clock end CLK2 receives.For ease of understanding, quote signal port symbol and represent this signal, sweep signal is that IN, output scanning signal are that OUT, the first clock signal are that CKL1, second clock signal are that CLK2, driving signal are EM.Quote element label symbol and distinguish different elements, for example the first transistor M1 is transistor M1, and the first capacitor C 1 is capacitor C 1.
In first clock period t1: the clock signal (being CLK1) that the first clock end CLK1 receives is low level, all conductings of transistor M1, M4, M7, IN is low level (capacitor C 1 charging), the clock signal (being CLK2) that second clock end end CLK2 receives is high level, thereby transistor M2 conducting, output scanning signal OUT is high level; Thereby the grid of transistor M7 conducting transistor M9 is also low level, M9 conducting, EM is low level.
In second clock period t2: CLK1 is high level, and transistor M1, M4, M7 end, capacitor C 1 electric discharge, CLK2 is low level.Due to the coupling of capacitor C 1, thereby the grid of transistor M2 continues as lower low level, makes M2 conducting, M3 conducting, M5 cut-off simultaneously, thus OUT is low level; So M2 conducting transistor M6 and all conductings of M8, and transistor M9 cut-off, thereby EM is high level.
In the 3rd clock period t3: CLK1 is low level, CLK2 is high level.All conductings of transistor M1, M4, M7, IN is high level, thus M2 cut-off; Thereby M4 conducting M5 conducting (capacitor C 2 chargings), OUT is high level; Thereby the grid of transistor M7 conducting transistor M9 is also low level (capacitor C 3 chargings), M9 conducting, EM is low level.
In the 4th clock period t4: CLK1 is high level, CLK2 is low level, and IN is high level.Transistor M1, M2, M4, M7 end, thereby M3, M5 end, capacitor C 2 electric discharges, thus OUT is high level; Capacitor C 3 electric discharges, thereby M9 conducting, EM is low level.
So, OUT is high level within remaining time scan period, EM is low level within remaining time scan period, has realized the output that drives signal EM, and the passing of a clock signal of sweep signal IN (OUT passes a clock period than IN backward).
OUT passes a clock period than IN backward, and according to the mode of oem character set, be connected cascade structures at different levels with CLK2 due to CLK1, and CLK1 and CLK2 are that low and high level is just staggered, realized the synchronous passing of CLK1, CLK2 and OUT, thus every one-level cascade structure can export required driving signal (EM.1, EM.2, EM.3 ... EM.N).
Above-mentioned scan drive circuit has only been used two clock signals and 9 transistors, all fewer than traditional scan drive circuit, can increase substantially the reliability of circuit, has also reduced design cost and production cost simultaneously.
Embodiment 2
Please refer to Fig. 4, in the present embodiment, the first low level signal (VGL1) and the second low level signal (VGL2) are same low level signal, the second low level signal input end VGL2 connects second electrical level end VGL1, be equivalent to second of the 9th transistor M9 and extremely directly connect second electrical level end VGL1, now the first low level signal (VGL1) is identical with the magnitude of voltage of the second low level signal (VGL2) input.In circuit operational process, when the 7th transistor M7 conducting, the grid of the 9th transistor M9 is the low level vgl1+Vth (magnitude of voltage of vgl1 the first low level signal simultaneously, for Vth is the threshold voltage absolute value of P channel-type Thin Film Transistor (TFT)), so the 9th transistor M9 conducting, now the source electrode of the 9th transistor M9 is also low level (vgl1), the grid and the drain short circuit that are equivalent to the 9th transistor M9, the 9th transistor M9 forms diode and connects, so the source electrode output voltage of the 9th transistor M9 is vgl1+Vth, that just caused driving signal than required vgl1 height Vth.So, in order to make to drive the driving signal of signal output part EM output, be vgl1, in other embodiments, in driving process, the magnitude of voltage of the second low level signal (vgl2) is less than the magnitude of voltage (vgl1) of the first low level signal, is preferably the magnitude of voltage (vgl2) of the second low level signal than the little Vth of magnitude of voltage (vgl1) of the first low level signal.
It should be noted that, if sweep signal output terminal OUT termination has load capacitance, the second capacitor C 2 can be omitted, but the 3rd capacitor C 3 can not omit, and the 3rd capacitor C 3 effects are to stablize the grid voltage of the 9th transistor M9.
First clock period t in a scan period T of sweep signal IN is low level signal, and all the other times are high level signal; When sweep signal IN is low level signal, the first clock signal clk 1 is also low level signal.The first clock signal clk 1 is consistent with second clock signal CLK2 frequency, when the first clock signal clk 1 is high level, second clock signal CLK2 is low level, when the first clock signal clk 1 is low level, second clock signal CLK2 is high level, the low and high level of the first clock signal clk 1 and second clock signal CLK2 is just staggered, and first sweep signal IN is synchronously low level with the first clock signal clk 1 in a scan period T in first clock period t.
Embodiment 3
The rapid high level that in the present embodiment, can improve by only changing the connected mode of the 3rd capacitor C 3 output signal EM is changed.Specifically change into, the 3rd capacitor C 3 is connected in and drives between signal output part EM and the gate terminal of the 9th transistor M9, sees Fig. 5.
It should be noted that, if sweep signal output terminal OUT termination has load capacitance, the second capacitor C 2 can be omitted, but the 3rd capacitor C 3 can not omit, and the 3rd capacitor C 3 plays positive feedback effect.
In circuit operational process, when first clock period, t1 jumped to second clock period t2, utilize the 3rd capacitor C 3 both end voltage saltus step and positive feedback effects, output signal EM has become rapidly high level from low level.When second clock period t2 jumps to the 3rd clock period t3, utilize the 3rd capacitor C 3 both end voltage saltus step and positive feedback effects, output signal EM has become rapidly low level from high level.In the present embodiment, adopt the 3rd capacitor C 3 to play the effect of positive feedback, make to export low and high level more stable, therefore can improve load capacity and the low and high level transfer capability of driving circuit, export high and low level and more approach power level.
Please refer to Fig. 6, the invention provides a kind of organic light emitting display, it comprises above-described embodiment 1 or embodiment 2 or the scan drive circuit of embodiment 3 and the image element circuit of a plurality of organic light emitting display 112.Wherein, scan drive circuit comprises the first scanner driver 110 and the second scanner driver 116.The driving signal output part of the cascade structure of every one-level in the first scanner driver 110 (EM.1, EM.2, EM.3 ... EM.N) be connected with the driving signal input of the image element circuit 112 of organic light emitting display respectively, with output drive signal respectively (EM.1, EM.2, EM.3 ... EM.N) drive the image element circuit 112 that has organic light emitting display.
This organic light emitting display also comprises data driver 114 and time schedule controller 118.The image element circuit 112 that data driver 114 is respectively organic light emitting display provides data-signal, the image element circuit 112 that the second scanner driver 116 is organic light emitting display provides sweep signal, the first clock end, second clock end, sweep signal input end, the first level end, second electrical level end and the 3rd level end that time schedule controller 118 is the first scanner driver 110 and the second scanner driver 116 provide clock signal and low and high level signal, and ELVDD provides power supply signal for whole image element circuits 112 of organic light emitting display.
Apply the organic light emitting display of above-mentioned scan drive circuit, can increase substantially the reliability of product, also reduced product design costs and production cost simultaneously.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a scan drive circuit, comprise exporting successively and select the first scanner driver of signal and export successively the second scanner driver transmitting, described the first scanner driver comprises a plurality of the first cascade structures, described the second scanner driver comprises a plurality of the second cascade structures, it is characterized in that, described the first cascade structure or/and each cascade structure in described the second cascade structure comprise:
The first transistor, comprises and the sweep signal output terminal of last cascade structure or the connected input end of sweep signal input end, gate terminal and the output terminal being connected with the first clock end;
Transistor seconds, comprises the gate terminal being connected with the output terminal of the first transistor, the input end being connected with second clock end and the output terminal being connected with sweep signal output terminal;
The 3rd transistor, comprises the input end being connected with the first level end, the gate terminal and the output terminal that are connected with sweep signal output terminal;
The 4th transistor, comprises the input end being connected with the 3rd transistorized output terminal, the gate terminal being connected with the first clock end and the output terminal being connected with second electrical level end;
The 5th transistor, comprises the input end being connected with the first level end, the gate terminal being connected with the 3rd transistorized output terminal and the output terminal being connected with sweep signal output terminal;
The 6th transistor, comprises the input end being connected with the first level end, the gate terminal and the output terminal that are connected with sweep signal output terminal;
The 7th transistor, comprises the input end being connected with the 6th transistorized output terminal end, the gate terminal being connected with the first clock end and the output terminal being connected with second electrical level end;
The 8th transistor, comprises the input end being connected with the first level end, the gate terminal being connected with sweep signal output terminal and the output terminal being connected with driving signal output part;
The 9th transistor, comprises and the input end, the gate terminal being connected with the 6th transistorized output terminal that drive signal output part to be connected and the output terminal being connected with the 3rd level end;
And be connected in the gate terminal of transistor seconds and the first electric capacity between output terminal.
2. scan drive circuit according to claim 1, it is characterized in that, the frequency of the signal that the signal that the first clock termination of described the first cascade structure and each cascade structure in described the second cascade structure is received is received with second clock termination is consistent, the signal that when signal of receiving when the first clock termination is high level, second clock termination is received is low level, and the signal that when signal of receiving when the first clock termination is low level, second clock termination is received is high level.
3. scan drive circuit according to claim 2, it is characterized in that, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor are Thin Film Transistor (TFT).
4. scan drive circuit according to claim 1, is characterized in that, between described the first level end and described the 6th transistorized gate terminal, is connected with the second electric capacity.
5. according to the scan drive circuit described in arbitrary claim in claim 1 to 4, it is characterized in that, between described driving signal output part and described the 9th transistorized gate terminal, be connected with the 3rd electric capacity.
6. according to the scan drive circuit described in arbitrary claim in claim 1 to 4, it is characterized in that, between described second electrical level end and described the 9th transistorized gate terminal, be connected with the 3rd electric capacity.
7. scan drive circuit according to claim 6, is characterized in that, described the 3rd level end and described second electrical level end are same level end.
8. scan drive circuit according to claim 6, is characterized in that, less than the magnitude of voltage of inputting from described second electrical level end from the magnitude of voltage of described the 3rd level end input.
9. scan drive circuit according to claim 6, is characterized in that, from the voltage of described the first level end input, is high level, from the voltage of described second electrical level end and the input of the 3rd level end, is low level.
10. an organic light emitting display, comprise image element circuit, data driver and time schedule controller, it is characterized in that, also comprise the scan drive circuit as described in arbitrary claim in claim 1 to 9, described time schedule controller is the first clock end of described scan drive circuit, second clock end, sweep signal input end, the first level end, second electrical level end and the 3rd level end provide clock signal and low and high level signal, the driving signal output part of described scan drive circuit and the driving signal input of image element circuit are connected, with output drive signal, drive image element circuit work.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410464972.6A CN104183219B (en) | 2013-12-30 | 2014-09-12 | Scanning drive circuit and organic light-emitting displayer |
| EP14876723.9A EP3091532B1 (en) | 2013-12-30 | 2014-12-29 | Scanning drive circuit and organic light-emitting display |
| KR1020167020703A KR101878380B1 (en) | 2013-12-30 | 2014-12-29 | Scanning drive circuit and organic light-emitting display |
| JP2016543693A JP6316437B2 (en) | 2013-12-30 | 2014-12-29 | Scan driving circuit and organic light emitting display device |
| US15/107,676 US10013919B2 (en) | 2013-12-30 | 2014-12-29 | Scanning drive circuit and organic light-emitting display |
| PCT/CN2014/095370 WO2015101261A1 (en) | 2013-12-30 | 2014-12-29 | Scanning drive circuit and organic light-emitting display |
| TW103146184A TWI534781B (en) | 2013-12-30 | 2014-12-30 | Scan drive circuit and organic light shower display |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310744988.8 | 2013-12-30 | ||
| CN201310744988 | 2013-12-30 | ||
| CN2013107449888 | 2013-12-30 | ||
| CN201410464972.6A CN104183219B (en) | 2013-12-30 | 2014-09-12 | Scanning drive circuit and organic light-emitting displayer |
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| Publication Number | Publication Date |
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| CN104183219A true CN104183219A (en) | 2014-12-03 |
| CN104183219B CN104183219B (en) | 2017-02-15 |
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| CN201410464972.6A Active CN104183219B (en) | 2013-12-30 | 2014-09-12 | Scanning drive circuit and organic light-emitting displayer |
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| Country | Link |
|---|---|
| US (1) | US10013919B2 (en) |
| EP (1) | EP3091532B1 (en) |
| JP (1) | JP6316437B2 (en) |
| KR (1) | KR101878380B1 (en) |
| CN (1) | CN104183219B (en) |
| TW (1) | TWI534781B (en) |
| WO (1) | WO2015101261A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2017503208A (en) | 2017-01-26 |
| CN104183219B (en) | 2017-02-15 |
| JP6316437B2 (en) | 2018-04-25 |
| US20160321999A1 (en) | 2016-11-03 |
| WO2015101261A1 (en) | 2015-07-09 |
| TWI534781B (en) | 2016-05-21 |
| EP3091532A1 (en) | 2016-11-09 |
| KR101878380B1 (en) | 2018-07-13 |
| KR20160104044A (en) | 2016-09-02 |
| TW201528241A (en) | 2015-07-16 |
| EP3091532A4 (en) | 2017-08-30 |
| EP3091532B1 (en) | 2020-04-08 |
| US10013919B2 (en) | 2018-07-03 |
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Denomination of invention: Scanning driving circuit and organic light emitting display Effective date of registration: 20201221 Granted publication date: 20170215 Pledgee: Xin Xin Finance Leasing Co.,Ltd. Pledgor: Kunshan New Flat Panel Display Technology Center Co.,Ltd.|KunShan Go-Visionox Opto-Electronics Co.,Ltd. Registration number: Y2020980009652 |