TWI380275B - Shift register - Google Patents

Description

1380275

TW4067PA IX. Description of the invention: [Technical field to which the invention pertains] The invention relates to a type of shift register, and particularly relates to a charge having a έ έ 雷 雷 、,,,, The storage capacity is used to perform the level shift control of the shift register of the level control circuit. [Prior Art] In the current era of rapid technological development, liquid crystal displays have been used in electronic display products such as televisions, computer screens, notebook computers, mobile phones or personal digital assistants. The liquid crystal display includes a data driver, a scan driver (Scan DHver), and a liquid crystal display panel, wherein the liquid crystal display panel has a pixel array and is scanned and driven. The device is configured to sequentially open corresponding pixel columns in the pixel array to transmit the pixel data outputted by the data driver to the pixels, thereby displaying the image to be displayed. Today's technology mostly uses a Shift Register to implement a scan driver that can sequentially turn on the corresponding pixel columns in the pixel array. Please refer to Fig. 1, which shows a circuit diagram of a conventional shift register unit. The shift temporary unit SR(n) generates a level control signal VC(n) by a push-up effect (B〇〇tstrapping). Control signal vC(n) (the level is substantially greater than or equal to the level VDD-Vth, wherein the level VDD is, for example, the high voltage level of the shift register unit SR(n), and vth is the threshold voltage of the transistor TA The transistor TA responds to the control signal vc(n) to rotate the high-order timing signal ckz as the scan signal SC(n), wherein the high level of the timing signal CKZ is 6 丄275

TW4067PA is at voltage level VDD. However, the operation of the conventional shift register unit SR (nM^, using the control signal VC(n) to control the transistors TA and TB, so that the control signal VC(n) is driven to a higher load, resulting in control The signal ¥(:(11) has a lower level. For example, the level of the control signal vc(n) is lower than the level VDD-Vth. This will cause the scan signal sc(n) to be in position. The accuracy is lower than the high voltage level VDD, which causes the level of the scanning signal sc(n) to be too low, and the display quality of the liquid crystal display is lowered. In addition, the aspect ratio of the transistor TB is about the length of the transistor Tc. Ten times the width ratio, and the transistor tc is biased into a diode (Diode). Thus, the inverter legs formed by the transistors TC and TB can be inverted in response to the control signal VC(n). However, since the length and width of the electric a-body TC are relatively small, it is required to withstand the transistor and generate a large current when it is turned on. This will cause the transistor TC to generate a bad The bit register unit generates a malfunction and the life expectancy of the liquid crystal display is again. How to design a long life level control It is one of the directions in the industry to improve the service life of the liquid crystal display and its quality. 〃 【Contents】 Traditionally, a shift register (brain-deletion) is compared. The shift register provided by the invention can reduce the circuit load required for the control signal, shorten the control signal VC (8) level shift, and avoid the position of the SC(n) due to the control signal 7 1380275

TW4067PA VC (8) bit of the life of the money, the error 4, extended shift smart display has a better display picture ^ quality out of the liquid crystal root of the shift register" invention proposed _ kind of "storage register, including : Early 兀 'shift register unit for each stage / temporary storage: circuit, circuit and level control 2 = power up:, level: ΓΓ:: enable the level control scan signal is equal to No.:: Responding to the news. The level pull-down circuit responds to the second control sequence. The scan signal is equal to the first power house. :Α This level control level and the second control level enable the enable level and the non-enable level. The level control circuit returns the ,, the enable level and the non-enable level of the input signal. The fifth signal is the non-enabled level and the enable level. In order to make the above-mentioned contents of the present invention more obvious and easy to understand, the following is a detailed description of the present invention, and is described in detail with reference to the following drawings: [Embodiment] The shifting of the following various embodiments Each shift register unit in the shift register drives the transistors in the shift temporary storage unit with an input signal. The transistor in each stage of the shift register unit may be an amorphous thin film transistor (Amorphous TFT), a polycrystalline silicon transistor (Poly-silicon TFT) or an n-type gold oxide half (Metal Oxide Semiconductor). , MOS) transistor. 8 1380275 * * r TW4067PA 'First embodiment The shift register in this embodiment is applied to the one-side scan drive. The liquid crystal display is shown in the embodiment of the present invention. 10 includes data driver 12, scan. Dynamic 14 and display panel 16. The data driver 12 is configured to provide the data signals SD(1) to SD(m) to the display panel 16 = scan drive ϋ 14 via the m lines* of the feed lines 11 for providing the scans sc(1) to sc(8) to the display panel via the n scan lines 13. 16. The display panel 16 includes an array of texels, wherein each of the η 昼 al al al al al an an an an an an an an SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC Among them, the claw is a natural number. In the present embodiment, the scan driver 14 has, for example, a shift register 24 in which the n-stage shift register unit branches to provide scan signals SC(1) to SC(n). Next, the shift register % is further explained. °月参, in the third figure, which shows a block diagram of the shift temporarily in accordance with an embodiment of the present invention. When the shift register 24 includes the n-stage shift register units S(1) to S(8)', the scan signals sc(1) to sc(n) are not output. Each of the level register units s(1)~s(8) includes an input terminal IN, an output terminal (10) = RT, an NT1, a timing terminal C1, and a timing terminal c2. The input terminal IN of the shift register unit ^S(l) receives the start signal STV, and the output terminal 〇υτ inputs the signal SC(1). The input terminals of the shift register units S(2) to S(8) respectively receive the output terminal 则1 of the stage-level shift register; the output signals SC(1)~SC(nl)' output of the output buffer 〇υτ outputs scan signals SC(2) to SC(n), respectively. 9 1380275 • k

The timing of the odd-numbered shift register unit S(1), S(3), ...,]) of the TW4067PA shift register singles (1) to S(8) receives the timing signal CLK, and the even-order shift The timing terminal C1 of the bit register unit s (7), s (4), and (4) receives the timing signal CLKB. The timing signal CLKB is essentially the inverted signal of the timing signal CLK. The scan signals SC(2)~SC(n) rotated by the shift register unit s(7)~s(8) are further outputted to the control terminal RTe shift temporary storage of the shift register unit S(l)~S(nl) The units s(1) to (4) have similar structures and operations, for example, and then the shift register unit s (1) shift register unit s (1) is taken as an example to the shift register unit S (l) The operation of ~s(8) is explained. The towel, j is a natural number less than or equal to η. Please refer to Figure 4 for the detailed circuit diagram of the shift register unit in Figure 3. The memory unit s(1) includes a driving circuit, a shifting, level control circuit 204, a level rising circuit, and a level pull-down circuit 208. The level control circuit 204 includes transistors τι to τ3, nodes μ, ^, and a capacitor C. The powers of nodes Ρ2 and Ρ3 are defined as control signals Vc2(1) and Vc3(1), respectively. The transistors Τ2 and D3 are coupled to nodes P2 and P3, respectively, and the source (SGUIXe) receives low voltage vss. The inter-pole receives the signal. The towel input signal _ such as the pre-stage shift register saponin output scan signal SCCM), the transistor 12 and D 3 respond The high level scan Bauer SC㈣ turned in divided Vc2⑴ level and the control signal Vc3 (j) equal to the low voltage VSS. The terminal of the capacitor C receives the timing signal _, and the other end is coupled to the node P3. Capacitor C is used to store timing signal CLKB relative to node p3 1380275

TW4067PA voltage. The drain of the transistor T1 receives the high voltage VDD, the source is coupled to the point P2, the gate is coupled to the node P3, and the complex number na)i & YDD_〇-, the electric drive circuit 202 includes the electricity The crystals T4 to T6, wherein the transistor T4 has a pole and a gate coupled to each other to receive an input signal, and the source is coupled to the node < pi, and the voltage on the node pi is defined as a control signal Vcl(1). The electrical body T4 is responsive to the high level of the scan signal sc(j l) to turn on the signal Vc1(j) equal to the high level. Wherein, when 』 is not equal to ^, the wheel; the signal is the scan signal SCCM); when j is equal to i, the input signal is: STV. In the following description, the case where j is larger than i is taken as an example. The drains of the transistors T5 and T6 are coupled to the node P1, and the gates are respectively connected to the control signal Ve2(1) and the scan signal provided by the lower-stage shift register unit, SCCJ+1), and the source receives the low voltage vss. The transistors 15 and D6 are respectively turned on from the control signals Vc2(1) and sc(j+1) which are in response to the high level, so that the control signal Vcl(1) is equal to the low voltage vss. The pole level boosting circuit 2〇6 includes a transistor T7, wherein the transistor T7 turns out = the timing signal CLK, the gate is coupled to the node pl, and the source is coupled to the ^η terminal OUT. The output terminal 〇υτ is used to output a scanning signal 叱(1). The transistor input signal is turned on by the high level control signal VCl(1) so that ', (1) is as low as the timing signal CLK. Μ and bit = pull-down circuit 208 includes transistor D8 and Q' where the transistor is lightly connected to node OUT, and the gate receives control signals respectively 1380275 • »

TW4067PA

The Vc2(1) and the down-level front register unit provide the scan signal SC〇 + 1), and the source receives the low voltage VSS. The transistors T8 and T9 are respectively turned on in response to the high level control signals Vc2(1) and sc so that the known signal SC(1) is equal to the low voltage vss. Figures 5A to 5C show the timing diagrams of the related signals of the shift register unit s(1) of Figure 4. In the time period TP1, the scan signal scGd) and the timing signal CLKB are equal to the high voltage VDD, and the timing signal CLK and the scan §fl number SC(j+1) are equal to the low voltage VSS. At this time, the transistors T5, T6 and T9_ are turned off, the transistor T4 is turned on and the transistor T7 is turned on, so that the scanning signal SC(1) is equal to the timing signal CLK, which is equal to the low voltage vss. The transistor T4 satisfies the level of the control signal Vcl(1): Vcl(1) = VDD_Vth. The transistors T2 and T3 are turned "on" to cause the control signals vc2(1) and Vc3(j) to be equal to the low voltage VSS, respectively, to turn off the transistor T8. Where Vth is the threshold voltage of the transistor T4. At this time, the voltage across the capacitor c is substantially equal to the high voltage VDD. In the time period TP2, the timing signal CLK is boosted by the low voltage VSS equal to the rsj voltage VDD 'this huge voltage change will cause the voltage signal Vcl(j) to further boost a difference voltage AV due to the push-strapping effect. 'Making the voltage signal Vcl〇' satisfies: Vcl(1)=VDD-Vth+AV. In the present embodiment, the difference voltage Δν satisfies: av = Cgs {VDD - VSS) where Cgs is the internal parasitic capacitance of the transistor T7, and CP1 is the equivalent capacitance seen by the node P1. At this time, the control signals Vc2(j), Vc3〇) and the scanning signal SC(j+l) are both equal to the low voltage VSS to turn off the transistors T5, T6, T8 12 1380275 TW4067PA and T9. At this time, the scanning signal SC(1) is fast charging 炱 high voltage vdD, and the voltage across the capacitor C is substantially equal to zero.

In the time period TP3, the sweep signal sC(j+1) and the timing signal CLKB are close to the high voltage VDD, the sweep signal sc(j_!) and the timing signal CLk are equal to the low voltage vss, at this time, the electro-crystal title is 2~ 4 and T7 are off. (4) The rising edge of the sequence signal CLKB will charge the capacitor c, and the level of the control signal Vc3G) is substantially close to the level of the timing signal clKB, that is, the south voltage VDD' turns on the transistors D5 and D8. The worms 6 and T9 are also conducting 'at this time' the transistors Τ5 and τ6 quickly discharge the control signal Vcl(j) to the low voltage VSS' transistor τ8 and the τ9 system quickly scans the signal sc(1) to a low voltage. Vss. , : The month's participation, the 5th ′' is not the picture simulation of the control signals Μ(1) and Vc3(1) in Figure 4. In Fig. 4, the transistor τι~τ3 "" ratio (· Rati〇) is, for example, equal to 50/5, and the capacitance C is, for example, equal to 〇5 microfarads (Pw) m. It can be seen that the second register unit S(1) of the present embodiment is known. The control signal Vc2 (1) can be generated by the level control circuit in the timing cycle TP3. The conductive crystal scan signal SC(1) is equal to the low voltage vss, and the shift temporary unit is W. That is, in the timing period τρ3 When the thin circuit 204 of the present embodiment (1) is charged and discharged by the capacitor C and the timing signal = power is supplied to provide the f control signal % (1), the control signal is substantially reversed. The shift of the embodiment is known. Temporary crying scan signal sccm) (or start signal STV) to control & bit (1) access 204 operation. Thus, compared to the traditional shift register unit control, the local 13 TW4067PA instance shift The bit register unit S(1) can effectively reduce the circuit load of the control signal driving, so as to prevent the level of the control signal Vcl(1) from being too low (for example, lower than the voltage level: VDDVth), and avoiding and tracing. The level of SC(1) is too low (for example, below the voltage level VDD). The level control circuit 2 in the shift register unit S(j) interacts with the timing signal CLKB via the charging and discharging operation of the electric valley C. The deer scanning signal is called a control which is substantially opposite to each other (Vc2Cj). In the level control circuit 2G4, the transistor has the same aspect ratio. Thus, compared with the conventional shift register unit, the level control circuit of the I embodiment can avoid the conventional shift. In the temporary SR(8), the size of the transistor TBWC does not match, causing the transistor t to withstand excessive current and damage. In this implementation, only the shift register unit is used to shift the register unit. The operation of S(1) is taken as an example. However, the structure and operation of the shifting temporary storage 11 unit in t H4 can be obtained by analogy according to the shift temporary storage, single ^(1). τ according to Τ6: τί Γ example In the above, only the transistors T6 and T9 of the shift register unit S(1) are responsive to the τ-level shift temporary storage two-body signal SCCi+D to pull down the control signal Ertian shape as an example, narrow, m "(1) Knowing the heart of the tiger sc_ love one" and Ding 9 is not limited to return to the library in the lower-level shift (four) storage element s (four) ^ Next, for example, the shift register unit SQ is better known. In the register unit SG+2), v w, the J 2 level shift signal ve 丨 (1) paste == call = perform pull-down control (1) coupling. In other words, please refer to section 6 1380275

TW4067PA picture, the shift register unit s of the shift register 24', the control terminals RT of (1)~s, (n 2) can also respond to the shift register unit s, respectively (3) ) ~ Control signal Vci (3) ~ Vcl (n) to operate. Please refer to FIG. 7 , which is a detailed circuit diagram of the shift register unit s in FIG. 6 . In more detail, the signals received by the gates of transistors T6 and T9 are the control signals of shift register unit S, (j+2).

VclCj+2)' is the signal of the node ρι in the lower level shift register unit. In the present embodiment, 'there is only a case where the shift register Cuiyuan s(1) has a structure of π drawn in FIG. 4 as an example. However, the shifting temporary element S(1) is not limited to having the drawing shown in FIG. The structure is shifted, and the ^-element circuit can make other changes. For example, shifting the temporary sneak 兀 S (j) can also omit the transistor Τ 1 & Τ 2 of the second picture: (1) to the transistor τ5 and the transistor: order control ' as shown in Figure 8 . According to the mth figure, the control signal Vc is in the tank cycle time period TP3 by the low voltage two: voltage 雠. Therefore, the transistors Τ6 and D8 can respond to the high level control signal plus time in the time period ΤΡ3.

Vcl (1) and scan signal,) to low power a Qing. The control signal Ve2(1) in the mode is continuously maintained for one month and another voltage (as shown in FIG. 5B), for example, when the voltage is high: pressure, the control signal Vc2(1) is continuously controlled. To control the sweeping SC · low Mvss, _t = 15 1380275

The TW4067PA scg) is disturbed by noise, resulting in an error in the scanning operation of the scan driver to which the shift register 24 of the present embodiment is applied. However, the long-time conduction will make the threshold voltages of the crystals T5 and T8 easy to cause malfunction due to the stress effect (Stress screams and raises the malfunction (Malfunction^ The transistors T6 and T9 in this embodiment can be respectively used in the transistor D5 and D8). When the malfunction occurs, pull = (1) to the low voltage vss to avoid the level of the scan signal _ "longer t point. The shift register unit S(1) of this embodiment has the function of shifting the register unit separately with each register level. In the electric 曰 曰 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 各级 如此 如此 如此 如此 如此 如此 如此 如此The time required in the register unit, to avoid the need for each needle, the '" system number is converted to you', the silk thread is free of the corresponding level of the known signal, so the lead ^ ^ is too long to occur The error causes the shift register of the present application to be ft (four) crystal display (4). It has a different appearance than the 2, and it is too sturdy, and again, Wang Town has no picture quality. The charge and discharge operation and level controller are via the electrical unit. The shift of the present embodiment is temporarily inconsistent with the conventional shift temporary storage. And make the application for which: Transferred "* Single memory and the display of better surface quality advantages .ι day without & long life 1,380,275

TW4067PA An embodiment The shift register in this embodiment is applied to a bilateral scan driver. Fig. 9 is a block diagram showing a second embodiment of the present invention. The liquid crystal display 10 of the present embodiment is different from the first embodiment of the liquid crystal display 1G in that the scan driver 14 in the first embodiment is replaced by the scan driver 34. Scan driver 34 is a bilateral scan driver, which includes odd and even sequence scan drivers 34a and 34b. The odd-sequential scan driver 3 is configured to provide an odd number = a scan number SC (1), SC (3), ..., sc (four) to the display panel 16 via the scan line 33a; = a sequence scan driver 34b for providing via the scan line 33b The even sequence sweep = SC(2), SC(4), ..., SC(4) to the display panel 16, η, for example, the odd-sequence and even-sequence scan drivers 34a and 34b include shifts, registers 44a and 44b, respectively. Wherein, the shift register 4 and the servant have a structure and operation that are close to each other. Next, only the shift register 4 乜 = structure and operation are step-by-step description, and the shift is temporarily stored. The structure of the peach is similar to that of ', two = according to the description of the shift register 44a. 'Clock > ', '1', which is a block diagram of a shifting temporary in accordance with an embodiment of the present invention. The shift register 44a includes SH (= Sequential Shift Register Units SH(1), SH(3), SH(5), ...) in the scan driver 34 to dry out the odd-slot registers. The unit SH(1)~sound, for example, scans the signals sc(l)~sc(nl) respectively. The unit makes the shift register unit 1() in the (1)~qing11·1), SH(9). ....SH(n-3) timing terminal Cl receiving signal 娆CLK1, shift register unit SH(3), SH(7), 17

The timing terminal C1 of the TW4067PA TW4067PA SH(1)), ..., shw) receives the timing signal clk3. The control terminal RT of the shift register unit SH(1)~SH(n-3) respectively receives the voltage signal of the node NT1 of the shift register unit one SH(3)~SH(nl) as the control signal Vc 1 (1) to Vc 1 (η-1). The shift register unit SH(i)~SH(n_ι) has, for example, a similar structure and operation 'next to the i-th shift register unit in the shift register unit SH(1) to SH(nl) SH(i) is taken as an example to illustrate the operation of the shift register unit. Where i is an odd number less than or equal to η-I. Please refer to FIG. 11 and FIG. 12, FIG. 11 is a detailed circuit diagram of the i-th stage shift register unit SH(1) in FIG. 9, and FIG. 12 is a timing diagram of the related signal in FIG. The shift register unit sH(i) of the present embodiment is different from the shift register of the first embodiment by (1) in that the input signal received by the two ends of the pot is the scan signal sc (four) control terminal RT. To receive the control signal Vcl(i+2). The shift register unit SH(i) is different from the shift register of the first embodiment in that the timing signal (4) and the coffee 3 are at a high level to receive the timing signal received by the shift register unit. And CLKB is at a high level of time [two]. Thus, the shift temporary state is earlier το SH(1) is correspondingly still in the time/interval period, and TP2, in the eight-pass doubling time period TP1 and TP9 are The execution of the shift register unit s(1) is temporarily shifted by t 仃 。. In the time period TP3, in the time period =1, that is, in response to the high level of the control signal Vcl (4)) = binding and shifting temporary storage Unit S(j) is executed in time period τρ3

TW4067FA According to the operation diagram of shifting 2SH(1) in FIG. 11 and FIG. 12 and the second embodiment, it can be seen that the scanning signal of the present embodiment is improved to the corresponding one in the first embodiment. Scanning is: twice the time when ω is at a high level, and the scanning signals partially overlap each other. For example, the scan signal=secondary scan signal sc(i+l) is turned on during the second half of the time period TP2' (5) ,2, and the scan signal SC(i) and the scan signal SC(M) are in the time period τρ=, During the first half of the period, Τχ1 is conducting. Further, it can be seen that the liquid crystal display 10' of the present embodiment is substantially a liquid crystal display having a liquid crystal capacitor pre-charge function. For example, in the time period TP2, the i-th pixel a(1) and the i-th column pixel a(il) in the display panel 16 are turned on in response to the scan signals sc(i) and SCO·1, respectively. The first data output by the data driver 12 is the data of the m pixels to be written into the Mth column a (il). For the first column of alizarin a(i), the first data of the m-character is pre-charged data for precharging the pixel capacitors of the m pixels of the first column of alizarin a(1). In the period Tx2, the i-th pixel a(i+l) and the first column a(i) in the display panel 16 are turned on in response to the scanning signals sC(i+1)& sc(i), respectively. The second data of the output of the data driver 12 is the data of the m pixels of the i-th column. In this case, the m in the i-th column a(i) '分_Save m pen second data, and display the corresponding image screen for the 1+1 luminescence a (i + l), the second data of this m pen is pre-1380275

TW4067PA pre-charges the i+1th element a(i+1)<m pixels. '································································································· operating. 'In the present embodiment, only the shift register unit commits (1) to the L-th shift register unit SH(1) of the shift register * in the shift register * other stages of the shift register , ^ = shift temporary storage element ((4) axis! tT ί level shift register unit operation can be obtained according to the shift: second stolen shift shift temporary storage n SH (i) operation analogy. In this embodiment, the control signal 曰c, (1) and the scan signal SC(I) are pulled down in response to the control signal Vcl(i+2) only by the battery 6 and the shift register unit. The case is illustrated by way of example. However, the crystal and T9 are not limited to responding to the control signal %(4). In the present embodiment, only the shift register unit SH(i) is used. The case of the body W is exemplified as a case. However, the circuit of the shift temporary storage (1) is not limited thereto. For example, when shifting the register, the transistor T1 can be omitted as shown in FIG.设置 Set and control the operation of transistor τ directly with control signal Vc3(i). For a long time 6, similar to the shift register in the first embodiment, the local register can effectively reduce the material control in each shift register unit = shift 20 1380275 % l

TW4067PA signal-driven circuit load, shortening the time required for control signal level conversion, avoiding the level of each corresponding scan signal, thus the control signal level conversion time is too long and an error occurs, and the shift proposed by the present invention is applied. The liquid crystal display of the memory has better display quality. In addition, the shift register of the present embodiment also has a transistor size in the level control circuit - the size is matched, the transistor is not easily damaged, the shift register unit is less prone to malfunction, and the liquid crystal is applied. The display has a long service life and the advantages of better quality of the kneading surface. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is defined by the scope of the appended claims. 21 1380275

TW4067PA [Simple Description of the Drawing] Figure 1 shows the circuit diagram of the conventional shift register unit. Fig. 2 is a block diagram showing a liquid crystal display according to an embodiment of the present invention. Figure 3 is a block diagram of a shift register in accordance with an embodiment of the present invention. Fig. 4 is a detailed circuit diagram of the shift register unit S(1) in Fig. 3. • Figures 5A-5C show the timing diagrams of the associated signals for the shift register unit S(j) of Figure 4. FIG. 6 is another block diagram of the shift register of the embodiment. Fig. 7 is a circuit diagram showing another embodiment of the shift register unit of the embodiment. Fig. 8 is a circuit diagram showing still another embodiment of the shift register unit of the embodiment. Figure 9 is a block diagram of a liquid crystal display according to a second embodiment of the present invention. Figure 10 is a block diagram of a shift register in accordance with an embodiment of the present invention. Fig. 11 is a detailed circuit diagram showing the i-th stage shift register unit SH(i) in Fig. 9. Figure 12 is a timing diagram of the correlation signal of Figure 10. 22 1380275

TW4067PA [Explanation of main component symbols] SR(8), S(1)~S(n), S, (1)~S'(n), S"G), S"'(1), SH(1)~SH(k): Shift temporary storage Unit ΤΑ, TB, TC, T1 〜 T9, ΤΓ~T9,: transistor 10, 10': liquid crystal display 11: data line 12 · tribute drive benefit 13, 33a, 33b: scan line • 14, 34: scan Driver 24, 24', 44a, 44b: shift register 16: display panel a1~an: pixel IN: input terminal OUT: output terminal RT: control terminal

Cl, C2: timing terminal • C: capacitor

Cgs: parasitic capacitance 34a: odd-order shift register 34b: even-order shift register 23

Claims (1)

101 years. October 22, nuclear replacement 100 years. October 22 nuclear replacement replacement 2012/10/22_la Shen Fu & amendment application patent park: drive shifting temporary storage, for single-sided scanning The shift register temporary storage S includes a plurality of stage register units, and the output generates a first-time-n-th stage shift register unit for including a solid scan signal via a register unit. η is a natural number, the η-level shifting of the temporary control signal is enabled by the dry-capture circuit, in response to a first controller code being equal to - the first-order signal; The enablement bit name of the second control signal controls the knowledge signal to be equal to a first voltage; and controls the first drive circuit in response to an enable level of an input signal; ==::=:=r-bit potential-bit The quasi-control circuit is responsive to the enable level of the input signal to control the second control block to be a non-enabled level, and the second control signal is controlled to be the enable bit in response to the non-receiving b level of the input signal The quasi-control circuit includes: a first node, the voltage on the first node is a third control signal, the third control signal is related to the second control signal; a charge storage circuit, one end receives a second timing signal, and the other end is coupled Up to the first node, the charge storage circuit is configured to store the voltage of the second timing signal relative to the first node; and a first transistor, the gate receives the input signal, and the first source (Source) ) / / Drain (Drain) to the first node, the second source / 09712648 & • 〆- 〆 · 1013 | σ ^ 43-0 24 1380275 101. October Japanese nuclear replacement page 2012/10/ The second transistor receives the first voltage, and the first transistor provides the first voltage to the first node to disable the third control signal in response to the enable level of the input signal. 2. The shift register according to claim 1, wherein the level control circuit further comprises: a second node, the voltage on the second node is the second control signal; a crystal, the gate receives the input signal, the first source/drain is coupled to the second node, the second source/drain receives the first voltage, and the second transistor is responsive to the input signal Providing the first voltage to the second node to disable the second control signal; and a third transistor, the gate is coupled to the first node, and the first source/drain receives a second a second source/drain is coupled to the second node, the third transistor is responsive to the third control signal to provide the second voltage to the second node, thereby enabling the second control Signal. 3. The shift register according to claim 1, wherein the level pull-down circuit further comprises: a fourth transistor, the gate receiving the output of the n+1th shift register unit a scan signal, a first source/drain is coupled to the output, a second source/drain receives the first voltage, and the fourth transistor is responsive to the n+1th shift register The enabling level of the scanning signal output by the unit controls the scanning signal to be equal to the first voltage. 4. The shift register according to claim 1, wherein the level pull-down circuit further comprises: 037126.488· 10134Ό7.343-0 25 1380275 101. October 22 shuttle replacement page 2012/ 10/22_1Π Shen Fu & Amend a fourth transistor, the gate receives the first control signal in the n+2 stage shift register unit, and the first source/drain is coupled to the output terminal, The second source/drain receives the first voltage, and the fourth transistor is configured to respond to the enable level of the first control signal in the n+2 stage shift register unit, and control the scan signal to be equal to the The first voltage. 5. The shift register of claim 1, wherein the driving circuit further comprises: a third node, the voltage on the third node is equal to the first control signal; and a fifth transistor The gate receives the scan signal output by the n+1th shift register unit, the first source/drain is connected to the third node, and the second source/drain receives the first voltage. The fifth transistor is configured to control the first control signal to be equal to the first voltage in response to an enable level of the scan signal output by the n+1th shift register unit. 6. The shift register of claim 1, wherein the driving circuit further comprises: a third node, the voltage on the third node is equal to the first control signal; and a fifth transistor The gate receives the first control signal in the n+2th stage shift register unit, the first source/drain is coupled to the third node, and the second source/drain receives the first voltage. The fifth transistor is configured to control the first control signal to be equal to the first voltage in response to an enable level of the first control signal in the n+2th stage shift register unit. 7. The shift register as described in claim 1 wherein: 1:013?〇7.343-〇09712 6*4 8& 26 the replacement of the page drive circuit after October 2, 101 includes: 2012/10/22_1"Shen Fu&corrects a third node, the third node number; *Electricity is equal to the first control signal, a sixth transistor, gate and first number, second source/汲The pole is coupled to the second diode and receives the input signal, and the gate receives the first and the second poles, and the first source voltage is coupled to the third rib. . The second source/drain receives the shift described in item 1 of the first level range, wherein the second/sequence: the first control signal, the first-source terminal. 4, the first source/drain is coupled to the output level lowering 2 & the shift register according to item 1, wherein the (10) terminal is closed = two control signals, and the first source is 10. f - secret recording (four) - voltage. The input signal is the number of the first shift register as described in item i of the scope of the patent. 3 / n-1th level shift register unit output scan message you touch a shift register (ShiftRegi_ ' applied to a display surface two trace driver, the shift register includes a complex odd number The stage is 7 〇 and the complex even-numbered shift register unit, and the odd-numbered, and the even-numbered shift register units are respectively located on the display panel of the two. 097126.488 1013^07343-0 27 22 8 mmwj On the opposite side, the shifting buffers _ 2ω·/22_〗 "Shen Fu & correction to connect through an output: early ^ 1st level 11 shift register unit with stage shift register The unit scoop is a scanning signal, and 11 is a natural number. The η-th order quasi-boosting circuit controls the scanning signal to be equal to an enable level of the first control signal-level low-lowering circuit timing signal; controlling the scanning The second control signal of the signal is capable of a driving circuit, and the control signal is an enabling level of the enabling signal. The first control signal is a non-enabled level; and 9 The -2 control 1 circuit 'responds to the enable level control of the input signal: two The non-enabled level 'responds to the non-receiving level of the input signal to control the second control signal to be Wei level; wherein the level control circuit comprises: ^ the first node, the voltage on the first node is one a third control signal, the third signal is related to the second control signal; a charge storage circuit, one end receives a second timing signal, and the other end is connected to the first node, the charge storage circuit is used for Storing the voltage of the second timing signal relative to the first node; and a first transistor, the gate receives the input signal, and the first source/drain is coupled to the first a first source, the second source/drain receives the first voltage, and the first transistor provides the first voltage to the first node to disable the third control signal in response to an enable level of the input signal 097.12 6.4 88, 10134073, 43-0 28 1380275 October 2, 2010, the nuclear replacement page 2012/10/22_lst Shen Fu & Amendment 12. The position register as described in claim 11 Wherein the level control circuit further comprises: a second node The voltage on the second node is the second control signal; a second transistor, the gate receives the input signal, the first source/drain is coupled to the second node, and the second source/drain receives The first voltage, the second transistor provides the first voltage to the second node to disable the second control signal in response to the enable level of the input signal; and a third transistor coupled to the gate Up to the first node, the first source/drain receives a second voltage, the second source/drain is coupled to the second node, and the third transistor is responsive to the third control signal to provide The second voltage is applied to the second node to enable the second control signal. 13. The shift register of claim 11, wherein the level pull-down circuit further comprises: a fourth transistor, the gate receiving the n+2th shift register unit a control signal, a first source/drain is coupled to the output, a second source/drain receives the first voltage, and the fourth transistor is responsive to the n+2th shift register The enabling level of the first control signal in the unit controls the scanning signal to be equal to the first voltage. 14. The shift register of claim 11, wherein the driving circuit further comprises: a third node, the voltage on the third node is equal to the first control signal; and a fifth transistor , the gate receives the n+2 shift register unit. .09712 64 8& 1Ό134Ό7.343—0 • Fang· 29 1380275 101. October 22 revised replacement π 2012yi0/22_la Shen Fu & Amendment a first control signal, a first source/drain is coupled to the third node, a second source/drain receives the first voltage, and the fifth transistor is responsive to each n+2th shift The enabling level of the first control signal in the register unit controls the first control signal to be equal to the first voltage. 15. The shift register of claim 11, wherein the scan signal provided by the bilateral scan driver is a pre-charge scan signal. 16. The shift register of claim 11, wherein the driving circuit comprises: a third node, a voltage on the third node is equal to the first control signal; a sixth transistor, a gate The first source/drain receives the input signal, the second source/drain is coupled to the third node, and a seventh transistor, the gate receives the second control signal, the first source/ The drain receiving is coupled to the third node, and the second source/drain receives the first voltage. 17. The shift register of claim 11, wherein the level boosting circuit comprises: an eighth transistor, the gate receiving the first control signal, and the first source/drain receiving The first timing signal, the second source/drain is coupled to the output. 18. The shift register of claim 11, wherein the level pull-down circuit comprises: a ninth transistor, the gate receiving the second control signal, the first source 097126488.* - · · 1013:^7543-0 30 1380275 101. October 22 revision replacement page 2012/10/22_lst series complex & correction / drain is coupled to the output, the second source / drain receives the first A voltage. 19. The shift register of claim 11, wherein the input signal is a scan signal output by the n-2th stage shift register. 097126488 10134; 〇7343-0