CN104122724A - Low-color-error liquid crystal array substrate and drive method thereof - Google Patents
Low-color-error liquid crystal array substrate and drive method thereof Download PDFInfo
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- CN104122724A CN104122724A CN201410318192.0A CN201410318192A CN104122724A CN 104122724 A CN104122724 A CN 104122724A CN 201410318192 A CN201410318192 A CN 201410318192A CN 104122724 A CN104122724 A CN 104122724A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000010408 film Substances 0.000 claims description 27
- 238000007667 floating Methods 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 230000000007 visual effect Effects 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 208000025165 Autoerythrocyte sensitization syndrome Diseases 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
The invention relates to a low-color-error liquid crystal array substrate and a corresponding drive method. The low-color-error liquid crystal array substrate comprises a plurality of pixel structures, each pixel structure comprises a primary pixel area and a secondary pixel area, a gate line is arranged between each primary pixel area and the corresponding secondary pixel area and is provided with a first thin film transistor and a second thin film transistor which are connected to the primary pixel area and the secondary pixel area respectively, the position between each gate line and the corresponding secondary pixel area further comprises a public electrode wire and a metal component, each public electrode wire is provided with a standoff capacitor, and each metal component is provided with a share thin film transistor connected with the corresponding standoff capacitor and electrically connected with a data line through a through hole. Through the design of omitting a sub gate line, switches of the share thin film transistors are switched on directly through signal voltage of the data lines; the inconformity of voltage between each primary pixel area and the corresponding secondary pixel area is solved by adjusting the gate source capacitance of the thin film transistor in the primary pixel area, the aperture opening ratio is improved, and the processing cost is lowered.
Description
Technical field
The present invention relates to low colour cast liquid crystal array substrate and corresponding driving method thereof, particularly relate to a kind of dot structure that omits sub-grid line.
Background technology
Along with the development of information society, people raise year by year to the demand of display device, thereby promote the fast development of liquid crystal panel, the size of panel is also done larger and larger, especially also more and more higher to the requirement such as wide viewing angle, low energy consumption, therefore the dot structure of thin film transistor (TFT) (TFT) device and liquid crystal panel designs also towards diversified development.
General liquid crystal electron device all has the display mode of wide viewing angle, under the display mode of wide viewing angle, because the liquid crystal molecule of observing in different visual angles points to difference, results in the cross-color of observing down with great visual angle.At present, in order to improve cross-color with great visual angle, in the time that designing, dot structure a dot structure can be divided into He Ci pixel region, main pixel region two parts, and reduce the voltage of time pixel region by shared thin film transistor (TFT) and OFF state electric capacity, thereby the liquid crystal rotation amount of controlling He Ci pixel region, main pixel region is poor, to improve the phenomenon of cross-color under wide viewing angle.And the above-mentioned design that dot structure is divided into main pixel region and inferior pixel region is commonly referred to as low colour cast design (Low Color Shift, LCS).
Fig. 1 shows the dot structure schematic diagram of prior art, this dot structure includes 11He Ci pixel region, main pixel region 12, be connected in the first film transistor 13 of main pixel region 11, be connected in the second thin film transistor (TFT) 14 of time pixel region 12, share thin film transistor (TFT) 15, main grid line 16 (main gate line), sub-grid line 17 (sub gate line), common electrode 18, OFF state (Cdown) electric capacity 19, and the critical component such as shared thin film transistor (TFT) 15, the switch of wherein sharing thin film transistor (TFT) 15 is controlled by sub-grid line 17, and N root grid line and N+1 or N+2 or N+3 or N+4 root main grid line link together.
The defect of above-mentioned design is, sub-grid line 17 can increase the overlapping area with data line 20, not only affects the aperture opening ratio of pixel, also causes short circuit (Gate-Drain Short between grid line and data line 20, GDS) Probability increases, and the cost of joint product manufacture significantly rises.Therefore, be necessary to provide a kind of dot structure, to solve the existing problem of prior art.
Summary of the invention
The object of the present invention is to provide a kind of technical scheme of low colour cast liquid crystal array substrate, by omitting sub-grid line, reduce bad short circuit phenomenon and occur, and then capable of increasing opening rate and cost-saving.
For reaching aforementioned object of the present invention, the invention provides a kind of prior art that is different from uses two grid lines to realize the design of low colour cast array base palte, liquid crystal array substrate of the present invention comprises multiple dot structures, each dot structure comprises a main pixel region and a pixel region, described main pixel region and described pixel range are provided with a grid line, described grid line connects respectively a first film transistor and one second thin film transistor (TFT), and at least one data line is connected to described the first film transistor and the second thin film transistor (TFT), wherein said grid line and described pixel range also comprise: altogether by electrode wires, be provided with an OFF state electric capacity, and a metal parts, be provided with one and share thin film transistor (TFT) and be connected with described OFF state electric capacity, and pass through a through hole and be electrically connected with described data line.
In liquid crystal array substrate of the present invention, the switch of described shared thin film transistor (TFT) can directly be controlled by described data line.
In liquid crystal array substrate of the present invention, described the first film transistor has a first grid source capacitance, and described the second thin film transistor (TFT) has a second gate source capacitance, and described first grid source capacitance is greater than described second gate source capacitance.
In liquid crystal array substrate of the present invention, described metal parts is a floating dam.
Another object of the present invention is to provide a kind of driving method of liquid crystal array substrate, by omitting sub-grid line, directly drive and share thin film transistor (TFT) to reduce bad short circuit phenomenon generation with data line, and then capable of increasing opening rate and cost-saving.
For solving the problems of the technologies described above, the invention provides a kind of driving method of liquid crystal array substrate, described liquid crystal array substrate comprises multiple dot structures, each dot structure comprises a main pixel region and a pixel region, described main pixel region and described pixel range are provided with a grid line, described grid line connects respectively a first film transistor and one second thin film transistor (TFT), and at least one data line is connected to described the first film transistor and the second thin film transistor (TFT), described grid line and described pixel range also comprise altogether by electrode wires, be provided with an OFF state electric capacity, and one first metal portion, being provided with one and sharing thin film transistor (TFT), wherein said grid line produces a voltage signal for controlling the switch of described the first film transistor and one second thin film transistor (TFT), described shared thin film transistor (TFT) is electrically connected with described data line by a through hole, and described data line produces a voltage signal for controlling the switch of described shared thin film transistor (TFT).
Described in driving method of the present invention, share thin film transistor (TFT) and be connected with described OFF state electric capacity, in the time of described shared thin film transistor (TFT) conducting, an electric charge of described pixel region is discharged into described OFF state electric capacity.
In driving method of the present invention, described the first film transistor has a first grid source capacitance, and described the second thin film transistor (TFT) has a second gate source capacitance, and described first grid source capacitance is greater than described second gate source capacitance.
In driving method of the present invention, described metal parts is a floating dam.
In driving method of the present invention, the voltage of described data line is 0.2 volt or 14.2 volts in the time of white picture.
In driving method of the present invention, the voltage of described data line is 7.7 volts or 7.2 volts in the time of black picture.
The present invention is by omitting the setting of sub-grid line, directly share the switch of thin film transistor (TFT) with data line control, and by being the grid source electric capacity that is greater than thin film transistor (TFT) in inferior pixel region by the grid source capacitor design of thin film transistor (TFT) in main pixel region, to adjust the voltage difference between Yu Ci pixel region, main pixel region, make the voltage between Yu Ci pixel region, main pixel region consistent.
Under design of the present invention, can omit sub-grid line, the overlapping part of reduction and data line and metal parts, reduces the generation of the bad incidence of GDS, realizes the display effect of low colour cast, i.e. the energy-conservation cost of saving again in the situation that not reducing pixel aperture ratio.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate appended diagram, be described below in detail:
Brief description of the drawings
Fig. 1 is the dot structure schematic diagram of prior art.
Fig. 2 illustrates dot structure schematic diagram of the present invention.
Fig. 3 is the diagrammatic cross-section that label in Fig. 2 " 50 " is located.
Embodiment
The explanation of following embodiment is graphic with reference to what add, can be in order to the specific embodiment of implementing in order to illustrate the present invention.The direction term that the present invention mentions, for example " on ", D score, 'fornt', 'back', " left side ", " right side ", " interior ", " outward ", " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to illustrate and to understand the present invention, but not in order to limit the present invention.In the drawings, the unit of structural similarity is to represent with same numeral.
Liquid crystal array substrate of the present invention comprises multiple dot structures, Fig. 2 illustrates each dot structure schematic diagram, each dot structure comprises a main pixel region 31 and one pixel region 32, between described main pixel region 31 and described pixel region 32, be provided with a grid line 36, described grid line 36 is electrically connected respectively the grid level of a first film transistor 33 and one second thin film transistor (TFT) 34, and at least one data line is connected to the source class of described the first film transistor 33 and the second thin film transistor (TFT) 34, the drain electrode of described the first film transistor 33 and the second thin film transistor (TFT) 34 is connected to described main pixel region 31 and described pixel region 32, for controlling the demonstration of main pixel region 31 and inferior pixel region 32.Between described grid line 36 and described pixel region 32, also comprise: be provided with an OFF state electric capacity 38 with electrode wires 37 and described common electrode line 37 altogether, an and metal parts 39, be provided with a shared thin film transistor (TFT) 35 and described shared thin film transistor (TFT) 35 for being electrically connected with described OFF state electric capacity 38, and be electrically connected with described data line 40 by a through hole 41.
In an embodiment of the present invention, described grid line 36, through hole 41, metal parts 39 and common electrode line 37 are all a first metal layer, can be formed on liquid crystal array substrate simultaneously, 40 of described data lines are one second metal level, after being formed at described the first metal layer, and there is part to overlap with described grid line 36 and through hole 41.
In an embodiment of the present invention, the electrode of Yu Ci pixel region, described main pixel region is transparency conductive electrode, is preferably tin indium oxide (ITO).
In an embodiment of the present invention, described metal parts 39 is a floating dam.
Please refer to diagram 3, diagram 3 is for the present invention illustrates the diagrammatic cross-section that label in 2 " 50 " is located, and wherein, 39 is metal parts, namely the first metal layer, and it can be a floating dam; 51 is grid-silicon nitride layer (Gate-SiNx); 40 is data line, namely the second metal level; 52 is silicon nitride passivation (Passivation-SiNx).Therefore, described metal parts 39 produces electrical connection by through hole 41 and data line 40,40.
And the voltage of general data line is all positive-negative half-cycle alternating voltage, for example, the voltage in the time of white picture is 0.2 volt or 14.2 volts, and the voltage in the time of black picture is 7.7 volts or 7.2 volts.The electric current of the existing amorphous silicon of foundation, to voltage curve (I-V Curve) characteristic, can be opened the switch of sharing thin film transistor (TFT) 35 for above-mentioned 7.2 volts, 7.7 volts and 14.2 volts.
Therefore, be different from the sub-grid line of prior art and control the switch of sharing thin film transistor (TFT), in an embodiment of the present invention, sharing the switch of thin film transistor (TFT) 35 can directly be controlled by data line 40, namely utilize the signal voltage of data line 40 to open the switch of the shared thin film transistor (TFT) 35 of amorphous silicon, make the electric charge of time pixel region 32 can be released into OFF state electric capacity 38, reach the display effect of low colour cast.
Because the voltage of above-mentioned data line 40 has approached threshold voltage (Vth) 0.2 volt time, the switch of sharing thin film transistor (TFT) 35 is considered as not opening, therefore under white picture, positive-negative half-cycle is shared the degree difference that thin film transistor (TFT) 35 is opened, the electric charge that inferior pixel region 32 discharges is also different, cause the positive half cycle voltage drop of time pixel region 32, the voltage of negative half period also and then declines, thereby its best share voltage (Best Vcom) also needs downward adjustment.
Therefore, in order to make the best share voltage of 31Yu Ci pixel region, winner pixel region 32 consistent, in an embodiment of the present invention, visual actual state the grid source electric capacity (Cgs) of thin film transistor (TFT) 33 in main pixel region 31 design more greatly, the best share voltage of main pixel region 31 is pulled down to consistent with the best share voltage of inferior pixel region 32 by leaping voltage (Δ Vp).That is to say, make the first grid source capacitance of the first film transistor 33 in main pixel region 31 be greater than the second gate source capacitance of the second thin film transistor (TFT) 34 in inferior pixel region 32, while controlling shared thin film transistor (TFT) 35 to improve by data line 40, be offset (Best Vcom Shift) phenomenons because of the different caused best share voltage of data line positive-negative half-cycle opening degree.
By above-mentioned dot structure design, the present invention can omit the configuration of sub-grid line, directly open with the signal voltage of data line control the switch of sharing thin film transistor (TFT), and utilize the grid source electric capacity of adjusting thin film transistor (TFT) in main pixel region to improve the voltage inconsistence problems between Yu Ci pixel region, main pixel region.Therefore, not only can reduce overlapping part, capable of increasing opening rate between data line and grid line, also can reduce the cost of overall process.
The invention still further relates to a kind of driving method of liquid crystal array substrate, described liquid crystal array substrate comprises: described display panels comprises multiple dot structures, each dot structure comprises a main pixel region 31 and a pixel region 32, between described main pixel region 31 and described pixel region 32, be provided with a grid line 36, described grid line 36 is electrically connected respectively a first film transistor 33 and one second thin film transistor (TFT) 34, described the first film transistor 33 and the second thin film transistor (TFT) 34 are connected to described main pixel region 31 and described pixel region 32, for controlling the demonstration of main pixel region 31 and inferior pixel region 32, between wherein said grid line 36 and described pixel region 32, also comprise: altogether by electrode wires 37, be provided with an OFF state electric capacity 38, and one first metal portion 39, be provided with one and share thin film transistor (TFT) 35.
In an embodiment of the present invention, described metal parts 39 is a floating dam.
In an embodiment of the present invention, the electrode of 31Yu Ci pixel region, described main pixel region 32 is transparency conductive electrode, is preferably tin indium oxide (ITO).
In an embodiment of the present invention, described grid line 36 for generation of open or the voltage signal of closing to the first film transistor 33, for controlling the switch of the first film transistor 33, the drain electrode of the first film transistor 33 is connected in the first pixel region 31, the source electrode of the first film transistor 33 is connected in data line 40, described data line 40 is inputted data drive signal in the time of 33 conducting of the first film transistor, thereby controls the demonstration of main pixel region 31.
In an embodiment of the present invention, described grid line 36 is given the second thin film transistor (TFT) 34 for generation of the voltage signal of opening or close, for controlling the switch of the second thin film transistor (TFT) 34, the drain electrode of the second thin film transistor (TFT) 34 is connected in the second pixel region 32, the source electrode of the second thin film transistor (TFT) 34 is connected in data line 40, described data line 40 is inputted data drive signal in the time of the second thin film transistor (TFT) 34 conducting, thereby controls the demonstration of time pixel region 32.
Because the voltage of general data line is all positive-negative half-cycle alternating voltage, for example, the voltage in the time of white picture is 0.2 volt or 14.2 volts, and the voltage in the time of black picture is 7.7 volts or 7.2 volts.The characteristic of the electric current of the existing amorphous silicon of foundation to voltage curve (I-V Curve), all can open the switch of described shared thin film transistor (TFT) 35 for above-mentioned 7.2 volts, 7.7 volts and 14.2 volts.
Therefore, in one embodiment of this invention, the switch of described shared thin film transistor (TFT) 35 can directly be controlled by described data line 40, namely described shared thin film transistor (TFT) 35 is electrically connected with data line 40 by a through hole 41, utilizes the voltage signal of data line 40 to open the switch of the shared thin film transistor (TFT) 35 of amorphous silicon.
In an embodiment of the present invention, described shared thin film transistor (TFT) 35 is connected with OFF state electric capacity 38, and therefore in the time of described shared thin film transistor (TFT) 35 conducting, the electric charge of inferior pixel region 32 is discharged into described OFF state electric capacity 38 and reaches the effect of low colour cast.
In an embodiment of the present invention, the voltage of described data line is 0.2 volt or 14.2 volts in the time of white picture.
In an embodiment of the present invention, the voltage of art data line is 7.7 volts or 7.2 volts in the time of black picture.
Because the voltage of above-mentioned data line 40 has approached threshold voltage 0.2 volt time, the switch of sharing thin film transistor (TFT) 35 is considered as not opening, therefore under white picture, positive-negative half-cycle is shared the degree difference that thin film transistor (TFT) 35 is opened, the electric charge that inferior pixel region 32 discharges is also different, cause the positive half cycle voltage drop of time pixel region 32, the voltage of negative half period also declines, thereby its best share voltage also needs downward adjustment.
Therefore, in order to make the best share voltage of 31Yu Ci pixel region, winner pixel region 32 consistent, in an embodiment of the present invention, visual actual state the grid source capacitor design of thin film transistor (TFT) 33 in main pixel region 31 more greatly, the best share voltage of main pixel region 31 is pulled down to consistent with the best share voltage of inferior pixel region 32 by leaping voltage.That is to say, make the first grid source capacitance of the first film transistor 33 in main pixel region 31 be greater than the second gate source capacitance of the second thin film transistor (TFT) 34 in time pixel region 32, control while sharing thin film transistor (TFT) 35 because the different caused best share voltage shift phenomenons of data line positive-negative half-cycle opening degree to improve by data line 40.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is not in order to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various changes and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. a liquid crystal array substrate, comprise multiple dot structures, each dot structure comprises a main pixel region and a pixel region, described main pixel region and described pixel range are provided with a grid line, described grid line connects respectively a first film transistor and one second thin film transistor (TFT), and at least one data line is connected to described the first film transistor and the second thin film transistor (TFT), it is characterized in that, described grid line and described pixel range also comprise:
By electrode wires, be provided with an OFF state electric capacity altogether; And
One metal parts, is provided with a shared thin film transistor (TFT) and is connected with described OFF state electric capacity, and be electrically connected with described data line by a through hole.
2. liquid crystal array substrate according to claim 1, is characterized in that, the switch of described shared thin film transistor (TFT) is controlled by described data line.
3. liquid crystal array substrate according to claim 1, it is characterized in that, described the first film transistor has a first grid source capacitance, and described the second thin film transistor (TFT) has a second gate source capacitance, and described first grid source capacitance is greater than described second gate source capacitance.
4. liquid crystal array substrate according to claim 1, is characterized in that, described metal parts is a floating dam.
5. the driving method of a liquid crystal array substrate, described liquid crystal array substrate comprises multiple dot structures, each dot structure comprises a main pixel region and a pixel region, described main pixel region and described pixel range are provided with a grid line, described grid line connects respectively a first film transistor and one second thin film transistor (TFT), and at least one data line is connected to described the first film transistor and the second thin film transistor (TFT), described grid line and described pixel range also comprise altogether by electrode wires, be provided with an OFF state electric capacity, and one first metal portion, be provided with one and share thin film transistor (TFT), it is characterized in that: described grid line produces a voltage signal for controlling the switch of described the first film transistor and one second thin film transistor (TFT),
Described shared thin film transistor (TFT) is electrically connected with described data line by a through hole, and described data line produces a voltage signal for controlling the switch of described shared thin film transistor (TFT).
6. driving method according to claim 5, is characterized in that, described shared thin film transistor (TFT) is connected with described OFF state electric capacity, and in the time of described shared thin film transistor (TFT) conducting, an electric charge of described pixel region is discharged into described OFF state electric capacity.
7. driving method according to claim 5, it is characterized in that, described the first film transistor has a first grid source capacitance, and described the second thin film transistor (TFT) has a second gate source capacitance, and described first grid source capacitance is greater than described second gate source capacitance.
8. driving method according to claim 5, is characterized in that, described metal parts is a floating dam.
9. driving method according to claim 5, is characterized in that, the voltage of described data line is 0.2 volt or 14.2 volts in the time of white picture.
10. driving method according to claim 5, is characterized in that, the voltage of described data line is 7.7 volts or 7.2 volts in the time of black picture.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410318192.0A CN104122724B (en) | 2014-07-04 | 2014-07-04 | Low-color-error liquid crystal array substrate and drive method thereof |
| PCT/CN2014/084238 WO2016000296A1 (en) | 2014-07-04 | 2014-08-13 | Low color washout liquid crystal array substrate and driving method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410318192.0A CN104122724B (en) | 2014-07-04 | 2014-07-04 | Low-color-error liquid crystal array substrate and drive method thereof |
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| Publication Number | Publication Date |
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| CN104122724A true CN104122724A (en) | 2014-10-29 |
| CN104122724B CN104122724B (en) | 2017-01-18 |
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| WO (1) | WO2016000296A1 (en) |
Cited By (8)
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| CN104503158A (en) * | 2014-12-17 | 2015-04-08 | 深圳市华星光电技术有限公司 | Array baseplate, liquid crystal display panel and detection method of liquid crystal display panel |
| CN105093756A (en) * | 2015-08-31 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display pixel structure and manufacturing method thereof |
| CN105159002A (en) * | 2015-09-18 | 2015-12-16 | 友达光电股份有限公司 | Pixel structure |
| CN106773408A (en) * | 2016-12-29 | 2017-05-31 | 深圳市华星光电技术有限公司 | Dot structure and liquid crystal display panel |
| WO2019127692A1 (en) * | 2017-12-26 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | Coa type array substrate and display panel |
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| WO2021164060A1 (en) * | 2020-02-21 | 2021-08-26 | Tcl华星光电技术有限公司 | Pixel structure, pixel circuit, and display panel |
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| CN113219747B (en) * | 2021-04-23 | 2022-11-08 | 成都中电熊猫显示科技有限公司 | Array substrate, liquid crystal display panel and liquid crystal display |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1825172A (en) * | 2005-02-24 | 2006-08-30 | 三星电子株式会社 | Array substrate, method of manufacturing the same, display panel having the same, and liquid crystal display apparatus |
| CN101216645A (en) * | 2008-01-04 | 2008-07-09 | 昆山龙腾光电有限公司 | Low color error liquid crystal display and its driving method |
| CN101625489A (en) * | 2008-07-11 | 2010-01-13 | 奇美电子股份有限公司 | Liquid crystal display panel and drive method thereof |
| CN101718934A (en) * | 2009-12-28 | 2010-06-02 | 友达光电股份有限公司 | Display and photoelectric device thereof |
| US20120033148A1 (en) * | 2010-08-06 | 2012-02-09 | Samsung Electronics Co., Ltd. | Liquid crystal display |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI363917B (en) * | 2008-02-01 | 2012-05-11 | Au Optronics Corp | Thin film transistor array substrate |
| CN201314993Y (en) * | 2008-12-18 | 2009-09-23 | 上海广电光电子有限公司 | LCD device in polydomain vertical alignment mode |
| US8854561B2 (en) * | 2009-11-13 | 2014-10-07 | Au Optronics Corporation | Liquid crystal display panel with charge sharing scheme |
| KR101793176B1 (en) * | 2010-08-05 | 2017-11-03 | 삼성디스플레이 주식회사 | Display device |
| CN103235428B (en) * | 2013-05-06 | 2015-08-12 | 深圳市华星光电技术有限公司 | The dim spot restorative procedure of liquid crystal panel and liquid crystal panel |
| CN103400563B (en) * | 2013-08-15 | 2015-04-15 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
-
2014
- 2014-07-04 CN CN201410318192.0A patent/CN104122724B/en not_active Expired - Fee Related
- 2014-08-13 WO PCT/CN2014/084238 patent/WO2016000296A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1825172A (en) * | 2005-02-24 | 2006-08-30 | 三星电子株式会社 | Array substrate, method of manufacturing the same, display panel having the same, and liquid crystal display apparatus |
| CN101216645A (en) * | 2008-01-04 | 2008-07-09 | 昆山龙腾光电有限公司 | Low color error liquid crystal display and its driving method |
| CN101625489A (en) * | 2008-07-11 | 2010-01-13 | 奇美电子股份有限公司 | Liquid crystal display panel and drive method thereof |
| CN101718934A (en) * | 2009-12-28 | 2010-06-02 | 友达光电股份有限公司 | Display and photoelectric device thereof |
| US20120033148A1 (en) * | 2010-08-06 | 2012-02-09 | Samsung Electronics Co., Ltd. | Liquid crystal display |
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| CN104503158B (en) * | 2014-12-17 | 2017-04-19 | 深圳市华星光电技术有限公司 | Array baseplate, liquid crystal display panel and detection method of liquid crystal display panel |
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| CN105093756A (en) * | 2015-08-31 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display pixel structure and manufacturing method thereof |
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| WO2021164060A1 (en) * | 2020-02-21 | 2021-08-26 | Tcl华星光电技术有限公司 | Pixel structure, pixel circuit, and display panel |
| CN112068371A (en) * | 2020-09-10 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| WO2022052242A1 (en) * | 2020-09-10 | 2022-03-17 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| Publication number | Publication date |
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| WO2016000296A1 (en) | 2016-01-07 |
| CN104122724B (en) | 2017-01-18 |
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